Re: [PATCH 1/3] dt-bindings: display: msm: mdss-common: describe additional block resets

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] dt-bindings: display: msm: misdescribed MDSS_CORE_INT2 reset in
  mdss-common
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commit 022650a3f28469dcfe73a6138dee6ab78a21185f
Author: Qianhui Xu <xiaqinghuan@mail.ustc.edu.cn>

dt-bindings: display: msm: mdss-common: describe additional block resets

This commit updates the common MDSS Device Tree binding schema to allow a
second reset entry and adds DISP_CC_MDSS_CORE_INT2_BCR to the SM8750 MDSS
binding example.

> diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> index c6305a6e03346..51ef4cc74e818 100644
> --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml
> @@ -84,8 +84,10 @@ properties:
>            - const: cpu-cfg
>  
>    resets:
> +    minItems: 1
>      items:
> -      - description: MDSS_CORE reset
> +      - description: MDSS core reset
> +      - description: MDSS core INT2 interrupt controller reset

[Severity: Low]
Is "MDSS core INT2 interrupt controller reset" an accurate description of
DISP_CC_MDSS_CORE_INT2_BCR in the binding and commit message?

In drivers/clk/qcom/dispcc-sm8750.c, DISP_CC_MDSS_CORE_INT2_BCR (0xa000) is
paired with MDSS_INT2_GDSC (0xb000) and controls the secondary internal MDSS
core clock and power domain (disp_cc_mdss_mdp1_clk,
disp_cc_mdss_mdp_lut1_clk, disp_cc_mdss_vsync1_clk and
disp_cc_mdss_ahb1_clk), while the MDSS interrupt controller registers reside
in the primary MDSS core MMIO space.  Later in the series, commit "arm64: dts:
qcom: sm8750: describe the second MDSS block reset" already describes
DISP_CC_MDSS_CORE_INT2_BCR as belonging to the mdss_int2_gdsc and *1_clk
domain rather than an interrupt controller.

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Sashiko AI review · https://sashiko.dev/#/patchset/20261113155606.1677313-1-xiaqinghuan@mail.ustc.edu.cn?part=1