Re: [PATCH v2 08/11] PCI/IDE: Add IDE establishment helpers

[Aneesh Kumar K.V <aneesh.kumar@kernel.org>]

Dan Williams <dan.j.williams@intel.com> writes:

> There are two components to establishing an encrypted link, provisioning
> the stream in Partner Port config-space, and programming the keys into
> the link layer via IDE_KM (IDE Key Management). This new library,
> drivers/pci/ide.c, enables the former. IDE_KM, via a TSM low-level
> driver, is saved for later.
>
....

> +/**
> + * pci_ide_stream_setup() - program settings to Selective IDE Stream registers
> + * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port
> + * @ide: registered IDE settings descriptor
> + *
> + * When @pdev is a PCI_EXP_TYPE_ENDPOINT then the PCI_IDE_EP partner
> + * settings are written to @pdev's Selective IDE Stream register block,
> + * and when @pdev is a PCI_EXP_TYPE_ROOT_PORT, the PCI_IDE_RP settings
> + * are selected.
> + */
> +void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
> +{
> +	struct pci_ide_partner *settings = to_settings(pdev, ide);
> +	int pos;
> +	u32 val;
> +
> +	if (!settings)
> +		return;
> +
> +	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
> +			     pdev->nr_ide_mem);
>

This and the similar offset caclulation below needs the EXT_CAP_ID_IDE offset 

modified   drivers/pci/ide.c
@@ -10,11 +10,13 @@
 #include <linux/bitfield.h>
 #include "pci.h"
 
-static int sel_ide_offset(int nr_link_ide, int stream_index, int nr_ide_mem)
+static int sel_ide_offset(struct pci_dev *pdev, int nr_link_ide,
+			  int stream_index, int nr_ide_mem)
 {
 	int offset;
 
-	offset = PCI_IDE_LINK_STREAM_0 + nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE;
+	offset = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_IDE);
+	offset += PCI_IDE_LINK_STREAM_0 + nr_link_ide * PCI_IDE_LINK_BLOCK_SIZE;
 
 	/*
 	 * Assume a constant number of address association resources per
@@ -66,7 +68,7 @@ void pci_ide_init(struct pci_dev *pdev)
 	nr_streams = min(1 + FIELD_GET(PCI_IDE_CAP_SEL_NUM_MASK, val),
 			 CONFIG_PCI_IDE_STREAM_MAX);
 	for (int i = 0; i < nr_streams; i++) {
-		int offset = sel_ide_offset(nr_link_ide, i, nr_ide_mem);
+		int offset = sel_ide_offset(pdev, nr_link_ide, i, nr_ide_mem);
 		int nr_assoc;
 		u32 val;
 
@@ -352,8 +354,7 @@ void pci_ide_stream_setup(struct pci_dev *pdev, struct pci_ide *ide)
 
 	if (!settings)
 		return;
-
-	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
+	pos = sel_ide_offset(pdev, pdev->nr_link_ide, settings->stream_index,
 			     pdev->nr_ide_mem);
 
 	val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, settings->rid_end);
@@ -381,7 +382,7 @@ void pci_ide_stream_teardown(struct pci_dev *pdev, struct pci_ide *ide)
 	if (!settings)
 		return;
 
-	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
+	pos = sel_ide_offset(pdev, pdev->nr_link_ide, settings->stream_index,
 			     pdev->nr_ide_mem);
 
 	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0);
@@ -406,7 +407,7 @@ void pci_ide_stream_enable(struct pci_dev *pdev, struct pci_ide *ide)
 	if (!settings)
 		return;
 
-	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
+	pos = sel_ide_offset(pdev, pdev->nr_link_ide, settings->stream_index,
 			     pdev->nr_ide_mem);
 
 	val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) |
@@ -434,7 +435,7 @@ void pci_ide_stream_disable(struct pci_dev *pdev, struct pci_ide *ide)
 	if (!settings)
 		return;
 
-	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
+	pos = sel_ide_offset(pdev, pdev->nr_link_ide, settings->stream_index,
 			     pdev->nr_ide_mem);
 
 	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0);



> +
> +	val = FIELD_PREP(PCI_IDE_SEL_RID_1_LIMIT_MASK, settings->rid_end);
> +	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_1, val);
> +
> +	val = PREP_PCI_IDE_SEL_RID_2(settings->rid_start, ide_domain(pdev));
> +	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_RID_2, val);
> +}
> +EXPORT_SYMBOL_GPL(pci_ide_stream_setup);
> +
>

....

> +/**
> + * pci_ide_stream_enable() - after setup, enable the stream
> + * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port
> + * @ide: registered and setup IDE settings descriptor
> + *
> + * Activate the stream by writing to the Selective IDE Stream Control Register.
> + */
> +void pci_ide_stream_enable(struct pci_dev *pdev, struct pci_ide *ide)
> +{
> +	struct pci_ide_partner *settings = to_settings(pdev, ide);
> +	int pos;
> +	u32 val;
> +
> +	if (!settings)
> +		return;
> +
> +	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
> +			     pdev->nr_ide_mem);
> +
>
> +	val = FIELD_PREP(PCI_IDE_SEL_CTL_ID_MASK, ide->stream_id) |
> +	      FIELD_PREP(PCI_IDE_SEL_CTL_DEFAULT, 1) |
> +	      FIELD_PREP(PCI_IDE_SEL_CTL_CFG_EN, pdev->ide_cfg) |
> +	      FIELD_PREP(PCI_IDE_SEL_CTL_TEE_LIMITED, pdev->ide_tee_limit) |
>

Does enabling pdev->ide_tee_limit here will prevent a device from operating 
as expected before we get to TDISP RUN state? 

TEE-Limited Stream – When Set, requires that, for Requests, only those that have the T bit Set are
permitted to be associated with this Stream


> +	      FIELD_PREP(PCI_IDE_SEL_CTL_EN, 1);
> +	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val);
> +}
> +EXPORT_SYMBOL_GPL(pci_ide_stream_enable);
> +
> +/**
> + * pci_ide_stream_disable() - disable the given stream
> + * @pdev: PCIe device object for either a Root Port or Endpoint Partner Port
> + * @ide: registered and setup IDE settings descriptor
> + *
> + * Clear the Selective IDE Stream Control Register, but leave all other
> + * registers untouched.
> + */
> +void pci_ide_stream_disable(struct pci_dev *pdev, struct pci_ide *ide)
> +{
> +	struct pci_ide_partner *settings = to_settings(pdev, ide);
> +	int pos;
> +
> +	if (!settings)
> +		return;
> +
> +	pos = sel_ide_offset(pdev->nr_link_ide, settings->stream_index,
> +			     pdev->nr_ide_mem);
>

here

> +
> +	pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, 0);
> +}
> +EXPORT_SYMBOL_GPL(pci_ide_stream_disable);


-aneesh