From: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
To: Dan Williams <dan.j.williams@intel.com>, linux-coco@lists.linux.dev
Cc: Yilun Xu <yilun.xu@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alexey Kardashevskiy <aik@amd.com>,
gregkh@linuxfoundation.org, linux-pci@vger.kernel.org,
aik@amd.com, lukas@wunner.de
Subject: Re: [PATCH v2 04/11] PCI/IDE: Enumerate Selective Stream IDE capabilities
Date: Tue, 11 Mar 2025 11:16:38 +0530 [thread overview]
Message-ID: <yq5aa59sglvl.fsf@kernel.org> (raw)
In-Reply-To: <174107247873.1288555.8934248700370548272.stgit@dwillia2-xfh.jf.intel.com>
Dan Williams <dan.j.williams@intel.com> writes:
.....
> +void pci_ide_init(struct pci_dev *pdev)
> +{
> + u8 nr_link_ide, nr_ide_mem, nr_streams;
> + u16 ide_cap;
> + u32 val;
> +
> + if (!pci_is_pcie(pdev))
> + return;
> +
> + ide_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_IDE);
> + if (!ide_cap)
> + return;
> +
> + pci_read_config_dword(pdev, ide_cap + PCI_IDE_CAP, &val);
> + if ((val & PCI_IDE_CAP_SELECTIVE) == 0)
> + return;
> +
> + /*
> + * Require endpoint IDE capability to be paired with IDE Root
> + * Port IDE capability.
> + */
> + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ENDPOINT) {
> + struct pci_dev *rp = pcie_find_root_port(pdev);
> +
> + if (!rp->ide_cap)
> + return;
> + }
> +
> + if (val & PCI_IDE_CAP_SEL_CFG)
> + pdev->ide_cfg = 1;
> +
> + if (val & PCI_IDE_CAP_TEE_LIMITED)
> + pdev->ide_tee_limit = 1;
> +
> + if (val & PCI_IDE_CAP_LINK)
> + nr_link_ide = 1 + FIELD_GET(PCI_IDE_CAP_LINK_TC_NUM_MASK, val);
> +
> + nr_ide_mem = 0;
> + nr_streams = min(1 + FIELD_GET(PCI_IDE_CAP_SEL_NUM_MASK, val),
> + CONFIG_PCI_IDE_STREAM_MAX);
> + for (int i = 0; i < nr_streams; i++) {
> + int offset = sel_ide_offset(nr_link_ide, i, nr_ide_mem);
> + int nr_assoc;
> + u32 val;
> +
> + pci_read_config_dword(pdev, ide_cap + offset, &val);
> +
> + /*
> + * Let's not entertain devices that do not have a
> + * constant number of address association blocks
> + */
> + nr_assoc = FIELD_GET(PCI_IDE_SEL_CAP_ASSOC_NUM_MASK, val);
> + if (i && (nr_assoc != nr_ide_mem)) {
> + pci_info(pdev, "Unsupported Selective Stream %d capability\n", i);
> + return;
> + }
> +
> + nr_ide_mem = nr_assoc;
>
What is the purpose of the loop? Should it use the minimum value to
ensure we select the lowest supported value for all selective IDE
stream? I assume that, in practice, the number of address association
register blocks will be the same for all selective streams?
nr_ide_mem = min(nr_ide_mem, nr_assoc);
> + }
> +
> + pdev->ide_cap = ide_cap;
> + pdev->nr_link_ide = nr_link_ide;
> + pdev->nr_ide_mem = nr_ide_mem;
> +}
-aneesh
next prev parent reply other threads:[~2025-03-11 5:46 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-04 7:14 [PATCH v2 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-03-04 7:14 ` [PATCH v2 01/11] configfs-tsm: Namespace TSM report symbols Dan Williams
2025-03-05 10:11 ` Steven Price
2025-03-10 16:26 ` Sathyanarayanan Kuppuswamy
2025-03-10 22:19 ` Huang, Kai
2025-03-04 7:14 ` [PATCH v2 02/11] coco/guest: Move shared guest CC infrastructure to drivers/virt/coco/guest/ Dan Williams
2025-03-10 16:26 ` Sathyanarayanan Kuppuswamy
2025-03-10 22:57 ` Huang, Kai
2025-04-18 23:28 ` Dan Williams
2025-03-04 7:14 ` [PATCH v2 03/11] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-03-04 7:14 ` [PATCH v2 04/11] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-03-11 5:46 ` Aneesh Kumar K.V [this message]
2025-03-11 6:33 ` Alexey Kardashevskiy
2025-04-25 21:03 ` Dan Williams
2025-03-04 7:14 ` [PATCH v2 05/11] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2025-04-16 5:33 ` Aneesh Kumar K.V
2025-04-25 22:51 ` Dan Williams
2025-03-04 7:14 ` [PATCH v2 06/11] samples/devsec: Introduce a PCI device-security bus + endpoint sample Dan Williams
2025-03-11 14:17 ` [PATCH v2 06/11] samples/devsec: Introduce a PCI device-security Suzuki K Poulose
2025-03-11 14:45 ` [RESEND RFC PATCH 1/3] pci: ide: Fix build failure Suzuki K Poulose
2025-03-11 14:46 ` [RESEND RFC PATCH 2/3] pci: generic-domains: Add helpers to alloc/free dynamic bus numbers Suzuki K Poulose
2025-03-11 14:46 ` [RESEND RFC PATCH 3/3] samples: devsec: Add support for PCI_DOMAINS_GENERIC Suzuki K Poulose
2025-04-20 18:29 ` Dan Williams
2025-04-22 15:45 ` Suzuki K Poulose
2025-04-24 12:39 ` [tip: irq/urgent] irqchip/gic-v2m: Prevent use after free of gicv2m_get_fwnode() tip-bot2 for Suzuki K Poulose
2025-04-24 13:01 ` tip-bot2 for Suzuki K Poulose
2025-05-13 10:18 ` [PATCH v2 06/11] samples/devsec: Introduce a PCI device-security bus + endpoint sample Zhi Wang
2025-03-04 7:14 ` [PATCH v2 07/11] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-03-04 7:15 ` [PATCH v2 08/11] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-03-04 20:44 ` kernel test robot
2025-03-05 12:32 ` kernel test robot
2025-03-11 10:51 ` Suzuki K Poulose
2025-04-19 17:50 ` Dan Williams
2025-03-18 3:18 ` Alexey Kardashevskiy
2025-04-25 21:42 ` Dan Williams
2025-04-21 6:13 ` Aneesh Kumar K.V
2025-04-25 16:29 ` Xu Yilun
2025-04-25 23:31 ` Dan Williams
2025-04-27 9:33 ` Aneesh Kumar K.V
2025-03-04 7:15 ` [PATCH v2 09/11] PCI/IDE: Report available IDE streams Dan Williams
2025-03-04 13:49 ` kernel test robot
2025-03-04 16:54 ` Dionna Amalie Glaze
2025-04-25 20:42 ` Dan Williams
2025-03-04 7:15 ` [PATCH v2 10/11] PCI/TSM: Report active " Dan Williams
2025-03-04 7:15 ` [PATCH v2 11/11] samples/devsec: Add sample IDE establishment Dan Williams
2025-05-07 10:47 ` [PATCH v2 00/11] PCI/TSM: Core infrastructure for PCI device security (TDISP) Zhi Wang
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