From: Keith Packard <keithp@keithp.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Reset GMBUS controller after NAK
Date: Wed, 30 Mar 2011 10:22:48 -0700 [thread overview]
Message-ID: <yunpqp87cbb.fsf@aiko.keithp.com> (raw)
In-Reply-To: <1bdc18$k257pk@fmsmga002.fm.intel.com>
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On Wed, 30 Mar 2011 17:59:51 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> I'm not even sure we need the first posting read. Maybe it should be a
> wait_for(I915_READ(GMBUS1 + reg_offset) & GMBUS_SW_CLR_INT, 100)
> to be clearer that we are simply giving the hardware the chance to assert
> the bit and reset before re-enabling.
Doesn't look like the hardware actually delays in setting this bit, so
your original sequence should be correct. Of course, a comment
indicating that you're toggling the SW_CLR_INT bit to reset the bus
might be nice.
> No, GMBUS0 is not read until the very first phase of the data cycle. And
> the very first thing we do in the next xfer is a write to GMBUS0 of the
> port settings. I just thought that explicitly marking the GMBUS controller
> as disabled when not in use by us would lead to less confusion in
> future.
Sounds reasonable. I'd love to have seen a comment in the code and in
the patch...
--
keith.packard@intel.com
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next prev parent reply other threads:[~2011-03-30 17:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-30 16:07 [PATCH] drm/i915: Reset GMBUS controller after NAK Chris Wilson
2011-03-30 16:48 ` Keith Packard
2011-03-30 16:59 ` Chris Wilson
2011-03-30 17:22 ` Keith Packard [this message]
2011-03-30 17:42 ` Chris Wilson
2011-03-30 17:56 ` Keith Packard
2011-03-30 20:05 ` Jesse Barnes
2011-03-31 15:16 ` Steven Newbury
2011-03-31 15:20 ` Chris Wilson
2011-03-31 15:33 ` Steven Newbury
2011-04-02 21:50 ` Steven Newbury
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