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From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Caleb Crome <caleb@crome.org>
Cc: Fabio Estevam <fabio.estevam@freescale.com>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
	Markus Pargmann <mpa@pengutronix.de>,
	"arnaud.mouiche@invoxia.com" <arnaud.mouiche@invoxia.com>,
	Roberto Fichera <kernel@tekno-soft.it>,
	"shawn.guo@linaro.org" <shawn.guo@linaro.org>
Subject: Re: fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode.
Date: Wed, 28 Oct 2015 21:53:51 -0700	[thread overview]
Message-ID: <20151029045350.GA3374@Asurada-CZ80> (raw)
In-Reply-To: <CAG5mAdz=TKSmXBOqKfSj0FYfk3c6syBa87OazyGRRF0NU4snXA@mail.gmail.com>

On Wed, Oct 28, 2015 at 03:06:40PM -0700, Caleb Crome wrote:

> > 2) Set the watermarks for both TX and RX to 8 while using burst sizes
> >    of 6. It'd be nicer to provisionally set these numbers using hard
> >    code than your current change depending on fifo_depth as it might
> >    be an odd value.

> Ah, this is fascinating you say this.  fifo_depth is definitely odd,
> it's 15 as set in imx6qdl.dtsi:

> fsl,fifo-depth = <15>;
> But the DMA maxburst is made even later in the code...

And odd number for burst size may course a similar problem like
channel swapping in two-channel cases because the number of data
FIFO is 2 -- an even number. But it seems not to be related to
your problem here.

> Setting the watermark to 8 and maxburst to 8 dramatically reduces the
> channel slip rate, in fact, i didn't see a slip for more than 30
> minutes of playing.  That's a new record for sure.  But, eventually,
> there was an underrun, and the channels slipped.
> 
> Setting watermark to 8 and maxburst to 6 still had some slips,
> seemingly more than 8 & 8.
> 
> I feel like a monkey randomly typing at my keyboard though.  I don't
> know why maxburst=8 worked better.  I get the
> feeling that I was just lucky.

That's actually another possible root cause -- performance issue.
burst=8 will have less bus transaction number than the case when
burst=6. As you have quite a lot channels comparing to normal 2
channels, you need to feed the FIFO more frequently. If SDMA does
not feed the data before the input FIFO gets underrun, a channel
swapping might happen: in your case, channel slip.

> There does seem to be a correlation between user space reported
> underruns and this channel slip, although they definitely are not 1:1

Reported by user space? Are you saying that's an ALSA underrun in
the user space, not a hardware underrun reported by the IRQ in the
driver? They are quite different. ALSA underrun comes from the DMA
buffer gets underrun while the other one results from FIFO feeding
efficiency. For ALSA underrun, enlarging the playback period size
and period number will ease the problem:

period number = buffer size / period size;

An ALSA underrun may not be companied by a hardware underrun but
they may co-exist.

> ratio:  underruns happen without slips and slips happen without
> underruns.  The latter is very disturbing because user space has no
> idea something is wrong.

> @@ -1260,8 +1260,8 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
>          * We have burstsize be "fifo_depth - 2" to match the SSI
>          * watermark setting in fsl_ssi_startup().
>          */
> -       ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
> -       ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
> +       ssi_private->dma_params_tx.maxburst = 8;
> +       ssi_private->dma_params_rx.maxburst = 8;

I am actually thinking about setting a watermark to a larger number.
I forgot how the SDMA script handles this number. But if this burst
size means the overall data count per transaction, it might indicate
that each FIFO only gets half of the burst size due to dual FIFOs.

Therefore, if setting watermark to 8, each FIFO has 7 (15 - 8) space
left, the largest safe burst size could be 14 (7 * 2) actually.

Yes. That's kind of fine tunning the parameters. And for your case,
you may try a larger number as the SSI is simultaneously consuming
a large amount of data even though it sounds risky. But it's worth
trying since you are using SSI which only has tight FIFOs not like
ESAI has 128 depth.

Nicolin

  reply	other threads:[~2015-10-29  4:53 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-19 15:55 fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode Caleb Crome
2015-10-20  7:36 ` arnaud.mouiche
2015-10-20 17:43   ` Caleb Crome
2015-10-21  7:32     ` arnaud.mouiche
2015-10-21 19:37       ` Caleb Crome
2015-10-26 17:31         ` Caleb Crome
2015-10-27  7:13           ` Markus Pargmann
2015-10-27  9:41             ` Fabio Estevam
2015-10-27 16:02               ` Caleb Crome
2015-10-27 16:10                 ` Fabio Estevam
2015-10-27 16:42                   ` Caleb Crome
2015-10-27 16:45                     ` Fabio Estevam
2015-10-27 18:57                       ` Fabio Estevam
2015-10-28  8:11                         ` Roberto Fichera
2015-10-28 13:59                           ` Caleb Crome
2015-10-28 14:05                             ` Roberto Fichera
2015-10-28 14:24                               ` Caleb Crome
2015-10-28 14:48                                 ` Roberto Fichera
2015-10-28 22:09                             ` Caleb Crome
2015-10-29  8:04                               ` Roberto Fichera
2015-10-29 23:04                           ` Nicolin Chen
2015-10-30 11:42                             ` Roberto Fichera
2015-10-30 17:21                               ` Nicolin Chen
2015-10-28 13:53                       ` Caleb Crome
2015-10-27 20:11             ` Nicolin Chen
2015-10-28  8:23               ` Roberto Fichera
2015-10-29 23:05                 ` Nicolin Chen
2015-10-28 22:06               ` Caleb Crome
2015-10-29  4:53                 ` Nicolin Chen [this message]
2015-10-29 13:44                   ` Caleb Crome
2015-10-29 14:55                     ` Caleb Crome
2015-10-29 15:37                       ` Roberto Fichera
2015-10-29 15:54                         ` Caleb Crome
2015-10-29 16:02                           ` Roberto Fichera
2015-10-29 16:19                             ` Caleb Crome
2015-10-29 16:34                             ` Roberto Fichera
2015-10-29 16:39                               ` Caleb Crome
2015-10-29 16:59                                 ` Roberto Fichera
2015-10-29 18:36                           ` Nicolin Chen
2015-10-29 19:08                             ` Caleb Crome
2015-10-29 23:22                         ` Nicolin Chen
2015-10-29 18:11                       ` Nicolin Chen
2015-10-29 17:19                     ` Nicolin Chen
2015-10-29 19:06                       ` Caleb Crome
2015-10-29 19:28                         ` Nicolin Chen
2015-10-29 22:23                           ` Caleb Crome
2015-10-29 22:47                             ` Nicolin Chen
2015-10-29 23:33                               ` Caleb Crome
2015-10-30  1:29                                 ` Nicolin Chen
2015-10-30  8:29                                   ` arnaud.mouiche
2015-10-30  8:45                                     ` arnaud.mouiche
2015-10-30 16:07                                       ` Nicolin Chen
2015-10-30 15:49                                     ` Nicolin Chen
2015-10-30 18:10                                       ` Caleb Crome
2015-10-30 22:04                                   ` Caleb Crome
2015-10-30 22:35                                     ` Caleb Crome
2015-10-31  1:32                                       ` Nicolin Chen
2015-10-31 16:12                                         ` Caleb Crome
2015-10-31  1:48                                     ` Nicolin Chen
2015-10-31 16:22                                       ` Caleb Crome
2015-11-02 17:22                                         ` Nicolin Chen

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