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From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Caleb Crome <caleb@crome.org>
Cc: Fabio Estevam <fabio.estevam@freescale.com>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
	Markus Pargmann <mpa@pengutronix.de>,
	"arnaud.mouiche@invoxia.com" <arnaud.mouiche@invoxia.com>,
	Roberto Fichera <kernel@tekno-soft.it>,
	"shawn.guo@linaro.org" <shawn.guo@linaro.org>
Subject: Re: fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode.
Date: Thu, 29 Oct 2015 15:47:14 -0700	[thread overview]
Message-ID: <20151029224713.GA44369@Asurada-CZ80> (raw)
In-Reply-To: <CAG5mAdzJ2_MizAq2ACXwnA=wfO=xujGbUdB2OvcDi=7fHQfyBQ@mail.gmail.com>

On Thu, Oct 29, 2015 at 03:23:41PM -0700, Caleb Crome wrote:

> > I saw your problem in the other reply. And I suggested you to let
> > DMA work first before SSI gets enabled. As SDMA in that case would
> > transfer one burst length (16 if you applied my patch I sent you)
> > and pause before SSI gets enabled. Then SSI would have enough data
> > to send out without any startup issue.
> 
> Ah ha, you are exactly right.  The root cause is that TE and SSIE are
> enabled at the same regmap write, with no opportunity for delay
> between the SSIE and TE.
> DMA can only get going if SSIE is enabled, and the only place SSIE
> gets enabled is exactly the same line that TE gets enabled.

A little difference between your point and mine is that you think
DMA request only starts when SSIE and TDMAE both get set while I
only think about TDMAE. It's hard to say which one is correct as
it depends on the design of IP wrapper but you can fairly test it
with your change below: Mask both TE with SSIE and set them after
the delay. If it doesn't work, yours is the correct one.

> I've looked over your emails and I don't see the patch that shows a

You may need to open an offline email that I sent you with patches
in its attachment. I can see it via Gmail anyway.

> pause between SSIE enable and TE enable.  (I do see the dual-fifo
> example -- thank you!  I'll give that a try -- it may further reduce
> stress on the system).

I'm sure dual FIFO will get better performance. But the example I
gave you doesn't set RX parameters so well. You may need to fine
tune it later.

> Is adding the udelay the best way to put a delay between SSIE and TE enable?
> Are there any other mechanisms for that?

Having a delay is much safer for you but surely it's not a common
practice that's best all other platforms such as two-channel cases
and those who needs performance.

I encourage you to try to follow one of patches I gave you that
sets TDMAE/RDMAE at the beginning of the trigger(). Surely you may
change it to TDMAE | SSIE after you find out that SSIE is indeed
required. If you are still having trouble, adding a delay would
be nice for you but it may be hard for me to ack it if you want
to merge it in the driver.

Nicolin

  reply	other threads:[~2015-10-29 22:47 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-19 15:55 fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode Caleb Crome
2015-10-20  7:36 ` arnaud.mouiche
2015-10-20 17:43   ` Caleb Crome
2015-10-21  7:32     ` arnaud.mouiche
2015-10-21 19:37       ` Caleb Crome
2015-10-26 17:31         ` Caleb Crome
2015-10-27  7:13           ` Markus Pargmann
2015-10-27  9:41             ` Fabio Estevam
2015-10-27 16:02               ` Caleb Crome
2015-10-27 16:10                 ` Fabio Estevam
2015-10-27 16:42                   ` Caleb Crome
2015-10-27 16:45                     ` Fabio Estevam
2015-10-27 18:57                       ` Fabio Estevam
2015-10-28  8:11                         ` Roberto Fichera
2015-10-28 13:59                           ` Caleb Crome
2015-10-28 14:05                             ` Roberto Fichera
2015-10-28 14:24                               ` Caleb Crome
2015-10-28 14:48                                 ` Roberto Fichera
2015-10-28 22:09                             ` Caleb Crome
2015-10-29  8:04                               ` Roberto Fichera
2015-10-29 23:04                           ` Nicolin Chen
2015-10-30 11:42                             ` Roberto Fichera
2015-10-30 17:21                               ` Nicolin Chen
2015-10-28 13:53                       ` Caleb Crome
2015-10-27 20:11             ` Nicolin Chen
2015-10-28  8:23               ` Roberto Fichera
2015-10-29 23:05                 ` Nicolin Chen
2015-10-28 22:06               ` Caleb Crome
2015-10-29  4:53                 ` Nicolin Chen
2015-10-29 13:44                   ` Caleb Crome
2015-10-29 14:55                     ` Caleb Crome
2015-10-29 15:37                       ` Roberto Fichera
2015-10-29 15:54                         ` Caleb Crome
2015-10-29 16:02                           ` Roberto Fichera
2015-10-29 16:19                             ` Caleb Crome
2015-10-29 16:34                             ` Roberto Fichera
2015-10-29 16:39                               ` Caleb Crome
2015-10-29 16:59                                 ` Roberto Fichera
2015-10-29 18:36                           ` Nicolin Chen
2015-10-29 19:08                             ` Caleb Crome
2015-10-29 23:22                         ` Nicolin Chen
2015-10-29 18:11                       ` Nicolin Chen
2015-10-29 17:19                     ` Nicolin Chen
2015-10-29 19:06                       ` Caleb Crome
2015-10-29 19:28                         ` Nicolin Chen
2015-10-29 22:23                           ` Caleb Crome
2015-10-29 22:47                             ` Nicolin Chen [this message]
2015-10-29 23:33                               ` Caleb Crome
2015-10-30  1:29                                 ` Nicolin Chen
2015-10-30  8:29                                   ` arnaud.mouiche
2015-10-30  8:45                                     ` arnaud.mouiche
2015-10-30 16:07                                       ` Nicolin Chen
2015-10-30 15:49                                     ` Nicolin Chen
2015-10-30 18:10                                       ` Caleb Crome
2015-10-30 22:04                                   ` Caleb Crome
2015-10-30 22:35                                     ` Caleb Crome
2015-10-31  1:32                                       ` Nicolin Chen
2015-10-31 16:12                                         ` Caleb Crome
2015-10-31  1:48                                     ` Nicolin Chen
2015-10-31 16:22                                       ` Caleb Crome
2015-11-02 17:22                                         ` Nicolin Chen

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