From: Nicolin Chen <nicoleotsuka@gmail.com>
To: "arnaud.mouiche@invoxia.com" <arnaud.mouiche@invoxia.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
Caleb Crome <caleb@crome.org>,
Markus Pargmann <mpa@pengutronix.de>,
Roberto Fichera <kernel@tekno-soft.it>,
"shawn.guo@linaro.org" <shawn.guo@linaro.org>
Subject: Re: fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode.
Date: Fri, 30 Oct 2015 08:49:47 -0700 [thread overview]
Message-ID: <20151030154946.GA3505@Asurada-CZ80> (raw)
In-Reply-To: <56332A4E.3010704@invoxia.com>
On Fri, Oct 30, 2015 at 09:29:02AM +0100, arnaud.mouiche@invoxia.com wrote:
> At imx50 age, I remember one workaround was to fill the fifo
> manually, writing directly a number of samples (equal to the number
> of slots for one frame to keep the synchronization), and then,
> enable the TMDAE.
> This just allow to not have to wait an undefined period of time for
> the DMA to be ready.
> But, on the other hand, if the time to wait the DMA is short enough,
> it should not be an issue.
Nice input. This reminds me of the zero-filling step inside the
ESAI startup procedure:
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
/* Write initial words reqiured by ESAI as normal procedure */
for (i = 0; tx && i < channels; i++)
regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
break;
It's exactly the same thing to prevent underrun. This might be
a reasonable alternative option due to no polling overhead and
timeout handling.
Thanks
Nicolin
next prev parent reply other threads:[~2015-10-30 15:49 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-19 15:55 fsl_ssi.c: Getting channel slips with fsl_ssi.c in TDM (network) mode Caleb Crome
2015-10-20 7:36 ` arnaud.mouiche
2015-10-20 17:43 ` Caleb Crome
2015-10-21 7:32 ` arnaud.mouiche
2015-10-21 19:37 ` Caleb Crome
2015-10-26 17:31 ` Caleb Crome
2015-10-27 7:13 ` Markus Pargmann
2015-10-27 9:41 ` Fabio Estevam
2015-10-27 16:02 ` Caleb Crome
2015-10-27 16:10 ` Fabio Estevam
2015-10-27 16:42 ` Caleb Crome
2015-10-27 16:45 ` Fabio Estevam
2015-10-27 18:57 ` Fabio Estevam
2015-10-28 8:11 ` Roberto Fichera
2015-10-28 13:59 ` Caleb Crome
2015-10-28 14:05 ` Roberto Fichera
2015-10-28 14:24 ` Caleb Crome
2015-10-28 14:48 ` Roberto Fichera
2015-10-28 22:09 ` Caleb Crome
2015-10-29 8:04 ` Roberto Fichera
2015-10-29 23:04 ` Nicolin Chen
2015-10-30 11:42 ` Roberto Fichera
2015-10-30 17:21 ` Nicolin Chen
2015-10-28 13:53 ` Caleb Crome
2015-10-27 20:11 ` Nicolin Chen
2015-10-28 8:23 ` Roberto Fichera
2015-10-29 23:05 ` Nicolin Chen
2015-10-28 22:06 ` Caleb Crome
2015-10-29 4:53 ` Nicolin Chen
2015-10-29 13:44 ` Caleb Crome
2015-10-29 14:55 ` Caleb Crome
2015-10-29 15:37 ` Roberto Fichera
2015-10-29 15:54 ` Caleb Crome
2015-10-29 16:02 ` Roberto Fichera
2015-10-29 16:19 ` Caleb Crome
2015-10-29 16:34 ` Roberto Fichera
2015-10-29 16:39 ` Caleb Crome
2015-10-29 16:59 ` Roberto Fichera
2015-10-29 18:36 ` Nicolin Chen
2015-10-29 19:08 ` Caleb Crome
2015-10-29 23:22 ` Nicolin Chen
2015-10-29 18:11 ` Nicolin Chen
2015-10-29 17:19 ` Nicolin Chen
2015-10-29 19:06 ` Caleb Crome
2015-10-29 19:28 ` Nicolin Chen
2015-10-29 22:23 ` Caleb Crome
2015-10-29 22:47 ` Nicolin Chen
2015-10-29 23:33 ` Caleb Crome
2015-10-30 1:29 ` Nicolin Chen
2015-10-30 8:29 ` arnaud.mouiche
2015-10-30 8:45 ` arnaud.mouiche
2015-10-30 16:07 ` Nicolin Chen
2015-10-30 15:49 ` Nicolin Chen [this message]
2015-10-30 18:10 ` Caleb Crome
2015-10-30 22:04 ` Caleb Crome
2015-10-30 22:35 ` Caleb Crome
2015-10-31 1:32 ` Nicolin Chen
2015-10-31 16:12 ` Caleb Crome
2015-10-31 1:48 ` Nicolin Chen
2015-10-31 16:22 ` Caleb Crome
2015-11-02 17:22 ` Nicolin Chen
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