* [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines
@ 2023-04-22 16:10 Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 1/7] ALSA: emu10k1: comment updates Oswald Buddenhagen
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
Mostly adding, removing, and otherwise massaging numerous #defines and
code using them, and surrounding comments.
Oswald Buddenhagen (7):
ALSA: emu10k1: comment updates
ALSA: emu10k1: fix lineup of EMU_HANA_* defines
ALSA: emu10k1: eliminate some unused defines
ALSA: emu10k1: remove some bogus defines
ALSA: emu10k1: pull in some register definitions from kX-project
ALSA: emu10k1: fixup DSP defines
ALSA: emu10k1: use more existing defines instead of open-coded numbers
include/sound/emu10k1.h | 685 +++++++++++++--------------
include/uapi/sound/emu10k1.h | 147 ++++--
sound/pci/emu10k1/emu10k1.c | 11 -
sound/pci/emu10k1/emu10k1_callback.c | 15 +-
sound/pci/emu10k1/emu10k1_main.c | 125 ++---
sound/pci/emu10k1/emufx.c | 18 +-
sound/pci/emu10k1/emumixer.c | 13 +-
sound/pci/emu10k1/emupcm.c | 39 +-
sound/pci/emu10k1/io.c | 26 +-
sound/pci/emu10k1/p16v.c | 29 +-
sound/pci/emu10k1/p16v.h | 2 +-
sound/pci/emu10k1/p17v.h | 4 +-
12 files changed, 554 insertions(+), 560 deletions(-)
--
2.40.0.152.g15d061e6df
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/7] ALSA: emu10k1: comment updates
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 2/7] ALSA: emu10k1: fix lineup of EMU_HANA_* defines Oswald Buddenhagen
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
Move comments to better locations, de-duplicate, fix/remove incorrect/
outdated ones, add new ones, and unify spacing somewhat.
While at it, also add testing credits for Jonathan Dowland (SB Live!
Platinum) and myself (E-MU 0404b).
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 502 +++++++++++++++----------------
include/uapi/sound/emu10k1.h | 3 +
sound/pci/emu10k1/emu10k1.c | 11 -
sound/pci/emu10k1/emu10k1_main.c | 77 +++--
sound/pci/emu10k1/emufx.c | 12 +-
sound/pci/emu10k1/emumixer.c | 5 +-
sound/pci/emu10k1/emupcm.c | 26 +-
sound/pci/emu10k1/io.c | 8 -
sound/pci/emu10k1/p16v.h | 2 +-
sound/pci/emu10k1/p17v.h | 4 +-
10 files changed, 311 insertions(+), 339 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 790dedd42340..7786d5807679 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -97,9 +97,9 @@
#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
/* highest set channel in CLIPL, CLIPH, HLIPL, */
- /* or HLIPH. When IP is written with CL set, */
+ /* or HLIPH. When IPR is written with CL set, */
/* the bit in H/CLIPL or H/CLIPH corresponding */
- /* to the CIN value written will be cleared. */
+ /* to the CN value written will be cleared. */
#define INTE 0x0c /* Interrupt enable register */
#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
@@ -180,6 +180,7 @@
#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
/* Specific to Alice2, CA0102 */
+
#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
@@ -200,9 +201,8 @@
/* I2S format input */
/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
-
-
/* Older chips */
+
#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
@@ -238,7 +238,7 @@
/* Should be set to 1 when the EMU10K1 is */
/* completely initialized. */
-//For Audigy, MPU port move to 0x70-0x74 ptr register
+// On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
#define MUDATA 0x18 /* MPU401 data register (8 bits) */
@@ -277,12 +277,6 @@
#define A_IOCFG_REAR_JACK 0x8000
#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
-/* outputs:
- * for audigy2 platinum: 0xa00
- * for a2 platinum ex: 0x1c00
- * for a1 platinum: 0x0
- */
-
#define TIMER 0x1a /* Timer terminal count register */
/* NOTE: After the rate is changed, a maximum */
/* of 1024 sample periods should be allowed */
@@ -323,7 +317,7 @@
/* 0x00000000 2-channel output. */
/* 0x00000200 8-channel output. */
/* 0x00000004 pauses stream/irq fail. */
- /* Rest of bits no nothing to sound output */
+ /* Rest of bits do nothing to sound output */
/* bit 0: Enable P16V audio.
* bit 1: Lock P16V record memory cache.
* bit 2: Lock P16V playback memory cache.
@@ -337,6 +331,7 @@
*/
#define IPR3 0x38 /* Cdif interrupt pending register */
#define INTE3 0x3c /* Cdif interrupt enable register. */
+
/************************************************************************************************/
/* PCI function 1 registers, address = <val> + PCIBASE1 */
/************************************************************************************************/
@@ -355,11 +350,38 @@
#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
-
/********************************************************************************************************/
/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
/********************************************************************************************************/
+// No official documentation was released for EMU10K1, but some info
+// about playback can be extrapolated from the EMU8K documents:
+// "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
+// "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
+
+// The short version:
+// - The engine has 64 playback channels, also called voices. The channels
+// operate independently, except when paired for stereo (see below).
+// - PCM samples are fetched into the cache; see description of CD0 below.
+// - Samples are consumed at the rate CPF_CURRENTPITCH.
+// - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
+// - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
+// according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero
+// CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim.
+// - The value is multiplied by CVCF_CURRENTVOL.
+// - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
+// delay stages Z1 and Z2.
+// - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
+// of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*,
+// multiplied by a per-send amount (*_FXSENDAMOUNT_*).
+// The scaling of the send amounts is exponential-ish.
+// - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
+// - The pitch, volume, and filter cutoff can be modulated by two envelope
+// engines and two low frequency oscillators.
+// - To avoid abrupt changes to the parameters (which may cause audible
+// distortion), the modulation engine sets the target registers, towards
+// which the current registers "swerve" gradually.
+
#define CPF 0x00 /* Current pitch and fraction register */
#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
#define CPF_CURRENTPITCH 0x10100000
@@ -399,7 +421,7 @@
#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
#define PSST_LOOPSTARTADDR 0x18000006
-#define DSL 0x07 /* Send D amount and loop start address register */
+#define DSL 0x07 /* Send D amount and loop end address register */
#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
#define DSL_FXSENDAMOUNT_D 0x08180007
@@ -424,46 +446,48 @@
#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
+ /* 8-bit samples are unsigned, 16-bit ones signed */
#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
#define CCCA_CURRADDR 0x18000008
#define CCR 0x09 /* Cache control register */
#define CCR_CACHEINVALIDSIZE 0x07190009
-#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
+#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples before the read address */
#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
+ /* Auto-set from CPF_STEREO_MASK */
#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
+ /* Auto-set from CCCA_8BITSELECT */
#define CCR_READADDRESS 0x06100009
-#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
+#define CCR_READADDRESS_MASK 0x003f0000 /* Next cached sample to play */
#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
/* NOTE: This is valid only if CACHELOOPFLAG is set */
#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
-#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
+#define CCR_CACHELOOPADDRHI 0x000000ff /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
/* NOTE: This register is normally not used */
-#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
+#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address low word */
#define FXRT 0x0b /* Effects send routing register */
/* NOTE: It is illegal to assign the same routing to */
/* two effects sends. */
#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
#define MAPA 0x0c /* Cache map A */
-
#define MAPB 0x0d /* Cache map B */
#define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */
#define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
#define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
#define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
-/* 0x0e, 0x0f: Not used */
+/* 0x0e, 0x0f: Internal state, at least on Audigy */
#define ENVVOL 0x10 /* Volume envelope register */
#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
@@ -476,9 +500,9 @@
/* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
-#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
+#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
-#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
+#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */
/* this channel and from writing to pitch, filter and */
/* volume targets. */
#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
@@ -499,7 +523,7 @@
/* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
-#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
+#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
/* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
@@ -521,27 +545,26 @@
#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
#define IFATN_ATTENUATION 0x08000019
-
#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
/* Signed 2's complement, +/- one octave peak extremes */
#define PEFE_PITCHAMOUNT 0x0808001a
#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
/* Signed 2's complement, +/- six octaves peak extremes */
#define PEFE_FILTERAMOUNT 0x0800001a
+
#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
/* Signed 2's complement, +/- one octave extremes */
#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
/* Signed 2's complement, +/- three octave extremes */
-
#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
/* Signed 2's complement, with +/- 12dB extremes */
-
#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
/* ??Hz steps, maximum of ?? Hz. */
+
#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
/* Signed 2's complement, +/- one octave extremes */
@@ -645,17 +668,15 @@
#define FXBA 0x47 /* FX Buffer Address */
#define FXBA_MASK 0xfffff000 /* 20 bit base address */
-#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
+#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
#define MICBS 0x49 /* Microphone buffer size register */
#define ADCBS 0x4a /* ADC buffer size register */
#define FXBS 0x4b /* FX buffer size register */
-/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
-
-/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
+/* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
#define ADCBS_BUFSIZE_NONE 0x00000000
#define ADCBS_BUFSIZE_384 0x00000001
#define ADCBS_BUFSIZE_448 0x00000002
@@ -689,38 +710,30 @@
#define ADCBS_BUFSIZE_57344 0x0000001e
#define ADCBS_BUFSIZE_65536 0x0000001f
-/* Current Send B, A Amounts */
-#define A_CSBA 0x4c
+#define A_CSBA 0x4c /* FX send B & A current amounts */
+#define A_CSDC 0x4d /* FX send D & C current amounts */
+#define A_CSFE 0x4e /* FX send F & E current amounts */
+#define A_CSHG 0x4f /* FX send H & G current amounts */
-/* Current Send D, C Amounts */
-#define A_CSDC 0x4d
+// NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
+#define CDCS 0x50 /* CD-ROM digital channel status register */
-/* Current Send F, E Amounts */
-#define A_CSFE 0x4e
+#define GPSCS 0x51 /* General Purpose SPDIF channel status register */
-/* Current Send H, G Amounts */
-#define A_CSHG 0x4f
+#define DBG 0x52
+#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
-#define CDCS 0x50 /* CD-ROM digital channel status register */
-
-#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
-
-#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
-
-/* S/PDIF Input C Channel Status */
-#define A_SPSC 0x52
-
-#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
+#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
#define A_DBG 0x53
#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
#define A_DBG_ZC 0x40000000 /* zero tram counter */
#define A_DBG_STEP_ADDR 0x000003ff
#define A_DBG_SATURATION_OCCURED 0x20000000
#define A_DBG_SATURATION_ADDR 0x0ffc0000
-// NOTE: 0x54,55,56: 64-bit
+// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
@@ -753,33 +766,29 @@
/* 0x57: Not used */
-/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
+/* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
#define CLIEL 0x58 /* Channel loop interrupt enable low register */
-
#define CLIEH 0x59 /* Channel loop interrupt enable high register */
#define CLIPL 0x5a /* Channel loop interrupt pending low register */
-
#define CLIPH 0x5b /* Channel loop interrupt pending high register */
#define SOLEL 0x5c /* Stop on loop enable low register */
-
#define SOLEH 0x5d /* Stop on loop enable high register */
#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
-#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
-#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
-#define AC97SLOT_CNTR 0x10 /* Center enable */
-#define AC97SLOT_LFE 0x20 /* LFE enable */
+#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
+#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
+#define AC97SLOT_CNTR 0x10 /* Center enable */
+#define AC97SLOT_LFE 0x20 /* LFE enable */
-/* PCB Revision */
-#define A_PCB 0x5f
+#define A_PCB 0x5f /* PCB Revision */
// NOTE: 0x60,61,62: 64-bit
#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
@@ -819,27 +828,21 @@
#define FXIDX_MASK 0x0000ffff /* 16-bit value */
#define FXIDX_IDX 0x10000065
-/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
+/* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
#define HLIEL 0x66 /* Channel half loop interrupt enable low register */
-
#define HLIEH 0x67 /* Channel half loop interrupt enable high register */
#define HLIPL 0x68 /* Channel half loop interrupt pending low register */
-
#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
-/* S/PDIF Host Record Index (bypasses SRC) */
-#define A_SPRI 0x6a
-/* S/PDIF Host Record Address */
-#define A_SPRA 0x6b
-/* S/PDIF Host Record Control */
-#define A_SPRC 0x6c
-/* Delayed Interrupt Counter & Enable */
-#define A_DICE 0x6d
-/* Tank Table Base */
-#define A_TTB 0x6e
-/* Tank Delay Offset */
-#define A_TDOF 0x6f
+#define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
+#define A_SPRA 0x6b /* S/PDIF Host Record Address */
+#define A_SPRC 0x6c /* S/PDIF Host Record Control */
+
+#define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */
+
+#define A_TTB 0x6e /* Tank Table Base */
+#define A_TDOF 0x6f /* Tank Delay Offset */
/* This is the MPU port on the card (via the game port) */
#define A_MUDATA1 0x70
@@ -852,7 +855,7 @@
#define A_MUSTAT2 A_MUCMD2
/* The next two are the Audigy equivalent of FXWC */
-/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
+/* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */
/* Each bit selects a channel for recording */
#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
@@ -880,20 +883,13 @@
#define A_PCM_96000 0x00004000
#define A_PCM_44100 0x00008000
-/* I2S0 Sample Rate Tracker Status */
-#define A_SRT3 0x77
-
-/* I2S1 Sample Rate Tracker Status */
-#define A_SRT4 0x78
-
-/* I2S2 Sample Rate Tracker Status */
-#define A_SRT5 0x79
+#define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
+#define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
+#define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
-/* Tank Table DMA Address */
-#define A_TTDA 0x7a
-/* Tank Table DMA Data */
-#define A_TTDD 0x7b
+#define A_TTDA 0x7a /* Tank Table DMA Address */
+#define A_TTDD 0x7b /* Tank Table DMA Data */
#define A_FXRT2 0x7c
#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
@@ -906,6 +902,7 @@
#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
#define A_FXSENDAMOUNT_H_MASK 0x000000FF
+
/* 0x7c, 0x7e "high bit is used for filtering" */
/* The send amounts for this one are the same as used with the emu10k1 */
@@ -956,15 +953,47 @@
#define A_HIWORD_RESULT_MASK 0x007ff000
#define A_HIWORD_OPA_MASK 0x000007ff
+
/************************************************************************************************/
-/* EMU1010m HANA FPGA registers */
+/* E-MU Digital Audio System overview */
/************************************************************************************************/
+
+// - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
+// the PCIe variants simply put the Audigy chip behind a PCI bridge.
+// - All physical PCM I/O is routed through an additional FPGA; the regular
+// EXTIN/EXTOUT ports are unconnected.
+// - The FPGA has a signal routing matrix, to connect each destination (output
+// socket or capture channel) to a source (input socket or playback channel).
+// - The FPGA is controlled via Audigy's GPIO port, while sample data is
+// transmitted via proprietary EMU32 serial links. On first-generation
+// E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
+// - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
+// - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
+// Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
+// while the later cards use a single crystal and a PLL chip.
+// - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
+// sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
+// are bundled.
+// - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
+// number of usable inputs/outputs is limited, esp. with ADAT in use.
+// - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
+// to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
+// can overlap with the Dock's ADC/DAC's high channels.
+// - The code names are mentioned below and in the emu_chip_details table.
+
+/************************************************************************************************/
+/* EMU1010 FPGA registers */
+/************************************************************************************************/
+
#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
+
#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
+
#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
+
#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
/* Must be written after power on to reset DLL */
/* One is unable to detect the Audio dock without this */
@@ -1073,21 +1102,19 @@
#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
/* 0x14 - 0x1f Unused R/W registers */
-#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
-#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
-#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
-#define EMU_HANA_IRQ_ADAT 0x02
-#define EMU_HANA_IRQ_DOCK 0x04
-#define EMU_HANA_IRQ_DOCK_LOST 0x08
-#endif
+
+#define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */
+ /* Same bits as for EMU_HANA_IRQ_ENABLE */
+ /* Reading the register resets it. */
#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
-#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
+#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
-#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
-#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
+#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */
+#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */
-#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
+#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */
+ /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */
#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
@@ -1110,113 +1137,88 @@
#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
+
/* 0x30 - 0x3f Unused Read only registers */
/************************************************************************************************/
-/* EMU1010m HANA Destinations */
+/* EMU1010 Audio Destinations */
/************************************************************************************************/
-/* Hana, original 1010,1212,1820 using Alice2
- * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
+/* Hana, original 1010,1212m,1820[m] using Alice2
* 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
- * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
- * 0x01, 0x00: Dock DAC 1 Left
- * 0x01, 0x04: Dock DAC 1 Right
- * 0x01, 0x08: Dock DAC 2 Left
- * 0x01, 0x0c: Dock DAC 2 Right
- * 0x01, 0x10: Dock DAC 3 Left
- * 0x01, 0x12: PHONES Left
- * 0x01, 0x14: Dock DAC 3 Right
- * 0x01, 0x16: PHONES Right
- * 0x01, 0x18: Dock DAC 4 Left
- * 0x01, 0x1a: S/PDIF Left
- * 0x01, 0x1c: Dock DAC 4 Right
- * 0x01, 0x1e: S/PDIF Right
+ * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
+ * 0x00: Dock DAC 1 Left
+ * 0x04: Dock DAC 1 Right
+ * 0x08: Dock DAC 2 Left
+ * 0x0c: Dock DAC 2 Right
+ * 0x10: Dock DAC 3 Left
+ * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left)
+ * 0x14: Dock DAC 3 Right
+ * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right)
+ * 0x18: Dock DAC 4 Left
+ * 0x1a: S/PDIF Left
+ * 0x1c: Dock DAC 4 Right
+ * 0x1e: S/PDIF Right
* 0x02, 0x00: Hana S/PDIF Left
* 0x02, 0x01: Hana S/PDIF Right
- * 0x03, 0x00: Hanoa DAC Left
- * 0x03, 0x01: Hanoa DAC Right
+ * 0x03, 0x00: Hamoa DAC Left
+ * 0x03, 0x01: Hamoa DAC Right
* 0x04, 0x00-0x07: Hana ADAT
* 0x05, 0x00: I2S0 Left to Alice2
* 0x05, 0x01: I2S0 Right to Alice2
* 0x06, 0x00: I2S0 Left to Alice2
* 0x06, 0x01: I2S0 Right to Alice2
* 0x07, 0x00: I2S0 Left to Alice2
* 0x07, 0x01: I2S0 Right to Alice2
*
* Hana2 never released, but used Tina
* Not needed.
*
- * Hana3, rev2 1010,1212,1616 using Tina
- * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
+ * Hana3, rev2 1010,1212m,1616[m] using Tina
* 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
- * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
- * 0x01, 0x00: Dock DAC 1 Left
- * 0x01, 0x04: Dock DAC 1 Right
- * 0x01, 0x08: Dock DAC 2 Left
- * 0x01, 0x0c: Dock DAC 2 Right
- * 0x01, 0x10: Dock DAC 3 Left
- * 0x01, 0x12: Dock S/PDIF Left
- * 0x01, 0x14: Dock DAC 3 Right
- * 0x01, 0x16: Dock S/PDIF Right
- * 0x01, 0x18-0x1f: Dock ADAT 0-7
+ * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
+ * 0x00: Dock DAC 1 Left
+ * 0x04: Dock DAC 1 Right
+ * 0x08: Dock DAC 2 Left
+ * 0x0c: Dock DAC 2 Right
+ * 0x10: Dock DAC 3 Left
+ * 0x12: Dock S/PDIF Left
+ * 0x14: Dock DAC 3 Right
+ * 0x16: Dock S/PDIF Right
+ * 0x18-0x1f: Dock ADAT 0-7
* 0x02, 0x00: Hana3 S/PDIF Left
* 0x02, 0x01: Hana3 S/PDIF Right
- * 0x03, 0x00: Hanoa DAC Left
- * 0x03, 0x01: Hanoa DAC Right
+ * 0x03, 0x00: Hamoa DAC Left
+ * 0x03, 0x01: Hamoa DAC Right
* 0x04, 0x00-0x07: Hana3 ADAT 0-7
* 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
* 0x06-0x07: Not used
*
* HanaLite, rev1 0404 using Alice2
- * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
- * 0x01: Not used
- * 0x02, 0x00: S/PDIF Left
- * 0x02, 0x01: S/PDIF Right
- * 0x03, 0x00: DAC Left
- * 0x03, 0x01: DAC Right
- * 0x04-0x07: Not used
- *
- * HanaLiteLite, rev2 0404 using Alice2
- * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
+ * HanaLiteLite, rev2 0404 using Tina
+ * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
* 0x01: Not used
* 0x02, 0x00: S/PDIF Left
* 0x02, 0x01: S/PDIF Right
* 0x03, 0x00: DAC Left
* 0x03, 0x01: DAC Right
* 0x04-0x07: Not used
*
* Mana, Cardbus 1616 using Tina2
- * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
* 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
- * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
- * 0x01, 0x00: Dock DAC 1 Left
- * 0x01, 0x04: Dock DAC 1 Right
- * 0x01, 0x08: Dock DAC 2 Left
- * 0x01, 0x0c: Dock DAC 2 Right
- * 0x01, 0x10: Dock DAC 3 Left
- * 0x01, 0x12: Dock S/PDIF Left
- * 0x01, 0x14: Dock DAC 3 Right
- * 0x01, 0x16: Dock S/PDIF Right
- * 0x01, 0x18-0x1f: Dock ADAT 0-7
+ * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
+ * (same as rev2 1010)
* 0x02: Not used
* 0x03, 0x00: Mana DAC Left
* 0x03, 0x01: Mana DAC Right
* 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
* 0x05-0x07: Not used
- *
- *
*/
+
/* 32-bit destinations of signal in the Hana FPGA. Destinations are either
- * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture
- * - 16 x EMU_DST_ALICE2_EMU32_X.
- */
-/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
-/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
- * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on
- * setup of mixer control for each destination - see emumixer.c -
- * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
+ * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
+ * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into
+ * a channel depends on the mixer control setting for each destination - see
+ * emumixer.c - snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
*/
#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
@@ -1286,135 +1288,100 @@
#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
+// In S/MUX mode, the samples of one channel are adjacent.
#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
/* Additional destinations for 1616(M)/Microdock */
-/* Microdock S/PDIF OUT Left, 1st or 48kHz only */
-#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
-/* Microdock S/PDIF OUT Left, 2nd or 96kHz */
-#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
-/* Microdock S/PDIF OUT Right, 1st or 48kHz only */
-#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
-/* Microdock S/PDIF OUT Right, 2nd or 96kHz */
-#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
-/* Microdock S/PDIF ADAT 8 channel out +8 to +f */
-#define EMU_DST_MDOCK_ADAT 0x0118
-/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
-#define EMU_DST_MANA_DAC_LEFT 0x0300
-/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
-#define EMU_DST_MANA_DAC_RIGHT 0x0301
+#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
+#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
+#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
+#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
+#define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
+
+#define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
+#define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
/************************************************************************************************/
-/* EMU1010m HANA Sources */
+/* EMU1010 Audio Sources */
/************************************************************************************************/
-/* Hana, original 1010,1212,1820 using Alice2
- * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00,0x00-0x1f: Silence
- * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
- * 0x01, 0x00: Dock Mic A
- * 0x01, 0x04: Dock Mic B
- * 0x01, 0x08: Dock ADC 1 Left
- * 0x01, 0x0c: Dock ADC 1 Right
- * 0x01, 0x10: Dock ADC 2 Left
- * 0x01, 0x14: Dock ADC 2 Right
- * 0x01, 0x18: Dock ADC 3 Left
- * 0x01, 0x1c: Dock ADC 3 Right
- * 0x02, 0x00: Hana ADC Left
- * 0x02, 0x01: Hana ADC Right
+/* Hana, original 1010,1212m,1820[m] using Alice2
+ * 0x00, 0x00-0x1f: Silence
+ * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
+ * 0x00: Dock Mic A
+ * 0x04: Dock Mic B
+ * 0x08: Dock ADC 1 Left
+ * 0x0c: Dock ADC 1 Right
+ * 0x10: Dock ADC 2 Left
+ * 0x14: Dock ADC 2 Right
+ * 0x18: Dock ADC 3 Left
+ * 0x1c: Dock ADC 3 Right
+ * 0x02, 0x00: Hamoa ADC Left
+ * 0x02, 0x01: Hamoa ADC Right
* 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
* 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
* 0x04, 0x00-0x07: Hana ADAT
* 0x05, 0x00: Hana S/PDIF Left
* 0x05, 0x01: Hana S/PDIF Right
* 0x06-0x07: Not used
*
* Hana2 never released, but used Tina
* Not needed.
*
- * Hana3, rev2 1010,1212,1616 using Tina
- * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00,0x00-0x1f: Silence
- * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
- * 0x01, 0x00: Dock Mic A
- * 0x01, 0x04: Dock Mic B
- * 0x01, 0x08: Dock ADC 1 Left
- * 0x01, 0x0c: Dock ADC 1 Right
- * 0x01, 0x10: Dock ADC 2 Left
- * 0x01, 0x12: Dock S/PDIF Left
- * 0x01, 0x14: Dock ADC 2 Right
- * 0x01, 0x16: Dock S/PDIF Right
- * 0x01, 0x18-0x1f: Dock ADAT 0-7
- * 0x01, 0x18: Dock ADC 3 Left
- * 0x01, 0x1c: Dock ADC 3 Right
- * 0x02, 0x00: Hanoa ADC Left
- * 0x02, 0x01: Hanoa ADC Right
+ * Hana3, rev2 1010,1212m,1616[m] using Tina
+ * 0x00, 0x00-0x1f: Silence
+ * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
+ * 0x00: Dock Mic A
+ * 0x04: Dock Mic B
+ * 0x08: Dock ADC 1 Left
+ * 0x0c: Dock ADC 1 Right
+ * 0x10: Dock ADC 2 Left
+ * 0x12: Dock S/PDIF Left
+ * 0x14: Dock ADC 2 Right
+ * 0x16: Dock S/PDIF Right
+ * 0x18-0x1f: Dock ADAT 0-7
+ * 0x02, 0x00: Hamoa ADC Left
+ * 0x02, 0x01: Hamoa ADC Right
* 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
* 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
* 0x04, 0x00-0x07: Hana3 ADAT
* 0x05, 0x00: Hana3 S/PDIF Left
* 0x05, 0x01: Hana3 S/PDIF Right
* 0x06-0x07: Not used
*
* HanaLite, rev1 0404 using Alice2
- * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00,0x00-0x1f: Silence
+ * HanaLiteLite, rev2 0404 using Tina
+ * 0x00, 0x00-0x1f: Silence
* 0x01: Not used
* 0x02, 0x00: ADC Left
* 0x02, 0x01: ADC Right
- * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
- * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
- * 0x04: Not used
- * 0x05, 0x00: S/PDIF Left
- * 0x05, 0x01: S/PDIF Right
- * 0x06-0x07: Not used
- *
- * HanaLiteLite, rev2 0404 using Alice2
- * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00,0x00-0x1f: Silence
- * 0x01: Not used
- * 0x02, 0x00: ADC Left
- * 0x02, 0x01: ADC Right
- * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
- * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
+ * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
+ * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
* 0x04: Not used
* 0x05, 0x00: S/PDIF Left
* 0x05, 0x01: S/PDIF Right
* 0x06-0x07: Not used
*
* Mana, Cardbus 1616 using Tina2
- * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
- * 0x00,0x00-0x1f: Silence
- * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
- * 0x01, 0x00: Dock Mic A
- * 0x01, 0x04: Dock Mic B
- * 0x01, 0x08: Dock ADC 1 Left
- * 0x01, 0x0c: Dock ADC 1 Right
- * 0x01, 0x10: Dock ADC 2 Left
- * 0x01, 0x12: Dock S/PDIF Left
- * 0x01, 0x14: Dock ADC 2 Right
- * 0x01, 0x16: Dock S/PDIF Right
- * 0x01, 0x18-0x1f: Dock ADAT 0-7
- * 0x01, 0x18: Dock ADC 3 Left
- * 0x01, 0x1c: Dock ADC 3 Right
+ * 0x00, 0x00-0x1f: Silence
+ * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
+ * (same as rev2 1010)
* 0x02: Not used
- * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
- * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
+ * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
+ * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
* 0x04-0x07: Not used
- *
*/
/* 32-bit sources of signal in the Hana FPGA. The sources are routed to
- * destinations using mixer control for each destination - see emumixer.c
- * Sources are either physical inputs of FPGA,
- * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
- * 16 x EMU_SRC_ALICE_EMU32B
+ * destinations using a mixer control for each destination - see emumixer.c.
+ * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
+ * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B.
*/
#define EMU_SRC_SILENCE 0x0000 /* Silence */
#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
@@ -1459,23 +1426,20 @@
#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
+// In S/MUX mode, the samples of one channel are adjacent.
#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
/* Additional inputs for 1616(M)/Microdock */
-/* Microdock S/PDIF Left, 1st or 48kHz only */
-#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
-/* Microdock S/PDIF Left, 2nd or 96kHz */
-#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
-/* Microdock S/PDIF Right, 1st or 48kHz only */
-#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
-/* Microdock S/PDIF Right, 2nd or 96kHz */
-#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
-/* Microdock ADAT 8 channel in +8 to +f */
-#define EMU_SRC_MDOCK_ADAT 0x0118
+
+#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
+#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
+#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
+#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
+#define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */
/* 0x600 and 0x700 no used */
@@ -1642,25 +1606,37 @@ enum {
EMU_MODEL_EMU0404,
};
+// Chip-o-logy:
+// - All SB Live! cards use EMU10K1 chips
+// - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
+// - Original Audigy uses CA0100 "Alice"
+// - Audigy 2 uses CA0102/CA10200 "Alice2"
+// - Has an interface for CA0151 (P16V) "Alice3"
+// - Audigy 2 Value uses CA0108/CA10300 "Tina"
+// - Approximately a CA0102 with an on-chip CA0151 (P17V)
+// - Audigy 2 ZS NB uses CA0109 "Tina2"
+// - Cardbus version of CA0108
struct snd_emu_chip_details {
u32 vendor;
u32 device;
u32 subsystem;
unsigned char revision;
unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
+ /* Redundant with emu10k2_chip being unset. */
unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
+ /* Redundant with ca0108_chip being unset. */
unsigned char ca0108_chip; /* Audigy 2 Value */
unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
unsigned char ca0151_chip; /* P16V */
unsigned char spk71; /* Has 7.1 speakers */
unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
unsigned char spdif_bug; /* Has Spdif phasing bug */
unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
unsigned char ecard; /* APS EEPROM */
unsigned char emu_model; /* EMU model type */
- unsigned char spi_dac; /* SPI interface for DAC */
- unsigned char i2c_adc; /* I2C interface for ADC */
+ unsigned char spi_dac; /* SPI interface for DAC; requires ca0108_chip */
+ unsigned char i2c_adc; /* I2C interface for ADC; requires ca0108_chip */
unsigned char adc_1361t; /* Use Philips 1361T ADC */
unsigned char invert_shared_spdif; /* analog/digital switch inverted */
const char *driver;
@@ -1734,9 +1710,9 @@ struct snd_emu10k1 {
void *synth;
int (*get_synth_voice)(struct snd_emu10k1 *emu);
- spinlock_t reg_lock;
- spinlock_t emu_lock;
- spinlock_t voice_lock;
+ spinlock_t reg_lock; // high-level driver lock
+ spinlock_t emu_lock; // low-level i/o lock
+ spinlock_t voice_lock; // voice allocator lock
spinlock_t spi_lock; /* serialises access to spi port */
spinlock_t i2c_lock; /* serialises access to i2c port */
diff --git a/include/uapi/sound/emu10k1.h b/include/uapi/sound/emu10k1.h
index c2414bd5aecd..33e5228f5d8c 100644
--- a/include/uapi/sound/emu10k1.h
+++ b/include/uapi/sound/emu10k1.h
@@ -111,6 +111,9 @@
#define CC_REG_NONZERO C_00000100
/* FX buses */
+// These are arbitrary mappings; our DSP code simply expects
+// the config files to route the channels this way.
+// The numbers are documented in {audigy,sb-live}-mixer.rst.
#define FXBUS_PCM_LEFT 0x00
#define FXBUS_PCM_RIGHT 0x01
#define FXBUS_PCM_LEFT_REAR 0x02
diff --git a/sound/pci/emu10k1/emu10k1.c b/sound/pci/emu10k1/emu10k1.c
index 672af4b9597b..b8163f26004a 100644
--- a/sound/pci/emu10k1/emu10k1.c
+++ b/sound/pci/emu10k1/emu10k1.c
@@ -68,17 +68,6 @@ static const struct pci_device_id snd_emu10k1_ids[] = {
{ 0, }
};
-/*
- * Audigy 2 Value notes:
- * A_IOCFG Input (GPIO)
- * 0x400 = Front analog jack plugged in. (Green socket)
- * 0x1000 = Read analog jack plugged in. (Black socket)
- * 0x2000 = Center/LFE analog jack plugged in. (Orange socket)
- * A_IOCFG Output (GPIO)
- * 0x60 = Sound out of front Left.
- * Win sets it to 0xXX61
- */
-
MODULE_DEVICE_TABLE(pci, snd_emu10k1_ids);
static int snd_card_emu10k1_probe(struct pci_dev *pci,
diff --git a/sound/pci/emu10k1/emu10k1_main.c b/sound/pci/emu10k1/emu10k1_main.c
index c37df604d470..39b63c4ca1df 100644
--- a/sound/pci/emu10k1/emu10k1_main.c
+++ b/sound/pci/emu10k1/emu10k1_main.c
@@ -162,6 +162,8 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir)
outl(0, emu->port + INTE);
snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
+
+ /* disable stop on loop end */
snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
@@ -660,13 +662,14 @@ static int snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu,
return -EIO;
/* The FPGA is a Xilinx Spartan IIE XC2S50E */
+ /* On E-MU 0404b it is a Xilinx Spartan III XC3S50 */
/* GPIO7 -> FPGA PGMN
* GPIO6 -> FPGA CCLK
* GPIO5 -> FPGA DIN
* FPGA CONFIG OFF -> FPGA PGMN
*/
spin_lock_irqsave(&emu->emu_lock, flags);
- outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 1uS. */
+ outw(0x00, emu->port + A_GPIO); /* Set PGMN low for 100uS. */
write_post = inw(emu->port + A_GPIO);
udelay(100);
outw(0x80, emu->port + A_GPIO); /* Leave bit 7 set during netlist setup. */
@@ -782,41 +785,18 @@ static void emu1010_firmware_work(struct work_struct *work)
} else if (!reg && emu->emu1010.last_reg) {
/* Audio Dock removed */
dev_info(emu->card->dev, "emu1010: Audio Dock detached\n");
- /* Unmute all */
+ /* The hardware auto-mutes all, so we unmute again */
snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
}
next:
emu->emu1010.last_reg = reg;
if (!emu->card->shutdown)
schedule_delayed_work(&emu->emu1010.firmware_work,
msecs_to_jiffies(1000));
}
/*
- * EMU-1010 - details found out from this driver, official MS Win drivers,
- * testing the card:
- *
- * Audigy2 (aka Alice2):
- * ---------------------
- * * communication over PCI
- * * conversion of 32-bit data coming over EMU32 links from HANA FPGA
- * to 2 x 16-bit, using internal DSP instructions
- * * slave mode, clock supplied by HANA
- * * linked to HANA using:
- * 32 x 32-bit serial EMU32 output channels
- * 16 x EMU32 input channels
- * (?) x I2S I/O channels (?)
- *
- * FPGA (aka HANA):
- * ---------------
- * * provides all (?) physical inputs and outputs of the card
- * (ADC, DAC, SPDIF I/O, ADAT I/O, etc.)
- * * provides clock signal for the card and Alice2
- * * two crystals - for 44.1kHz and 48kHz multiples
- * * provides internal routing of signal sources to signal destinations
- * * inputs/outputs to Alice2 - see above
- *
* Current status of the driver:
* ----------------------------
* * only 44.1/48kHz supported (the MS Win driver supports up to 192 kHz)
@@ -884,11 +864,8 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ®);
dev_info(emu->card->dev, "emu1010: Card options = 0x%x\n", reg);
/* Optical -> ADAT I/O */
- /* 0 : SPDIF
- * 1 : ADAT
- */
emu->emu1010.optical_in = 1; /* IN_ADAT */
- emu->emu1010.optical_out = 1; /* IN_ADAT */
+ emu->emu1010.optical_out = 1; /* OUT_ADAT */
tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
(emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
@@ -1279,6 +1256,15 @@ static const struct snd_emu_chip_details emu_chip_details[] = {
* AC97: STAC9750
* CA0151: None
*/
+ /*
+ * A_IOCFG Input (GPIO)
+ * 0x400 = Front analog jack plugged in. (Green socket)
+ * 0x1000 = Rear analog jack plugged in. (Black socket)
+ * 0x2000 = Center/LFE analog jack plugged in. (Orange socket)
+ * A_IOCFG Output (GPIO)
+ * 0x60 = Sound out of front Left.
+ * Win sets it to 0xXX61
+ */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
.driver = "Audigy2", .name = "SB Audigy 2 Value [SB0400]",
.id = "Audigy2",
@@ -1327,67 +1313,85 @@ static const struct snd_emu_chip_details emu_chip_details[] = {
.spi_dac = 1,
.i2c_adc = 1,
.spk71 = 1} ,
+ /* This is MAEM8950 "Mana" */
+ /* Attach MicroDock[M] to make it an E-MU 1616[m]. */
+ /* Does NOT support sync daughter card (obviously). */
/* Tested by James@superbug.co.uk 4th Nov 2007. */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x42011102,
.driver = "Audigy2", .name = "E-mu 1010 Notebook [MAEM8950]",
.id = "EMU1010",
.emu10k2_chip = 1,
.ca0108_chip = 1,
.ca_cardbus_chip = 1,
.spk71 = 1 ,
.emu_model = EMU_MODEL_EMU1616},
/* Tested by James@superbug.co.uk 4th Nov 2007. */
- /* This is MAEM8960, 0202 is MAEM 8980 */
+ /* This is MAEM8960 "Hana3", 0202 is MAEM8980 */
+ /* Attach 0202 daughter card to make it an E-MU 1212m, OR a
+ * MicroDock[M] to make it an E-MU 1616[m]. */
+ /* Does NOT support sync daughter card. */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40041102,
.driver = "Audigy2", .name = "E-mu 1010b PCI [MAEM8960]",
.id = "EMU1010",
.emu10k2_chip = 1,
.ca0108_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 new revision */
/* Tested by Maxim Kachur <mcdebugger@duganet.ru> 17th Oct 2012. */
/* This is MAEM8986, 0202 is MAEM8980 */
+ /* Attach 0202 daughter card to make it an E-MU 1212m, OR a
+ * MicroDockM to make it an E-MU 1616m. The non-m
+ * version was never sold with this card, but should
+ * still work. */
+ /* Does NOT support sync daughter card. */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40071102,
.driver = "Audigy2", .name = "E-mu 1010 PCIe [MAEM8986]",
.id = "EMU1010",
.emu10k2_chip = 1,
.ca0108_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU1010B}, /* EMU 1010 PCIe */
/* Tested by James@superbug.co.uk 8th July 2005. */
- /* This is MAEM8810, 0202 is MAEM8820 */
+ /* This is MAEM8810 "Hana", 0202 is MAEM8820 "Hamoa" */
+ /* Attach 0202 daughter card to make it an E-MU 1212m, OR an
+ * AudioDock[M] to make it an E-MU 1820[m]. */
+ /* Supports sync daughter card. */
{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
.driver = "Audigy2", .name = "E-mu 1010 [MAEM8810]",
.id = "EMU1010",
.emu10k2_chip = 1,
.ca0102_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU1010}, /* EMU 1010 old revision */
- /* EMU0404b */
+ /* This is MAEM8852 "HanaLiteLite" */
+ /* Supports sync daughter card. */
+ /* Tested by oswald.buddenhagen@gmx.de Mar 2023. */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40021102,
.driver = "Audigy2", .name = "E-mu 0404b PCI [MAEM8852]",
.id = "EMU0404",
.emu10k2_chip = 1,
.ca0108_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 new revision */
+ /* This is MAEM8850 "HanaLite" */
+ /* Supports sync daughter card. */
/* Tested by James@superbug.co.uk 20-3-2007. */
{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40021102,
.driver = "Audigy2", .name = "E-mu 0404 [MAEM8850]",
.id = "EMU0404",
.emu10k2_chip = 1,
.ca0102_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 */
/* EMU0404 PCIe */
+ /* Does NOT support sync daughter card. */
{.vendor = 0x1102, .device = 0x0008, .subsystem = 0x40051102,
.driver = "Audigy2", .name = "E-mu 0404 PCIe [MAEM8984]",
.id = "EMU0404",
.emu10k2_chip = 1,
.ca0108_chip = 1,
.spk71 = 1,
.emu_model = EMU_MODEL_EMU0404}, /* EMU 0404 PCIe ver_03 */
- /* Note that all E-mu cards require kernel 2.6 or newer. */
{.vendor = 0x1102, .device = 0x0008,
.driver = "Audigy2", .name = "SB Audigy 2 Value [Unknown]",
.id = "Audigy2",
@@ -1468,6 +1472,8 @@ static const struct snd_emu_chip_details emu_chip_details[] = {
.spdif_bug = 1,
.adc_1361t = 1, /* 24 bit capture instead of 16bit */
.ac97_chip = 1} ,
+ /* Audigy 2 Platinum EX */
+ /* Win driver sets A_IOCFG output to 0x1c00 */
{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
.driver = "Audigy2", .name = "Audigy 2 Platinum EX [SB0280]",
.id = "Audigy2",
@@ -1488,6 +1494,8 @@ static const struct snd_emu_chip_details emu_chip_details[] = {
.spdif_bug = 1,
.invert_shared_spdif = 1, /* digital/analog switch swapped */
.ac97_chip = 1} ,
+ /* Audigy 2 Platinum */
+ /* Win driver sets A_IOCFG output to 0xa00 */
{.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
.driver = "Audigy2", .name = "SB Audigy 2 Platinum [SB0240P]",
.id = "Audigy2",
@@ -1593,6 +1601,9 @@ static const struct snd_emu_chip_details emu_chip_details[] = {
.emu10k1_chip = 1,
.ac97_chip = 1,
.sblive51 = 1} ,
+ /* SB Live! Platinum */
+ /* Win driver sets A_IOCFG output to 0 */
+ /* Tested by Jonathan Dowland <jon@dow.land> Apr 2023. */
{.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
.driver = "EMU10K1", .name = "SB Live! Platinum [CT4760P]",
.id = "Live",
diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c
index 6a51aed59238..510b776f856d 100644
--- a/sound/pci/emu10k1/emufx.c
+++ b/sound/pci/emu10k1/emufx.c
@@ -1187,8 +1187,8 @@ snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl
}
/*
- * Used for emu1010 - conversion from 32-bit capture inputs from HANA
- * to 2 x 16-bit registers in audigy - their values are read via DMA.
+ * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA
+ * to 2 x 16-bit registers in Audigy - their values are read via DMA.
* Conversion is performed by Audigy DSP instructions of FX8010.
*/
static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
@@ -1330,8 +1330,9 @@ static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
#define A_ADD_VOLUME_IN(var,vol,input) \
A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
- /* emu1212 DSP 0 and DSP 1 Capture */
if (emu->card_capabilities->emu_model) {
+ /* EMU1010 DSP 0 and DSP 1 Capture */
+ // The 24 MSB hold the actual value. We implicitly discard the 16 LSB.
if (emu->card_capabilities->ca0108_chip) {
/* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
@@ -1636,17 +1637,20 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
#endif
if (emu->card_capabilities->emu_model) {
+ /* Capture 16 channels of S32_LE sound. */
if (emu->card_capabilities->ca0108_chip) {
dev_info(emu->card->dev, "EMU2 inputs on\n");
+ /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */
+
for (z = 0; z < 0x10; z++) {
snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
bit_shifter16,
A3_EMU32IN(z),
A_FXBUS2(z*2) );
}
} else {
dev_info(emu->card->dev, "EMU inputs on\n");
- /* Capture 16 (originally 8) channels of S32_LE sound */
+ /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */
/*
dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
diff --git a/sound/pci/emu10k1/emumixer.c b/sound/pci/emu10k1/emumixer.c
index 754d91050af2..3d2ed5e0a59d 100644
--- a/sound/pci/emu10k1/emumixer.c
+++ b/sound/pci/emu10k1/emumixer.c
@@ -346,7 +346,7 @@ static const unsigned int emu1616_output_dst[] = {
};
/*
- * Data destinations - HANA outputs going to Alice2 (audigy) for
+ * Data destinations - FPGA outputs going to Alice2 (Audigy) for
* capture (EMU32 + I2S links)
* Each destination has an enum mixer control to choose a data source
*/
@@ -367,6 +367,7 @@ static const unsigned int emu1010_input_dst[] = {
EMU_DST_ALICE2_EMU32_D,
EMU_DST_ALICE2_EMU32_E,
EMU_DST_ALICE2_EMU32_F,
+ /* These exist only on rev1 EMU1010 cards. */
EMU_DST_ALICE_I2S0_LEFT,
EMU_DST_ALICE_I2S0_RIGHT,
EMU_DST_ALICE_I2S1_LEFT,
@@ -708,7 +709,7 @@ static int snd_emu1010_internal_clock_put(struct snd_kcontrol *kcontrol,
/* 44100 */
/* Mute all */
snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_MUTE );
- /* Default fallback clock 48kHz */
+ /* Default fallback clock 44.1kHz */
snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_44_1K );
/* Word Clock source, Internal 44.1kHz x1 */
snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK,
diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c
index 87c3b19c6b2d..ff6ca91b0d28 100644
--- a/sound/pci/emu10k1/emupcm.c
+++ b/sound/pci/emu10k1/emupcm.c
@@ -326,7 +326,6 @@ static void snd_emu10k1_pcm_init_voice(struct snd_emu10k1 *emu,
} else
snd_emu10k1_ptr_write(emu, FXRT, voice,
snd_emu10k1_compose_send_routing(send_routing));
- /* Stop CA */
/* Assumption that PT is already 0 so no harm overwriting */
snd_emu10k1_ptr_write(emu, PTRX, voice, (send_amount[0] << 8) | send_amount[1]);
snd_emu10k1_ptr_write(emu, DSL, voice, end_addr | (send_amount[3] << 24));
@@ -480,9 +479,6 @@ static int snd_emu10k1_efx_playback_prepare(struct snd_pcm_substream *substream)
start_addr = epcm->start_addr;
end_addr = epcm->start_addr + snd_pcm_lib_buffer_bytes(substream);
- /*
- * the kX driver leaves some space between voices
- */
channel_size = ( end_addr - start_addr ) / NUM_EFX_PLAYBACK;
snd_emu10k1_pcm_init_voice(emu, 1, 1, epcm->extra,
@@ -1218,26 +1214,25 @@ static int snd_emu10k1_capture_efx_open(struct snd_pcm_substream *substream)
runtime->hw.rate_min = runtime->hw.rate_max = 48000;
spin_lock_irq(&emu->reg_lock);
if (emu->card_capabilities->emu_model) {
- /* Nb. of channels has been increased to 16 */
/* TODO
- * SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE
* SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
* SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
* SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000
* rate_min = 44100,
* rate_max = 192000,
* channels_min = 16,
* channels_max = 16,
* Need to add mixer control to fix sample rate
*
* There are 32 mono channels of 16bits each.
- * 24bit Audio uses 2x channels over 16bit
- * 96kHz uses 2x channels over 48kHz
- * 192kHz uses 4x channels over 48kHz
- * So, for 48kHz 24bit, one has 16 channels
- * for 96kHz 24bit, one has 8 channels
- * for 192kHz 24bit, one has 4 channels
- *
+ * 24bit Audio uses 2x channels over 16bit,
+ * 96kHz uses 2x channels over 48kHz,
+ * 192kHz uses 4x channels over 48kHz.
+ * So, for 48kHz 24bit, one has 16 channels,
+ * for 96kHz 24bit, one has 8 channels,
+ * for 192kHz 24bit, one has 4 channels.
+ * 1010rev2 and 1616(m) cards have double that,
+ * but we don't exceed 16 channels anyway.
*/
#if 1
switch (emu->emu1010.internal_clock) {
@@ -1459,11 +1454,12 @@ static int snd_emu10k1_pcm_efx_voices_mask_put(struct snd_kcontrol *kcontrol, st
nval[idx / 32] |= 1 << (idx % 32);
bits++;
}
-
+
+ // Check that the number of requested channels is a power of two
+ // not bigger than the number of available channels.
for (idx = 0; idx < nefxb; idx++)
if (1 << idx == bits)
break;
-
if (idx >= nefxb)
return -EINVAL;
diff --git a/sound/pci/emu10k1/io.c b/sound/pci/emu10k1/io.c
index 42b06f2e5552..c60573f14ea8 100644
--- a/sound/pci/emu10k1/io.c
+++ b/sound/pci/emu10k1/io.c
@@ -314,7 +314,6 @@ void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenu
unsigned int val;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(CLIEH << 16, emu->port + PTR);
val = inl(emu->port + DATA);
@@ -334,7 +333,6 @@ void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicen
unsigned int val;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(CLIEH << 16, emu->port + PTR);
val = inl(emu->port + DATA);
@@ -353,7 +351,6 @@ void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
unsigned long flags;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(CLIPH << 16, emu->port + PTR);
voicenum = 1 << (voicenum - 32);
@@ -371,7 +368,6 @@ void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned i
unsigned int val;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(HLIEH << 16, emu->port + PTR);
val = inl(emu->port + DATA);
@@ -391,7 +387,6 @@ void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned
unsigned int val;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(HLIEH << 16, emu->port + PTR);
val = inl(emu->port + DATA);
@@ -410,7 +405,6 @@ void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int
unsigned long flags;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(HLIPH << 16, emu->port + PTR);
voicenum = 1 << (voicenum - 32);
@@ -428,7 +422,6 @@ void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voice
unsigned int sol;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(SOLEH << 16, emu->port + PTR);
sol = inl(emu->port + DATA);
@@ -448,7 +441,6 @@ void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voi
unsigned int sol;
spin_lock_irqsave(&emu->emu_lock, flags);
- /* voice interrupt */
if (voicenum >= 32) {
outl(SOLEH << 16, emu->port + PTR);
sol = inl(emu->port + DATA);
diff --git a/sound/pci/emu10k1/p16v.h b/sound/pci/emu10k1/p16v.h
index 3cdafa311617..9d429ad1feff 100644
--- a/sound/pci/emu10k1/p16v.h
+++ b/sound/pci/emu10k1/p16v.h
@@ -64,7 +64,7 @@
*/
/********************************************************************************************************/
-/* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
+/* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
/********************************************************************************************************/
/* The sample rate of the SPDIF outputs is set by modifying a register in the EMU10K2 PTR register A_SPDIF_SAMPLERATE.
diff --git a/sound/pci/emu10k1/p17v.h b/sound/pci/emu10k1/p17v.h
index 3a6568346fad..d4ada1c430c8 100644
--- a/sound/pci/emu10k1/p17v.h
+++ b/sound/pci/emu10k1/p17v.h
@@ -6,8 +6,8 @@
*/
/******************************************************************************/
-/* Audigy2Value Tina (P17V) pointer-offset register set,
- * accessed through the PTR20 and DATA24 registers */
+/* Audigy2Value Tina (P17V) pointer-offset register set, */
+/* accessed through the PTR2 and DATA2 registers */
/******************************************************************************/
/* 00 - 07: Not used */
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/7] ALSA: emu10k1: fix lineup of EMU_HANA_* defines
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 1/7] ALSA: emu10k1: comment updates Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 3/7] ALSA: emu10k1: eliminate some unused defines Oswald Buddenhagen
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
The bit values are supposed to be internally indented by one step
relative to the register addresses.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 7786d5807679..35a60bdcf641 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1072,44 +1072,44 @@
#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
-#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
-#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
-#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
-#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
+#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
+#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
+#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
+#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
-#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
-#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
-#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
-#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
+#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
+#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
+#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
+#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
-#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
-#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
-#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
-#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
-#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
+#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
+#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
+#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
+#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
+#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
-#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
-#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
-#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
-#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
-#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
+#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
+#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
+#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
+#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
+#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
/* 0x14 - 0x1f Unused R/W registers */
#define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */
/* Same bits as for EMU_HANA_IRQ_ENABLE */
/* Reading the register resets it. */
#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
-#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
-#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
+#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
+#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */
#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */
@@ -1123,8 +1123,8 @@
#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
-#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
-#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
+#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
+#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/7] ALSA: emu10k1: eliminate some unused defines
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 1/7] ALSA: emu10k1: comment updates Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 2/7] ALSA: emu10k1: fix lineup of EMU_HANA_* defines Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 4/7] ALSA: emu10k1: remove some bogus defines Oswald Buddenhagen
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
One might be mislead to think that these mean anything.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 35a60bdcf641..931f3016d60d 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -25,21 +25,16 @@
/* ------------------- DEFINES -------------------- */
#define EMUPAGESIZE 4096
-#define MAXREQVOICES 8
#define MAXPAGES0 4096 /* 32 bit mode */
#define MAXPAGES1 8192 /* 31 bit mode */
-#define RESERVED 0
-#define NUM_MIDI 16
#define NUM_G 64 /* use all channels */
-#define NUM_FXSENDS 4
#define NUM_EFX_PLAYBACK 16
/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
#define TMEMSIZE 256*1024
-#define TMEMSIZEREG 4
#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
@@ -283,7 +278,6 @@
/* before the new rate is guaranteed accurate. */
#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
/* 0 == 1024 periods, [1..4] are not useful */
-#define TIMER_RATE 0x0a00001a
#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/7] ALSA: emu10k1: remove some bogus defines
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
` (2 preceding siblings ...)
2023-04-22 16:10 ` [PATCH 3/7] ALSA: emu10k1: eliminate some unused defines Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 5/7] ALSA: emu10k1: pull in some register definitions from kX-project Oswald Buddenhagen
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
Firstly, remove the FXWC_* defines - the comment on FXWC implies that
the relevant defines are the (A_)EXTOUT_* ones. It's unclear where this
came from - it was in the initial ALSA import, but neither the driver
from Creative nor kX-project have these defines.
Secondly, remove A_HR, which made plain no sense (was unused, and
clashed with FXRT). Amends commit cbb7d8f9b7b ("emu10k1: Update
registers defines for the Audigy 2/emu10k2.5").
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 15 ---------------
sound/pci/emu10k1/emupcm.c | 1 -
2 files changed, 16 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 931f3016d60d..6927fac1aa5f 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -471,7 +471,6 @@
#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
-#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
#define MAPA 0x0c /* Cache map A */
#define MAPB 0x0d /* Cache map B */
@@ -626,20 +625,6 @@
/* is 16bit, 48KHz only. All 32 channels can be enabled */
/* simultaneously. */
-#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
-#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
-#define FXWC_DEFAULTROUTE_A (1<<12)
-#define FXWC_DEFAULTROUTE_D (1<<13)
-#define FXWC_ADCLEFT (1<<18)
-#define FXWC_CDROMSPDIFLEFT (1<<18)
-#define FXWC_ADCRIGHT (1<<19)
-#define FXWC_CDROMSPDIFRIGHT (1<<19)
-#define FXWC_MIC (1<<20)
-#define FXWC_ZOOMLEFT (1<<20)
-#define FXWC_ZOOMRIGHT (1<<21)
-#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
-#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
-
#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
#define TCBS 0x44 /* Tank cache buffer size register */
diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c
index ff6ca91b0d28..b0c0ef342756 100644
--- a/sound/pci/emu10k1/emupcm.c
+++ b/sound/pci/emu10k1/emupcm.c
@@ -1749,7 +1749,6 @@ int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device)
* to these
*/
- /* emu->efx_voices_mask[0] = FXWC_DEFAULTROUTE_C | FXWC_DEFAULTROUTE_A; */
if (emu->audigy) {
emu->efx_voices_mask[0] = 0;
if (emu->card_capabilities->emu_model)
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/7] ALSA: emu10k1: pull in some register definitions from kX-project
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
` (3 preceding siblings ...)
2023-04-22 16:10 ` [PATCH 4/7] ALSA: emu10k1: remove some bogus defines Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 6/7] ALSA: emu10k1: fixup DSP defines Oswald Buddenhagen
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
For documentation purposes and later use.
Some pre-existing but (mostly) unused definitions were renamed for
consistency.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 78 ++++++++++++++++++++++----------
sound/pci/emu10k1/emu10k1_main.c | 2 +-
2 files changed, 56 insertions(+), 24 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 6927fac1aa5f..0d288cc618c1 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -61,8 +61,8 @@
/* the relevant bits and zero to the other bits */
#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
to interrupt */
-#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
- which INTE bits enable it) */
+#define IPR_WATERMARK_REACHED 0x40000000
+#define IPR_A_GPIO 0x20000000 /* GPIO input pin change */
/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
@@ -122,10 +122,14 @@
/* behavior and possibly random segfaults and */
/* lockups if enabled. */
+#define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */
+
/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
+#define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000
+#define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000
#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
/* NOTE: This bit must always be enabled */
@@ -146,9 +150,10 @@
#define WC 0x10 /* Wall Clock register */
#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
#define WC_SAMPLECOUNTER 0x14060010
-#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
+#define WC_CURRENTCHANNEL_MASK 0x0000003F /* Channel [0..63] currently being serviced */
/* NOTE: Each channel takes 1/64th of a sample */
/* period to be serviced. */
+#define WC_CURRENTCHANNEL 0x06000010
#define HCFG 0x14 /* Hardware config register */
/* NOTE: There is no reason to use the legacy */
@@ -276,7 +281,7 @@
/* NOTE: After the rate is changed, a maximum */
/* of 1024 sample periods should be allowed */
/* before the new rate is guaranteed accurate. */
-#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
+#define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
/* 0 == 1024 periods, [1..4] are not useful */
#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
@@ -425,7 +430,7 @@
#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
-#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
+#define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */
/* 1 == full band, 7 == lowpass */
/* ROM 0 is used when pitch shifting downward or less */
/* then 3 semitones upward. Increasingly higher ROM */
@@ -487,7 +492,7 @@
/* 0x8000-n == 666*n usec delay */
#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
-#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
+#define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
/* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
@@ -510,7 +515,7 @@
/* 0x8000-n == 666*n usec delay */
#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
-#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
+#define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
/* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
@@ -839,34 +844,45 @@
#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
-/* Extended Hardware Control */
-#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
-#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
-#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
-#define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
+#define A_EHC 0x76 /* Extended Hardware Control */
+
+#define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */
#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
-#define A_SPDIF_48000 0x00000000
+#define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */
#define A_SPDIF_192000 0x00000020
#define A_SPDIF_96000 0x00000040
#define A_SPDIF_44100 0x00000080
+#define A_SPDIF_MUTED 0x000000c0
#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
#define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
#define A_I2S_CAPTURE_192000 0x00000200
#define A_I2S_CAPTURE_96000 0x00000400
#define A_I2S_CAPTURE_44100 0x00000800
-#define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
-#define A_PCM_48000 0x00000000
-#define A_PCM_192000 0x00002000
-#define A_PCM_96000 0x00004000
-#define A_PCM_44100 0x00008000
+#define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
+#define A_EHC_SRC48_BYPASS 0x00000000
+#define A_EHC_SRC48_192 0x00002000
+#define A_EHC_SRC48_96 0x00004000
+#define A_EHC_SRC48_44 0x00008000
+#define A_EHC_SRC48_MUTED 0x0000c000
+
+#define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */
+#define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */
+#define A_EHC_P17V_SEL1_MASK 0x000c0000
+#define A_EHC_P17V_SEL2_MASK 0x00300000
+#define A_EHC_P17V_SEL3_MASK 0x00c00000
+
+#define A_EHC_ASYNC_BYPASS 0x80000000
#define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
#define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
#define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
+#define A_SRT_ESTSAMPLERATE 0x001fffff
+#define A_SRT_RATELOCKED 0x01000000
+
#define A_TTDA 0x7a /* Tank Table DMA Address */
#define A_TTDD 0x7b /* Tank Table DMA Data */
@@ -981,7 +997,7 @@
#define EMU_HANA_WCLOCK_INT_44_1K 0x01
#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
-#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
+#define EMU_HANA_WCLOCK_SYNC_BNC 0x04
#define EMU_HANA_WCLOCK_2ND_HANA 0x05
#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
@@ -1010,23 +1026,27 @@
#define EMU_HANA_IRQ_DOCK_LOST 0x08
#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
-#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
+#define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00
#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
-#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
+#define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00
#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
#define EMU_HANA_OPTICAL_IN_ADAT 0x01
#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
-#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
-#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
+#define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */
+#define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
+#define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
+#define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */
+#define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
+#define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
@@ -1119,6 +1139,10 @@
/* 0x30 - 0x3f Unused Read only registers */
+// The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
+#define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */
+#define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */
+
/************************************************************************************************/
/* EMU1010 Audio Destinations */
/************************************************************************************************/
@@ -1257,8 +1281,12 @@
#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
+#define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */
+#define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */
#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
+#define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */
+#define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */
#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
@@ -1409,8 +1437,12 @@
#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
+#define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */
+#define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */
#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
+#define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */
+#define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */
/* Additional inputs for 1616(M)/Microdock */
diff --git a/sound/pci/emu10k1/emu10k1_main.c b/sound/pci/emu10k1/emu10k1_main.c
index 39b63c4ca1df..007c445d72bf 100644
--- a/sound/pci/emu10k1/emu10k1_main.c
+++ b/sound/pci/emu10k1/emu10k1_main.c
@@ -1953,7 +1953,7 @@ static const unsigned char saved_regs[] = {
0xff /* end */
};
static const unsigned char saved_regs_audigy[] = {
- A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
+ A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_EHC,
A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
0xff /* end */
};
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/7] ALSA: emu10k1: fixup DSP defines
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
` (4 preceding siblings ...)
2023-04-22 16:10 ` [PATCH 5/7] ALSA: emu10k1: pull in some register definitions from kX-project Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers Oswald Buddenhagen
2023-04-23 7:27 ` [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Takashi Iwai
7 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
Firstly, fix the distribution between public and private headers.
Otherwise, some of the already public macros wouldn't actually work, and
the SNDRV_EMU10K1_IOCTL_DBG_READ result for Audigy would be useless.
Secondly, add condition code registers for Audigy. These are just
aliases for selected constant registers, and thus are generation-
specific. At least A_CC_REG_ZERO is actually correct ...
Finally, shuffle around some defines to more logical places while at it,
and fix up some more comments.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
include/sound/emu10k1.h | 46 ++---------
include/uapi/sound/emu10k1.h | 144 ++++++++++++++++++++++-------------
2 files changed, 99 insertions(+), 91 deletions(-)
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 0d288cc618c1..5958cae819fd 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -704,18 +704,15 @@
#define GPSCS 0x51 /* General Purpose SPDIF channel status register */
+// Corresponding EMU10K1_DBG_* constants are in the public header
#define DBG 0x52
#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
-#define A_DBG 0x53
-#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
-#define A_DBG_ZC 0x40000000 /* zero tram counter */
-#define A_DBG_STEP_ADDR 0x000003ff
-#define A_DBG_SATURATION_OCCURED 0x20000000
-#define A_DBG_SATURATION_ADDR 0x0ffc0000
+// Corresponding A_DBG_* constants are in the public header
+#define A_DBG 0x53
// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
@@ -908,45 +905,14 @@
#define A_FXRT_CHANNELD 0x3f000000
/* 0x7f: Not used */
-/* Each FX general purpose register is 32 bits in length, all bits are used */
-#define FXGPREGBASE 0x100 /* FX general purpose registers base */
-#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
-#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
-#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
-
-/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
-/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
-/* locations are for external TRAM. */
-#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
-#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
-
-/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
-#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
-#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
-#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
-#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
-#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
-#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
-
-#define MICROCODEBASE 0x400 /* Microcode data base address */
+/* The public header defines the GPR and TRAM base addresses that
+ * are valid for _both_ CPU and DSP addressing. */
/* Each DSP microcode instruction is mapped into 2 doublewords */
/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
-#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
-#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
-#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
-#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
-#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
-
-
-/* Audigy Soundcard have a different instruction format */
+#define MICROCODEBASE 0x400 /* Microcode data base address */
#define A_MICROCODEBASE 0x600
-#define A_LOWORD_OPY_MASK 0x000007ff
-#define A_LOWORD_OPX_MASK 0x007ff000
-#define A_HIWORD_OPCODE_MASK 0x0f000000
-#define A_HIWORD_RESULT_MASK 0x007ff000
-#define A_HIWORD_OPA_MASK 0x000007ff
/************************************************************************************************/
diff --git a/include/uapi/sound/emu10k1.h b/include/uapi/sound/emu10k1.h
index 33e5228f5d8c..c8e131d6da00 100644
--- a/include/uapi/sound/emu10k1.h
+++ b/include/uapi/sound/emu10k1.h
@@ -43,13 +43,36 @@
#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
+#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
+#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
+#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
+#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
+#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
+
+/* Audigy Soundcards have a different instruction format */
+#define A_LOWORD_OPX_MASK 0x007ff000
+#define A_LOWORD_OPY_MASK 0x000007ff
+#define A_HIWORD_OPCODE_MASK 0x0f000000
+#define A_HIWORD_RESULT_MASK 0x007ff000
+#define A_HIWORD_OPA_MASK 0x000007ff
+
/* GPRs */
#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
/* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
+#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
+#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
+#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
+#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
+#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
+#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" */
+#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_01 - _0F" */
+#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x1f "EMU32_IN_00 - _1F" - Only when .device = 0x0008 */
+#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x1f "EMU32_OUT_00 - _1F" - Only when .device = 0x0008 */
+
#define C_00000000 0x40
#define C_00000001 0x41
#define C_00000002 0x42
@@ -78,38 +101,88 @@
#define GPR_NOISE1 0x59 /* noise source */
#define GPR_IRQ 0x5a /* IRQ register */
#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
+
+/* Audigy constants */
+#define A_C_00000000 0xc0
+#define A_C_00000001 0xc1
+#define A_C_00000002 0xc2
+#define A_C_00000003 0xc3
+#define A_C_00000004 0xc4
+#define A_C_00000008 0xc5
+#define A_C_00000010 0xc6
+#define A_C_00000020 0xc7
+#define A_C_00000100 0xc8
+#define A_C_00010000 0xc9
+#define A_C_00000800 0xca
+#define A_C_10000000 0xcb
+#define A_C_20000000 0xcc
+#define A_C_40000000 0xcd
+#define A_C_80000000 0xce
+#define A_C_7fffffff 0xcf
+#define A_C_ffffffff 0xd0
+#define A_C_fffffffe 0xd1
+#define A_C_c0000000 0xd2
+#define A_C_4f1bbcdc 0xd3
+#define A_C_5a7ef9db 0xd4
+#define A_C_00100000 0xd5
+#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
+#define A_GPR_COND 0xd7 /* CCR, condition register */
+#define A_GPR_NOISE0 0xd8 /* noise source */
+#define A_GPR_NOISE1 0xd9 /* noise source */
+#define A_GPR_IRQ 0xda /* IRQ register */
+#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
+#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
+
+/* Each FX general purpose register is 32 bits in length, all bits are used */
+#define FXGPREGBASE 0x100 /* FX general purpose registers base */
+#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
+
+#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
+#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
+
+/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
+/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
+/* locations are for external TRAM. */
+#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
+#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
+
+/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
+#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
+#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
+#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
+#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
+#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
+#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
+
#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
+#define A_GPR(x) (A_FXGPREGBASE + (x))
#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
-#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
-#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
-#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
-#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
-#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
-#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
-#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
-#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
-#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
-#define A_GPR(x) (A_FXGPREGBASE + (x))
-
/* cc_reg constants */
#define CC_REG_NORMALIZED C_00000001
#define CC_REG_BORROW C_00000002
#define CC_REG_MINUS C_00000004
#define CC_REG_ZERO C_00000008
#define CC_REG_SATURATE C_00000010
#define CC_REG_NONZERO C_00000100
+#define A_CC_REG_NORMALIZED A_C_00000001
+#define A_CC_REG_BORROW A_C_00000002
+#define A_CC_REG_MINUS A_C_00000004
+#define A_CC_REG_ZERO A_C_00000008
+#define A_CC_REG_SATURATE A_C_00000010
+#define A_CC_REG_NONZERO A_C_00000100
+
/* FX buses */
// These are arbitrary mappings; our DSP code simply expects
// the config files to route the channels this way.
@@ -203,54 +276,23 @@
#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
-/* Audigy constants */
-#define A_C_00000000 0xc0
-#define A_C_00000001 0xc1
-#define A_C_00000002 0xc2
-#define A_C_00000003 0xc3
-#define A_C_00000004 0xc4
-#define A_C_00000008 0xc5
-#define A_C_00000010 0xc6
-#define A_C_00000020 0xc7
-#define A_C_00000100 0xc8
-#define A_C_00010000 0xc9
-#define A_C_00000800 0xca
-#define A_C_10000000 0xcb
-#define A_C_20000000 0xcc
-#define A_C_40000000 0xcd
-#define A_C_80000000 0xce
-#define A_C_7fffffff 0xcf
-#define A_C_ffffffff 0xd0
-#define A_C_fffffffe 0xd1
-#define A_C_c0000000 0xd2
-#define A_C_4f1bbcdc 0xd3
-#define A_C_5a7ef9db 0xd4
-#define A_C_00100000 0xd5
-#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
-#define A_GPR_COND 0xd7 /* CCR, condition register */
-#define A_GPR_NOISE0 0xd8 /* noise source */
-#define A_GPR_NOISE1 0xd9 /* noise source */
-#define A_GPR_IRQ 0xda /* IRQ register */
-#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
-#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
-
-/* definitions for debug register */
+/* Definitions for debug register. Note that these are for emu10k1 ONLY. */
#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
#define EMU10K1_DBG_STEP 0x00004000 /* start single step */
#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
-/* tank memory address line */
-#ifndef __KERNEL__
-#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
-#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
-#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
-#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
-#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
-#endif
+/* Definitions for emu10k2 debug register. */
+#define A_DBG_ZC 0x40000000 /* zero tram counter */
+#define A_DBG_SATURATION_OCCURED 0x20000000
+#define A_DBG_SATURATION_ADDR 0x0ffc0000
+#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
+#define A_DBG_STEP 0x00010000
+#define A_DBG_CONDITION_CODE 0x0000f800
+#define A_DBG_STEP_ADDR 0x000003ff
struct snd_emu10k1_fx8010_info {
unsigned int internal_tram_size; /* in samples */
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
` (5 preceding siblings ...)
2023-04-22 16:10 ` [PATCH 6/7] ALSA: emu10k1: fixup DSP defines Oswald Buddenhagen
@ 2023-04-22 16:10 ` Oswald Buddenhagen
2023-04-22 18:52 ` kernel test robot
2023-04-23 7:26 ` Takashi Iwai
2023-04-23 7:27 ` [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Takashi Iwai
7 siblings, 2 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-22 16:10 UTC (permalink / raw)
To: alsa-devel; +Cc: Takashi Iwai
Using the *_MASK defines for "maximal value" is debatable. I got the
idea from FreeBSD, and it sorta makes sense to me.
Some hunks look a bit incomplete, because code that is going to be
subsequently removed is not touched here.
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
---
sound/pci/emu10k1/emu10k1_callback.c | 15 ++++-----
sound/pci/emu10k1/emu10k1_main.c | 46 ++++++++++++++--------------
sound/pci/emu10k1/emufx.c | 6 ++--
sound/pci/emu10k1/emumixer.c | 8 ++---
sound/pci/emu10k1/emupcm.c | 12 ++++----
sound/pci/emu10k1/io.c | 18 +++++------
sound/pci/emu10k1/p16v.c | 29 ++++++++++--------
7 files changed, 69 insertions(+), 65 deletions(-)
diff --git a/sound/pci/emu10k1/emu10k1_callback.c b/sound/pci/emu10k1/emu10k1_callback.c
index dba1e9fc2eec..44f2a61c6be8 100644
--- a/sound/pci/emu10k1/emu10k1_callback.c
+++ b/sound/pci/emu10k1/emu10k1_callback.c
@@ -120,9 +120,9 @@ release_voice(struct snd_emux_voice *vp)
struct snd_emu10k1 *hw;
hw = vp->hw;
- dcysusv = 0x8000 | (unsigned char)vp->reg.parm.modrelease;
+ dcysusv = (unsigned char)vp->reg.parm.modrelease | DCYSUSM_PHASE1_MASK;
snd_emu10k1_ptr_write(hw, DCYSUSM, vp->ch, dcysusv);
- dcysusv = 0x8000 | (unsigned char)vp->reg.parm.volrelease | DCYSUSV_CHANNELENABLE_MASK;
+ dcysusv = (unsigned char)vp->reg.parm.volrelease | DCYSUSV_PHASE1_MASK | DCYSUSV_CHANNELENABLE_MASK;
snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, dcysusv);
}
@@ -138,7 +138,8 @@ terminate_voice(struct snd_emux_voice *vp)
if (snd_BUG_ON(!vp))
return;
hw = vp->hw;
- snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch, 0x807f | DCYSUSV_CHANNELENABLE_MASK);
+ snd_emu10k1_ptr_write(hw, DCYSUSV, vp->ch,
+ DCYSUSV_PHASE1_MASK | DCYSUSV_DECAYTIME_MASK | DCYSUSV_CHANNELENABLE_MASK);
if (vp->block) {
struct snd_emu10k1_memblk *emem;
emem = (struct snd_emu10k1_memblk *)vp->block;
@@ -347,9 +348,9 @@ start_voice(struct snd_emux_voice *vp)
}
/* channel to be silent and idle */
- snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0x0000);
- snd_emu10k1_ptr_write(hw, VTFT, ch, 0x0000FFFF);
- snd_emu10k1_ptr_write(hw, CVCF, ch, 0x0000FFFF);
+ snd_emu10k1_ptr_write(hw, DCYSUSV, ch, 0);
+ snd_emu10k1_ptr_write(hw, VTFT, ch, VTFT_FILTERTARGET_MASK);
+ snd_emu10k1_ptr_write(hw, CVCF, ch, CVCF_CURRENTFILTER_MASK);
snd_emu10k1_ptr_write(hw, PTRX, ch, 0);
snd_emu10k1_ptr_write(hw, CPF, ch, 0);
@@ -453,7 +454,7 @@ start_voice(struct snd_emux_voice *vp)
/* reset volume */
temp = (unsigned int)vp->vtarget << 16;
snd_emu10k1_ptr_write(hw, VTFT, ch, temp | vp->ftarget);
- snd_emu10k1_ptr_write(hw, CVCF, ch, temp | 0xff00);
+ snd_emu10k1_ptr_write(hw, CVCF, ch, temp | CVCF_CURRENTFILTER_MASK);
return 0;
}
diff --git a/sound/pci/emu10k1/emu10k1_main.c b/sound/pci/emu10k1/emu10k1_main.c
index 007c445d72bf..e53eb7fd0883 100644
--- a/sound/pci/emu10k1/emu10k1_main.c
+++ b/sound/pci/emu10k1/emu10k1_main.c
@@ -59,8 +59,8 @@ void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
{
snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
snd_emu10k1_ptr_write(emu, IP, ch, 0);
- snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
- snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
+ snd_emu10k1_ptr_write(emu, VTFT, ch, VTFT_FILTERTARGET_MASK);
+ snd_emu10k1_ptr_write(emu, CVCF, ch, CVCF_CURRENTFILTER_MASK);
snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
snd_emu10k1_ptr_write(emu, CPF, ch, 0);
snd_emu10k1_ptr_write(emu, CCR, ch, 0);
@@ -74,7 +74,7 @@ void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
- snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
+ snd_emu10k1_ptr_write(emu, IFATN, ch, IFATN_FILTERCUTOFF_MASK | IFATN_ATTENUATION_MASK);
snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
@@ -90,10 +90,10 @@ void snd_emu10k1_voice_init(struct snd_emu10k1 *emu, int ch)
/* Audigy extra stuffs */
if (emu->audigy) {
- snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
- snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
- snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
- snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
+ snd_emu10k1_ptr_write(emu, A_CSBA, ch, 0);
+ snd_emu10k1_ptr_write(emu, A_CSDC, ch, 0);
+ snd_emu10k1_ptr_write(emu, A_CSFE, ch, 0);
+ snd_emu10k1_ptr_write(emu, A_CSHG, ch, 0);
snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
@@ -267,7 +267,7 @@ static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir)
snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
- snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
+ snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_256K); /* taken from original driver */
silent_page = (emu->silent_page.addr << emu->address_mode) | (emu->address_mode ? MAP_PTI_MASK1 : MAP_PTI_MASK0);
for (ch = 0; ch < NUM_G; ch++) {
@@ -826,7 +826,7 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
/* FPGA netlist already present so clear it */
/* Return to programming mode */
- snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02);
+ snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_HANA);
}
snd_emu1010_fpga_read(emu, EMU_HANA_ID, ®);
dev_dbg(emu->card->dev, "reg2 = 0x%x\n", reg);
@@ -866,36 +866,36 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
/* Optical -> ADAT I/O */
emu->emu1010.optical_in = 1; /* IN_ADAT */
emu->emu1010.optical_out = 1; /* OUT_ADAT */
- tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
- (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
+ tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) |
+ (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF);
snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
/* Set no attenuation on Audio Dock pads. */
- snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00);
emu->emu1010.adc_pads = 0x00;
+ snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, emu->emu1010.adc_pads);
/* Unmute Audio dock DACs, Headphone source DAC-4. */
- snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30);
+ snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, EMU_HANA_DOCK_PHONES_192_DAC4);
/* DAC PADs. */
- snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f);
- emu->emu1010.dac_pads = 0x0f;
+ emu->emu1010.dac_pads = EMU_HANA_DOCK_DAC_PAD1 | EMU_HANA_DOCK_DAC_PAD2 |
+ EMU_HANA_DOCK_DAC_PAD3 | EMU_HANA_DOCK_DAC_PAD4;
+ snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, emu->emu1010.dac_pads);
/* SPDIF Format. Set Consumer mode, 24bit, copy enable */
- snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10);
+ snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, EMU_HANA_SPDIF_MODE_RX_INVALID);
/* MIDI routing */
- snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19);
- /* Unknown. */
- snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c);
+ snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, EMU_HANA_MIDI_INA_FROM_HAMOA | EMU_HANA_MIDI_INB_FROM_DOCK2);
+ snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, EMU_HANA_MIDI_OUT_DOCK2 | EMU_HANA_MIDI_OUT_SYNC2);
/* IRQ Enable: All on */
- /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); */
+ /* snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x0f); */
/* IRQ Enable: All off */
snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00);
emu->emu1010.internal_clock = 1; /* 48000 */
/* Default WCLK set to 48kHz. */
- snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00);
+ snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, EMU_HANA_DEFCLOCK_48K);
/* Word Clock source, Internal 48kHz x1 */
snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K);
/* snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X); */
/* Audio Dock LEDs. */
- snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);
+ snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, EMU_HANA_DOCK_LEDS_2_LOCK | EMU_HANA_DOCK_LEDS_2_48K);
#if 0
/* For 96kHz */
@@ -1022,7 +1022,7 @@ static int snd_emu10k1_emu1010_init(struct snd_emu10k1 *emu)
EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
snd_emu1010_fpga_link_dst_src_write(emu,
EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
- snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01); /* Unmute all */
+ snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, EMU_UNMUTE);
#if 0
snd_emu1010_fpga_link_dst_src_write(emu,
diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c
index 510b776f856d..317c69b22cc2 100644
--- a/sound/pci/emu10k1/emufx.c
+++ b/sound/pci/emu10k1/emufx.c
@@ -1358,7 +1358,7 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
gpr += 2;
/* mic capture buffer */
- A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
+ A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R));
/* Audigy CD Playback Volume */
A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
@@ -1441,7 +1441,7 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
/* Stereo Mix Center Playback */
/* Center = sub = Left/2 + Right/2 */
- A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
+ A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1));
A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
gpr++;
@@ -2484,7 +2484,7 @@ int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
spin_unlock_irq(&emu->emu_lock);
snd_emu10k1_ptr_write(emu, TCB, 0, 0);
- snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
+ snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
if (emu->fx8010.etram_pages.area != NULL) {
snd_dma_free_pages(&emu->fx8010.etram_pages);
emu->fx8010.etram_pages.area = NULL;
diff --git a/sound/pci/emu10k1/emumixer.c b/sound/pci/emu10k1/emumixer.c
index 3d2ed5e0a59d..faa42ba5870a 100644
--- a/sound/pci/emu10k1/emumixer.c
+++ b/sound/pci/emu10k1/emumixer.c
@@ -827,8 +827,8 @@ static int snd_emu1010_optical_out_put(struct snd_kcontrol *kcontrol,
change = (emu->emu1010.optical_out != val);
if (change) {
emu->emu1010.optical_out = val;
- tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
- (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
+ tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) |
+ (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF);
snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
}
return change;
@@ -878,8 +878,8 @@ static int snd_emu1010_optical_in_put(struct snd_kcontrol *kcontrol,
change = (emu->emu1010.optical_in != val);
if (change) {
emu->emu1010.optical_in = val;
- tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : 0) |
- (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : 0);
+ tmp = (emu->emu1010.optical_in ? EMU_HANA_OPTICAL_IN_ADAT : EMU_HANA_OPTICAL_IN_SPDIF) |
+ (emu->emu1010.optical_out ? EMU_HANA_OPTICAL_OUT_ADAT : EMU_HANA_OPTICAL_OUT_SPDIF);
snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, tmp);
}
return change;
diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c
index b0c0ef342756..e8d2f0f6fbb3 100644
--- a/sound/pci/emu10k1/emupcm.c
+++ b/sound/pci/emu10k1/emupcm.c
@@ -352,8 +352,8 @@ static void snd_emu10k1_pcm_init_voice(struct snd_emu10k1 *emu,
snd_emu10k1_ptr_write(emu, MAPA, voice, silent_page);
snd_emu10k1_ptr_write(emu, MAPB, voice, silent_page);
/* modulation envelope */
- snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff);
- snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff);
+ snd_emu10k1_ptr_write(emu, VTFT, voice, VTFT_FILTERTARGET_MASK);
+ snd_emu10k1_ptr_write(emu, CVCF, voice, CVCF_CURRENTFILTER_MASK);
snd_emu10k1_ptr_write(emu, ATKHLDM, voice, 0);
snd_emu10k1_ptr_write(emu, DCYSUSM, voice, 0x007f);
snd_emu10k1_ptr_write(emu, LFOVAL1, voice, 0x8000);
@@ -621,8 +621,8 @@ static void snd_emu10k1_playback_prepare_voice(struct snd_emu10k1 *emu, struct s
tmp = runtime->channels == 2 ? (master ? 1 : 2) : 0;
vattn = mix != NULL ? (mix->attn[tmp] << 16) : 0;
snd_emu10k1_ptr_write(emu, IFATN, voice, attn);
- snd_emu10k1_ptr_write(emu, VTFT, voice, vattn | 0xffff);
- snd_emu10k1_ptr_write(emu, CVCF, voice, vattn | 0xffff);
+ snd_emu10k1_ptr_write(emu, VTFT, voice, vattn | VTFT_FILTERTARGET_MASK);
+ snd_emu10k1_ptr_write(emu, CVCF, voice, vattn | CVCF_CURRENTFILTER_MASK);
snd_emu10k1_ptr_write(emu, DCYSUSV, voice, 0x7f7f);
snd_emu10k1_voice_clear_loop_stop(emu, voice);
}
@@ -663,8 +663,8 @@ static void snd_emu10k1_playback_stop_voice(struct snd_emu10k1 *emu, struct snd_
snd_emu10k1_ptr_write(emu, PTRX_PITCHTARGET, voice, 0);
snd_emu10k1_ptr_write(emu, CPF_CURRENTPITCH, voice, 0);
snd_emu10k1_ptr_write(emu, IFATN, voice, 0xffff);
- snd_emu10k1_ptr_write(emu, VTFT, voice, 0xffff);
- snd_emu10k1_ptr_write(emu, CVCF, voice, 0xffff);
+ snd_emu10k1_ptr_write(emu, VTFT, voice, VTFT_FILTERTARGET_MASK);
+ snd_emu10k1_ptr_write(emu, CVCF, voice, CVCF_CURRENTFILTER_MASK);
snd_emu10k1_ptr_write(emu, IP, voice, 0);
}
diff --git a/sound/pci/emu10k1/io.c b/sound/pci/emu10k1/io.c
index c60573f14ea8..cfb96a67aa35 100644
--- a/sound/pci/emu10k1/io.c
+++ b/sound/pci/emu10k1/io.c
@@ -95,8 +95,8 @@ unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu,
regptr = (reg << 16) | chn;
spin_lock_irqsave(&emu->emu_lock, flags);
- outl(regptr, emu->port + 0x20 + PTR);
- val = inl(emu->port + 0x20 + DATA);
+ outl(regptr, emu->port + PTR2);
+ val = inl(emu->port + DATA2);
spin_unlock_irqrestore(&emu->emu_lock, flags);
return val;
}
@@ -112,8 +112,8 @@ void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu,
regptr = (reg << 16) | chn;
spin_lock_irqsave(&emu->emu_lock, flags);
- outl(regptr, emu->port + 0x20 + PTR);
- outl(data, emu->port + 0x20 + DATA);
+ outl(regptr, emu->port + PTR2);
+ outl(data, emu->port + DATA2);
spin_unlock_irqrestore(&emu->emu_lock, flags);
}
@@ -128,7 +128,7 @@ int snd_emu10k1_spi_write(struct snd_emu10k1 * emu,
/* This function is not re-entrant, so protect against it. */
spin_lock(&emu->spi_lock);
if (emu->card_capabilities->ca0108_chip)
- reg = 0x3c; /* PTR20, reg 0x3c */
+ reg = P17V_SPI;
else {
/* For other chip types the SPI register
* is currently unknown. */
@@ -280,10 +280,10 @@ void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 s
return;
if (snd_BUG_ON(src & ~0x71f))
return;
- snd_emu1010_fpga_write(emu, 0x00, dst >> 8);
- snd_emu1010_fpga_write(emu, 0x01, dst & 0x1f);
- snd_emu1010_fpga_write(emu, 0x02, src >> 8);
- snd_emu1010_fpga_write(emu, 0x03, src & 0x1f);
+ snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8);
+ snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f);
+ snd_emu1010_fpga_write(emu, EMU_HANA_SRCHI, src >> 8);
+ snd_emu1010_fpga_write(emu, EMU_HANA_SRCLO, src & 0x1f);
}
void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)
diff --git a/sound/pci/emu10k1/p16v.c b/sound/pci/emu10k1/p16v.c
index ce4d3450959c..e7f097cae574 100644
--- a/sound/pci/emu10k1/p16v.c
+++ b/sound/pci/emu10k1/p16v.c
@@ -254,19 +254,24 @@ static int snd_p16v_pcm_prepare_playback(struct snd_pcm_substream *substream)
emu->p16v_buffer->bytes);
#endif /* debug */
tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel);
+ tmp &= ~(A_SPDIF_RATE_MASK | A_EHC_SRC48_MASK);
switch (runtime->rate) {
case 44100:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x8080);
+ snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel,
+ tmp | A_SPDIF_44100 | A_EHC_SRC48_44);
break;
case 96000:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x4040);
+ snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel,
+ tmp | A_SPDIF_96000 | A_EHC_SRC48_96);
break;
case 192000:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x2020);
+ snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel,
+ tmp | A_SPDIF_192000 | A_EHC_SRC48_192);
break;
case 48000:
default:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0xe0e0) | 0x0000);
+ snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel,
+ tmp | A_SPDIF_48000 | A_EHC_SRC48_BYPASS);
break;
}
/* FIXME: Check emu->buffer.size before actually writing to it. */
@@ -282,46 +287,44 @@ static int snd_p16v_pcm_prepare_playback(struct snd_pcm_substream *substream)
//snd_emu10k1_ptr20_write(emu, PLAYBACK_PERIOD_SIZE, channel, frames_to_bytes(runtime, runtime->period_size)<<16); // buffer size in bytes
snd_emu10k1_ptr20_write(emu, PLAYBACK_PERIOD_SIZE, channel, 0); // buffer size in bytes
snd_emu10k1_ptr20_write(emu, PLAYBACK_POINTER, channel, 0);
- snd_emu10k1_ptr20_write(emu, 0x07, channel, 0x0);
- snd_emu10k1_ptr20_write(emu, 0x08, channel, 0);
+ snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_END_ADDRESS, channel, 0);
+ snd_emu10k1_ptr20_write(emu, PLAYBACK_FIFO_POINTER, channel, 0);
return 0;
}
/* prepare capture callback */
static int snd_p16v_pcm_prepare_capture(struct snd_pcm_substream *substream)
{
struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);
struct snd_pcm_runtime *runtime = substream->runtime;
int channel = substream->pcm->device - emu->p16v_device_offset;
- u32 tmp;
/*
dev_dbg(emu->card->dev, "prepare capture:channel_number=%d, rate=%d, "
"format=0x%x, channels=%d, buffer_size=%ld, period_size=%ld, "
"frames_to_bytes=%d\n",
channel, runtime->rate, runtime->format, runtime->channels,
runtime->buffer_size, runtime->period_size,
frames_to_bytes(runtime, 1));
*/
- tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, channel);
switch (runtime->rate) {
case 44100:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0800);
+ snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_44100);
break;
case 96000:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0400);
+ snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_96000);
break;
case 192000:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0200);
+ snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_192000);
break;
case 48000:
default:
- snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, channel, (tmp & ~0x0e00) | 0x0000);
+ snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_48000);
break;
}
/* FIXME: Check emu->buffer.size before actually writing to it. */
- snd_emu10k1_ptr20_write(emu, 0x13, channel, 0);
+ snd_emu10k1_ptr20_write(emu, CAPTURE_FIFO_POINTER, channel, 0);
snd_emu10k1_ptr20_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr);
snd_emu10k1_ptr20_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size) << 16); // buffer size in bytes
snd_emu10k1_ptr20_write(emu, CAPTURE_POINTER, channel, 0);
--
2.40.0.152.g15d061e6df
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers
2023-04-22 16:10 ` [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers Oswald Buddenhagen
@ 2023-04-22 18:52 ` kernel test robot
2023-04-23 7:26 ` Takashi Iwai
1 sibling, 0 replies; 12+ messages in thread
From: kernel test robot @ 2023-04-22 18:52 UTC (permalink / raw)
To: Oswald Buddenhagen, alsa-devel; +Cc: oe-kbuild-all, Takashi Iwai
Hi Oswald,
kernel test robot noticed the following build errors:
[auto build test ERROR on tiwai-sound/for-next]
[cannot apply to tiwai-sound/for-linus linus/master v6.3-rc7 next-20230421]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Oswald-Buddenhagen/ALSA-emu10k1-comment-updates/20230423-002113
base: https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git for-next
patch link: https://lore.kernel.org/r/20230422161021.1143903-8-oswald.buddenhagen%40gmx.de
patch subject: [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20230423/202304230230.Hzwubvl5-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-8) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/e9c8b11aa4d8ccd105aba0217ff72e87bad545bf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Oswald-Buddenhagen/ALSA-emu10k1-comment-updates/20230423-002113
git checkout e9c8b11aa4d8ccd105aba0217ff72e87bad545bf
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 olddefconfig
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202304230230.Hzwubvl5-lkp@intel.com/
All errors (new ones prefixed by >>):
sound/pci/emu10k1/p16v.c: In function 'snd_p16v_pcm_prepare_capture':
>> sound/pci/emu10k1/p16v.c:313:38: error: 'A_I2S_CAPTURE_RATE' undeclared (first use in this function); did you mean 'A_I2S_CAPTURE_RATE_MASK'?
313 | snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_44100);
| ^~~~~~~~~~~~~~~~~~
| A_I2S_CAPTURE_RATE_MASK
sound/pci/emu10k1/p16v.c:313:38: note: each undeclared identifier is reported only once for each function it appears in
vim +313 sound/pci/emu10k1/p16v.c
295
296 /* prepare capture callback */
297 static int snd_p16v_pcm_prepare_capture(struct snd_pcm_substream *substream)
298 {
299 struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream);
300 struct snd_pcm_runtime *runtime = substream->runtime;
301 int channel = substream->pcm->device - emu->p16v_device_offset;
302
303 /*
304 dev_dbg(emu->card->dev, "prepare capture:channel_number=%d, rate=%d, "
305 "format=0x%x, channels=%d, buffer_size=%ld, period_size=%ld, "
306 "frames_to_bytes=%d\n",
307 channel, runtime->rate, runtime->format, runtime->channels,
308 runtime->buffer_size, runtime->period_size,
309 frames_to_bytes(runtime, 1));
310 */
311 switch (runtime->rate) {
312 case 44100:
> 313 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_44100);
314 break;
315 case 96000:
316 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_96000);
317 break;
318 case 192000:
319 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_192000);
320 break;
321 case 48000:
322 default:
323 snd_emu10k1_ptr_write(emu, A_I2S_CAPTURE_RATE, channel, A_I2S_CAPTURE_48000);
324 break;
325 }
326 /* FIXME: Check emu->buffer.size before actually writing to it. */
327 snd_emu10k1_ptr20_write(emu, CAPTURE_FIFO_POINTER, channel, 0);
328 snd_emu10k1_ptr20_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr);
329 snd_emu10k1_ptr20_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size) << 16); // buffer size in bytes
330 snd_emu10k1_ptr20_write(emu, CAPTURE_POINTER, channel, 0);
331 //snd_emu10k1_ptr20_write(emu, CAPTURE_SOURCE, 0x0, 0x333300e4); /* Select MIC or Line in */
332 //snd_emu10k1_ptr20_write(emu, EXTENDED_INT_MASK, 0, snd_emu10k1_ptr20_read(emu, EXTENDED_INT_MASK, 0) | (0x110000<<channel));
333
334 return 0;
335 }
336
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers
2023-04-22 16:10 ` [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers Oswald Buddenhagen
2023-04-22 18:52 ` kernel test robot
@ 2023-04-23 7:26 ` Takashi Iwai
2023-04-24 13:51 ` Oswald Buddenhagen
1 sibling, 1 reply; 12+ messages in thread
From: Takashi Iwai @ 2023-04-23 7:26 UTC (permalink / raw)
To: Oswald Buddenhagen; +Cc: alsa-devel
On Sat, 22 Apr 2023 18:10:21 +0200,
Oswald Buddenhagen wrote:
>
> Using the *_MASK defines for "maximal value" is debatable. I got the
> idea from FreeBSD, and it sorta makes sense to me.
>
> Some hunks look a bit incomplete, because code that is going to be
> subsequently removed is not touched here.
>
> Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
This patch actually broke the build due to A_I2S_CAPTURE_RATE, as
0-day bot caught. Any missing patch?
thanks,
Takashi
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
` (6 preceding siblings ...)
2023-04-22 16:10 ` [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers Oswald Buddenhagen
@ 2023-04-23 7:27 ` Takashi Iwai
7 siblings, 0 replies; 12+ messages in thread
From: Takashi Iwai @ 2023-04-23 7:27 UTC (permalink / raw)
To: Oswald Buddenhagen; +Cc: alsa-devel
On Sat, 22 Apr 2023 18:10:14 +0200,
Oswald Buddenhagen wrote:
>
> Mostly adding, removing, and otherwise massaging numerous #defines and
> code using them, and surrounding comments.
>
> Oswald Buddenhagen (7):
> ALSA: emu10k1: comment updates
> ALSA: emu10k1: fix lineup of EMU_HANA_* defines
> ALSA: emu10k1: eliminate some unused defines
> ALSA: emu10k1: remove some bogus defines
> ALSA: emu10k1: pull in some register definitions from kX-project
> ALSA: emu10k1: fixup DSP defines
> ALSA: emu10k1: use more existing defines instead of open-coded numbers
Applied now partially from patches 1 to 6. The patch 7 was skipped
due to the compile error.
thanks,
Takashi
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers
2023-04-23 7:26 ` Takashi Iwai
@ 2023-04-24 13:51 ` Oswald Buddenhagen
0 siblings, 0 replies; 12+ messages in thread
From: Oswald Buddenhagen @ 2023-04-24 13:51 UTC (permalink / raw)
To: Takashi Iwai; +Cc: alsa-devel
On Sun, Apr 23, 2023 at 09:26:47AM +0200, Takashi Iwai wrote:
>This patch actually broke the build due to A_I2S_CAPTURE_RATE, as
>0-day bot caught. Any missing patch?
>
turns out it has a dependency on the "use high-level I/O functions also
during init" patch. you applied that one meanwhile, so it's now safe to
apply this one as well.
(i did a lot of re-ordering within the series and didn't re-test every
commit separately each time, so it slipped through. :})
regards
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-04-24 13:53 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-22 16:10 [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 1/7] ALSA: emu10k1: comment updates Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 2/7] ALSA: emu10k1: fix lineup of EMU_HANA_* defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 3/7] ALSA: emu10k1: eliminate some unused defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 4/7] ALSA: emu10k1: remove some bogus defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 5/7] ALSA: emu10k1: pull in some register definitions from kX-project Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 6/7] ALSA: emu10k1: fixup DSP defines Oswald Buddenhagen
2023-04-22 16:10 ` [PATCH 7/7] ALSA: emu10k1: use more existing defines instead of open-coded numbers Oswald Buddenhagen
2023-04-22 18:52 ` kernel test robot
2023-04-23 7:26 ` Takashi Iwai
2023-04-24 13:51 ` Oswald Buddenhagen
2023-04-23 7:27 ` [PATCH 0/7] ALSA: emu10k1: improvements mostly related to #defines Takashi Iwai
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