[PATCH 0/4] PSR-SU-RC DC support and some PSR-SU fixes

[PATCH 0/4] PSR-SU-RC DC support and some PSR-SU fixes

[sunpeng.li]

From: Leo Li <sunpeng.li@amd.com>

The first two patches here add PSR SU Rate Control support to DC. Support in
amdgpu_dm is still pending to enable this fully.

The last two patches are some fixes for PSR SU.

David Zhang (3):
  drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support
  drm/amd/display: Add PSR-SU-RC support in DC
  drm/amd/display: pass panel instance in dirty rect message

Robin Chen (1):
  drm/amd/display: refactor dirty rect dmub command decision

 drivers/gpu/drm/amd/display/dc/core/dc.c      | 19 ++++++++++++++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 ++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++-----
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
 .../amd/display/include/ddc_service_types.h   |  4 ++++
 9 files changed, 100 insertions(+), 7 deletions(-)

-- 
2.36.1

[PATCH 1/4] drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support

[sunpeng.li]

From: David Zhang <dingchen.zhang@amd.com>

[why & how]

Expose vendor specific DPCD registers for rate controlling the eDP sink
TCON's refresh rate during PSR active. When used in combination with
PSR-SU and Freesync, it is called PSR-SU Rate Contorol, or PSR-SU-RC for
short.

v2: Add all DPCD registers required

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/include/ddc_service_types.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
index 20a3d4e23f66..05096c644a60 100644
--- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h
@@ -41,6 +41,10 @@
 #define DP_DEVICE_ID_38EC11 0x38EC11
 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
 
+#define DP_SINK_PSR_ACTIVE_VTOTAL		0x373
+#define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE	0x375
+#define DP_SOURCE_PSR_ACTIVE_VTOTAL		0x376
+
 enum ddc_result {
 	DDC_RESULT_UNKNOWN = 0,
 	DDC_RESULT_SUCESSFULL,
-- 
2.36.1

[PATCH 2/4] drm/amd/display: Add PSR-SU-RC support in DC

[sunpeng.li]

From: David Zhang <dingchen.zhang@amd.com>

[Why]

PSR-SU Rate Control - or PSR-SU-RC - enables PSR-SU panels to work with
variable refresh rate to allow for more power savings. Lowering the
refresh rate can increase PSR residency by expanding the eDP main link
shut down duration. It can also lower panel power consumption.

There is a complication with With PSR, since the eDP main link can be
shut down. Therefore, the timing controller (TCON) on the eDP sink nees
to be able to scan out its remote buffer independant of the main link.
To allow the eDP source to specify the sink's refresh rate while the
link is off, vendor-specific DPCD registers are used. This allows the
eDP source to then "Rate Control" the panel during PSR active.

[How]

Add DC support to communicate with PSR-SU-RC supported eDP sinks. The
sink will need to know the desired VTotal during PSR active.

This change only adds support to DC, support in amdgpu_dm is still pending to
enable this fully.

Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 ++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
 drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 +++++++++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
 .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
 6 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 31ffb961e18b..3d6dcaa6a483 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1795,6 +1795,7 @@ static bool dc_link_construct_legacy(struct dc_link *link,
 	 */
 	program_hpd_filter(link);
 
+	link->psr_settings.psr_vtotal_control_support = false;
 	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
 	DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
@@ -3207,6 +3208,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
 	union dpcd_alpm_configuration alpm_configuration;
+	union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
 
@@ -3276,6 +3278,13 @@ bool dc_link_setup_psr(struct dc_link *link,
 			psr_config->su_y_granularity;
 		psr_context->line_time_in_us =
 			psr_config->line_time_in_us;
+
+		if (link->psr_settings.psr_vtotal_control_support) {
+			psr_context->rate_control_caps = psr_config->rate_control_caps;
+			vtotal_control.bits.ENABLE = true;
+			core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
+							&vtotal_control.raw, sizeof(vtotal_control.raw));
+		}
 	}
 
 	psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
@@ -3408,6 +3417,19 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 		*residency = 0;
 }
 
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	struct dc *dc = link->ctx->dc;
+	struct dmub_psr *psr = dc->res_pool->psr;
+
+	if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
+		return false;
+
+	psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
+
+	return true;
+}
+
 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
 {
 	return &link->link_status;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 0bec986a6de8..3ec189dd73da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -100,6 +100,7 @@ struct psr_settings {
 	bool psr_feature_enabled;		// PSR is supported by sink
 	bool psr_allow_active;			// PSR is currently active
 	enum dc_psr_version psr_version;		// Internal PSR version, determined based on DPCD
+	bool psr_vtotal_control_support;	// Vtotal control is supported by sink
 
 	/* These parameters are calculated in Driver,
 	 * based on display timing and Sink capabilities.
@@ -324,6 +325,8 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
 void dc_link_blank_all_dp_displays(struct dc *dc);
 
 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init);
+bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 26b62f50ac4e..fa735d5f730f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -684,6 +684,7 @@ struct psr_config {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 union dmcu_psr_level {
@@ -794,6 +795,7 @@ struct psr_context {
 	/* psr2 selective update y granularity capability */
 	uint8_t su_y_granularity;
 	unsigned int line_time_in_us;
+	uint8_t rate_control_caps;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 9ca0cbb0af9b..0df06740ec39 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -250,6 +250,27 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
 }
 
+/**
+ * Set PSR vtotal requirement for FreeSync PSR.
+ */
+static void dmub_psr_set_sink_vtotal_in_psr_active(struct dmub_psr *dmub,
+		uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
+{
+	union dmub_rb_cmd cmd;
+	struct dc_context *dc = dmub->ctx;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.psr_set_vtotal.header.type = DMUB_CMD__PSR;
+	cmd.psr_set_vtotal.header.sub_type = DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE;
+	cmd.psr_set_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_vtotal_data);
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_idle = psr_vtotal_idle;
+	cmd.psr_set_vtotal.psr_set_vtotal_data.psr_vtotal_su = psr_vtotal_su;
+
+	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 /*
  * Set PSR power optimization flags.
  */
@@ -358,6 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 
 	copy_settings_data->line_capture_indication = 0;
 	copy_settings_data->line_time_in_us = psr_context->line_time_in_us;
+	copy_settings_data->rate_control_caps = psr_context->rate_control_caps;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
 	copy_settings_data->cmd_version =  DMUB_CMD_PSR_CONTROL_VERSION_1;
@@ -435,6 +457,7 @@ static const struct dmub_psr_funcs psr_funcs = {
 	.psr_set_level			= dmub_psr_set_level,
 	.psr_force_static		= dmub_psr_force_static,
 	.psr_get_residency		= dmub_psr_get_residency,
+	.psr_set_sink_vtotal_in_psr_active	= dmub_psr_set_sink_vtotal_in_psr_active,
 	.psr_set_power_opt		= dmub_psr_set_power_opt,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index 01acc01cc191..74005b9d352a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -46,6 +46,8 @@ struct dmub_psr_funcs {
 	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
 	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
 	uint8_t panel_inst);
+	void (*psr_set_sink_vtotal_in_psr_active)(struct dmub_psr *dmub,
+	uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su);
 	void (*psr_set_power_opt)(struct dmub_psr *dmub, unsigned int power_opt, uint8_t panel_inst);
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 6e6bd007babc..ec572a9e4054 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -101,6 +101,14 @@ union dpcd_alpm_configuration {
 	unsigned char raw;
 };
 
+union dpcd_sink_active_vtotal_control_mode {
+	struct {
+		unsigned char ENABLE                    : 1;
+		unsigned char RESERVED                  : 7;
+	} bits;
+	unsigned char raw;
+};
+
 union psr_error_status {
 	struct {
 		unsigned char LINK_CRC_ERROR        :1;
-- 
2.36.1

[PATCH 3/4] drm/amd/display: pass panel instance in dirty rect message

[sunpeng.li]

From: David Zhang <dingchen.zhang@amd.com>

[why]
DMUB FW uses OTG instance to get eDP panel instance. But in case
of MPO multiple pipe indexes are passed to updated the same panel.
The other OTG instance passed would be ignored causing in DMUB not
acknowledging the messages.

[how]
Add panel instance to dirty rectangle data and cursor update data
structures and pass to DMUB.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d4173be11903..31d83297bcb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 	struct dc_context *dc_ctx = dc->ctx;
 	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
 	unsigned int i, j;
+	unsigned int panel_inst = 0;
 
 	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
 		return;
 
+	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+		return;
+
 	memset(&cmd, 0x0, sizeof(cmd));
 	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
 	cmd.update_dirty_rect.header.sub_type = 0;
@@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
+			update_dirty_rect->panel_inst = panel_inst;
 			update_dirty_rect->pipe_idx = j;
 			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
 			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
-- 
2.36.1

Re: [PATCH 3/4] drm/amd/display: pass panel instance in dirty rect message

[Harry Wentland]

On 2022-06-02 14:03, sunpeng.li@amd.com wrote:
> From: David Zhang <dingchen.zhang@amd.com>
> 
> [why]
> DMUB FW uses OTG instance to get eDP panel instance. But in case
> of MPO multiple pipe indexes are passed to updated the same panel.
> The other OTG instance passed would be ignored causing in DMUB not
> acknowledging the messages.
> 
> [how]
> Add panel instance to dirty rectangle data and cursor update data
> structures and pass to DMUB.
> 

I'm not entirely following why passing the panel_inst solves the problem
that is described.

> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>

This says the author is David but it has only Mikita's sign-off.
We need David's sign-off as well.

Harry

> Acked-by: Leo Li <sunpeng.li@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d4173be11903..31d83297bcb5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>  	struct dc_context *dc_ctx = dc->ctx;
>  	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
>  	unsigned int i, j;
> +	unsigned int panel_inst = 0;
>  
>  	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
>  		return;
>  
> +	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
> +		return;
> +
>  	memset(&cmd, 0x0, sizeof(cmd));
>  	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
>  	cmd.update_dirty_rect.header.sub_type = 0;
> @@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>  			if (pipe_ctx->plane_state != plane_state)
>  				continue;
>  
> +			update_dirty_rect->panel_inst = panel_inst;
>  			update_dirty_rect->pipe_idx = j;
>  			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
>  			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);

Re: [PATCH 3/4] drm/amd/display: pass panel instance in dirty rect message

[Leo]

On 2022-06-02 16:48, Harry Wentland wrote:
> 
> 
> On 2022-06-02 14:03, sunpeng.li@amd.com wrote:
>> From: David Zhang <dingchen.zhang@amd.com>
>>
>> [why]
>> DMUB FW uses OTG instance to get eDP panel instance. But in case
>> of MPO multiple pipe indexes are passed to updated the same panel.
>> The other OTG instance passed would be ignored causing in DMUB not
>> acknowledging the messages.
>>
>> [how]
>> Add panel instance to dirty rectangle data and cursor update data
>> structures and pass to DMUB.
>>
> 
> I'm not entirely following why passing the panel_inst solves the problem
> that is described.

Oops, it looks like the commit message is misleading.

"panel_inst" already exists in the dmub_cmd structures. It defaults to 0 today due to the memset, which works with single eDP scenarios.
What this change is really doing is identifying the panel instance to run PSR commands on, instead of assuming that the eDP we want is always instance 0.

Will reword the message.

Thanks,
Leo

> 
>> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> 
> This says the author is David but it has only Mikita's sign-off.
> We need David's sign-off as well.
> 
> Harry
> 
>> Acked-by: Leo Li <sunpeng.li@amd.com>
>> ---
>>  drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> index d4173be11903..31d83297bcb5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
>> @@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>>  	struct dc_context *dc_ctx = dc->ctx;
>>  	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
>>  	unsigned int i, j;
>> +	unsigned int panel_inst = 0;
>>  
>>  	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
>>  		return;
>>  
>> +	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
>> +		return;
>> +
>>  	memset(&cmd, 0x0, sizeof(cmd));
>>  	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
>>  	cmd.update_dirty_rect.header.sub_type = 0;
>> @@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>>  			if (pipe_ctx->plane_state != plane_state)
>>  				continue;
>>  
>> +			update_dirty_rect->panel_inst = panel_inst;
>>  			update_dirty_rect->pipe_idx = j;
>>  			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
>>  			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
> 

[PATCH v2 3/4] drm/amd/display: pass panel instance in DMUB dirty rect command

[sunpeng.li]

From: David Zhang <dingchen.zhang@amd.com>

[Why]

In cases where there are multiple eDP instances, DMUB needs to know
which instance the command is for. Today, the field for specifying the
panel_inst exists in both dmub_cmd_update_dirty_rect_data and
dmub_cmd_update_cursor_info_data.

For cursor updates, we already specify the panel_inst, but that's not
the case for dirty_rect updates. Today, a value of '0' is used (due
to initial memsetting of the cmd struct to 0)

[how]

In dc_dmub_update_dirty_rect(), Call dc_get_edp_link_panel_inst() to get
the panel_inst, and fill it in the DMUB cmd struct.

v2: Update commit message for clarity.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d4173be11903..31d83297bcb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 	struct dc_context *dc_ctx = dc->ctx;
 	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
 	unsigned int i, j;
+	unsigned int panel_inst = 0;
 
 	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
 		return;
 
+	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+		return;
+
 	memset(&cmd, 0x0, sizeof(cmd));
 	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
 	cmd.update_dirty_rect.header.sub_type = 0;
@@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
+			update_dirty_rect->panel_inst = panel_inst;
 			update_dirty_rect->pipe_idx = j;
 			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
 			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);
-- 
2.36.1

Re: [PATCH v2 3/4] drm/amd/display: pass panel instance in DMUB dirty rect command

[Harry Wentland]

On 2022-06-03 12:32, sunpeng.li@amd.com wrote:
> From: David Zhang <dingchen.zhang@amd.com>
> 
> [Why]
> 
> In cases where there are multiple eDP instances, DMUB needs to know
> which instance the command is for. Today, the field for specifying the
> panel_inst exists in both dmub_cmd_update_dirty_rect_data and
> dmub_cmd_update_cursor_info_data.
> 
> For cursor updates, we already specify the panel_inst, but that's not
> the case for dirty_rect updates. Today, a value of '0' is used (due
> to initial memsetting of the cmd struct to 0)
> 
> [how]
> 
> In dc_dmub_update_dirty_rect(), Call dc_get_edp_link_panel_inst() to get
> the panel_inst, and fill it in the DMUB cmd struct.
> 
> v2: Update commit message for clarity.
> 
> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
> Signed-off-by: David Zhang <dingchen.zhang@amd.com>
> Acked-by: Leo Li <sunpeng.li@amd.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d4173be11903..31d83297bcb5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -2837,10 +2837,14 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>  	struct dc_context *dc_ctx = dc->ctx;
>  	struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
>  	unsigned int i, j;
> +	unsigned int panel_inst = 0;
>  
>  	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
>  		return;
>  
> +	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
> +		return;
> +
>  	memset(&cmd, 0x0, sizeof(cmd));
>  	cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
>  	cmd.update_dirty_rect.header.sub_type = 0;
> @@ -2869,6 +2873,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
>  			if (pipe_ctx->plane_state != plane_state)
>  				continue;
>  
> +			update_dirty_rect->panel_inst = panel_inst;
>  			update_dirty_rect->pipe_idx = j;
>  			dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd);
>  			dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv);

[PATCH 4/4] drm/amd/display: refactor dirty rect dmub command decision

[sunpeng.li]

From: Robin Chen <po-tchen@amd.com>

[Why]
To wrap the decision logic of sending dirty rect dmub command
for both frame update and cursor update path.

Signed-off-by: Robin Chen <po-tchen@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 14 ++++++++++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++-----
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 31d83297bcb5..645ec5bc3a7d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2827,6 +2827,18 @@ static void commit_planes_do_stream_update(struct dc *dc,
 	}
 }
 
+static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
+{
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    dc->debug.enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
 void dc_dmub_update_dirty_rect(struct dc *dc,
 			       int surface_count,
 			       struct dc_stream_state *stream,
@@ -2839,7 +2851,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 	unsigned int i, j;
 	unsigned int panel_inst = 0;
 
-	if (stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+	if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
 		return;
 
 	if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7fe06a2c0c04..5b5e0dd13fd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -3325,6 +3325,23 @@ static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx)
 	return false;
 }
 
+static bool dcn10_dmub_should_update_cursor_data(
+		struct pipe_ctx *pipe_ctx,
+		struct dc_debug_options *debug)
+{
+	if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+		return false;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		return true;
+
+	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1 &&
+	    debug->enable_sw_cntl_psr)
+		return true;
+
+	return false;
+}
+
 static void dcn10_dmub_update_cursor_data(
 		struct pipe_ctx *pipe_ctx,
 		struct hubp *hubp,
@@ -3346,13 +3363,8 @@ static void dcn10_dmub_update_cursor_data(
 
 	struct dc_debug_options *debug = &hubp->ctx->dc->debug;
 
-	if (!debug->enable_sw_cntl_psr && pipe_ctx->stream->link->psr_settings.psr_version != DC_PSR_VERSION_SU_1)
+	if (!dcn10_dmub_should_update_cursor_data(pipe_ctx, debug))
 		return;
-
-	if (pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED ||
-		pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
-		return;
-
 	/**
 	 * if cur_pos == NULL means the caller is from cursor_set_attribute
 	 * then driver use previous cursor position data
-- 
2.36.1

Re: [PATCH 0/4] PSR-SU-RC DC support and some PSR-SU fixes

[Harry Wentland]

Patches 1, 2, and 4 are
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

On 2022-06-02 14:03, sunpeng.li@amd.com wrote:
> From: Leo Li <sunpeng.li@amd.com>
> 
> The first two patches here add PSR SU Rate Control support to DC. Support in
> amdgpu_dm is still pending to enable this fully.
> 
> The last two patches are some fixes for PSR SU.
> 
> David Zhang (3):
>   drm/amd/display: expose AMD specific DPCD for PSR-SU-RC support
>   drm/amd/display: Add PSR-SU-RC support in DC
>   drm/amd/display: pass panel instance in dirty rect message
> 
> Robin Chen (1):
>   drm/amd/display: refactor dirty rect dmub command decision
> 
>  drivers/gpu/drm/amd/display/dc/core/dc.c      | 19 ++++++++++++++-
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 22 +++++++++++++++++
>  drivers/gpu/drm/amd/display/dc/dc_link.h      |  3 +++
>  drivers/gpu/drm/amd/display/dc/dc_types.h     |  2 ++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 23 ++++++++++++++++++
>  drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h |  2 ++
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 24 ++++++++++++++-----
>  .../drm/amd/display/dc/inc/hw/link_encoder.h  |  8 +++++++
>  .../amd/display/include/ddc_service_types.h   |  4 ++++
>  9 files changed, 100 insertions(+), 7 deletions(-)
>