From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: "Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Timur Kristóf" <timur.kristof@gmail.com>
Cc: amd-gfx@lists.freedesktop.org, kernel-dev@igalia.com
Subject: Re: [PATCH v3 3/5] Documentation/gpu: Expand generic block information
Date: Tue, 21 Oct 2025 10:54:27 +0530 [thread overview]
Message-ID: <079a7404-2310-4cff-b3f9-674222dd3603@amd.com> (raw)
In-Reply-To: <20251020194631.102260-4-siqueira@igalia.com>
On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> This commit expands the overall explanation about AMD GPU IPs by adding
> more details about their interconnection. Note that this commit includes
> a diagram that provides additional information.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> .../gpu/amdgpu/amd_overview_block.svg | 674 ++++++++++++++++++
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 3 +
> Documentation/gpu/amdgpu/driver-core.rst | 25 +
> 3 files changed, 702 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
>
> diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
> new file mode 100644
> index 000000000000..8d9ae95bd9a5
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
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> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index eb72e6f6d4f1..a3f9565d655b 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
> TOC
> Table of Contents
>
> + UMC
> + Unified Memory Controller
> +
> UMSCH
> User Mode Scheduler
>
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 3ce276272171..13f13e2e5497 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -77,6 +77,31 @@ VCN (Video Core Next)
> decode. It's exposed to userspace for user mode drivers (VA-API,
> OpenMAX, etc.)
>
> +It is important to note that these blocks can interact with each other. The
> +picture below illustrates some of the components and their interconnection:
> +
> +.. kernel-figure:: amd_overview_block.svg
> +
> +In the diagram, memory-related blocks are represented by a green color. Notice
> +that specific IPs have a green block that represents a small hardware block
> +named 'hub', which is responsible for interfacing with memory (pre-vega devices
> +have a dedicated block for that, named GMC). In the driver code, you can
GMC is replaced by UMC and it's not a hub.
> +identify this component by looking for the suffix hub, for example: gfxhub,
> +dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
> +turn is connected to memory blocks.
> +
> +There is some level of protection for certain elements in memory, and the PSP
> +plays an essential role in this area. For example, when a specific firmware is
> +loaded into the memory, PSP takes an action to ensure that the firmware has a
> +valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
> +encrypted memory via TMZ.
> +
Overall, you may summarize as PSP takes care of security features -
authenticating firmware, hardware access protection, content protection etc.
> +Another IP that deserves attention is the SMU, as it is connected to all the
> +other IPs. SMU will help put the GPU in optimal utilization by taking into
> +account performance and power consumption. SMU helps other blocks to set up a
> +proper clock configuration. Another feature of SMU is the support for resetting
> +every component.
SMU has a broader meaning. What is referred to as SMU in driver stands
for power management controller which is responsible for resets, power
and thermal management.
Thanks,
Lijo
> +
> .. _pipes-and-queues-description:
>
> GFX, Compute, and SDMA Overall Behavior
next prev parent reply other threads:[~2025-10-21 5:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 19:38 [PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-10-20 19:38 ` [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-10-20 20:30 ` Alex Deucher
2025-10-21 9:23 ` Timur Kristóf
2025-10-21 13:11 ` Rodrigo Siqueira
2025-10-28 13:01 ` Christian König
2025-10-20 19:38 ` [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
2025-10-20 20:17 ` Alex Deucher
2025-10-21 5:16 ` Lazar, Lijo
2025-10-21 13:25 ` Rodrigo Siqueira
2025-10-21 14:46 ` Alex Deucher
2025-10-28 13:10 ` Christian König
2025-10-28 14:36 ` Rodrigo Siqueira
2025-10-20 19:38 ` [PATCH v3 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
2025-10-20 20:28 ` Alex Deucher
2025-10-21 9:30 ` Timur Kristóf
2025-10-21 14:55 ` Rodrigo Siqueira
2025-10-21 21:34 ` Alex Deucher
2025-10-21 5:24 ` Lazar, Lijo [this message]
2025-10-20 19:38 ` [PATCH v3 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-10-20 20:30 ` Alex Deucher
2025-10-20 19:38 ` [PATCH v3 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
2025-10-20 20:53 ` Alex Deucher
2025-10-21 12:52 ` [PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers Alex Deucher
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