From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: "Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Timur Kristóf" <timur.kristof@gmail.com>
Cc: amd-gfx@lists.freedesktop.org, kernel-dev@igalia.com
Subject: Re: [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR
Date: Tue, 21 Oct 2025 10:46:20 +0530 [thread overview]
Message-ID: <26d69e19-a6dc-4506-b19a-7803323b5178@amd.com> (raw)
In-Reply-To: <20251020194631.102260-3-siqueira@igalia.com>
On 10/21/2025 1:08 AM, Rodrigo Siqueira wrote:
> When using UMR, a dashboard is available that displays the CPC, CPF,
> CPG, TCP, and UTCL utilization. This commit introduces the meanings of
> those acronyms (and others) to the glossary to improve the comprehension
> of the UMR dashboard.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..eb72e6f6d4f1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
> CP
> Command Processor
>
> + CPC
> + Command Processor Compute
> +
> + CPF
> + Command Processor Fetch
> +
> + CPG
> + Command Processor Graphics
> +
> CPLIB
> Content Protection Library
>
> @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
> GMC
> Graphic Memory Controller
>
> + GPR
> + General Purpose Register
> +
> GPUVM
> GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
> virtual address spaces that can be in flight at any given time. These
> @@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
> table for use by the kernel driver or into per process GPUVM page tables
> for application usage.
>
> + GWS
> + Global Wave Syncs
Sync (s is not there).
> +
> IH
> Interrupt Handler
>
> @@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
> TC
> Texture Cache
>
> + TCP (AMDGPU)
> + Texture Cache Processing
Texture Cache per Pipe - terminology used for L1 cache in old architecture.
> +
> TOC
> Table of Contents
>
> UMSCH
> User Mode Scheduler
>
> + UTCL
> + Universal Texture Cache Line
Unified Translation Cache - equivalent of TLB. Has multiple levels,
hence L may be dropped.
Thanks,
Lijo
> +
> UVD
> Unified Video Decoder
>
next prev parent reply other threads:[~2025-10-21 5:16 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 19:38 [PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-10-20 19:38 ` [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-10-20 20:30 ` Alex Deucher
2025-10-21 9:23 ` Timur Kristóf
2025-10-21 13:11 ` Rodrigo Siqueira
2025-10-28 13:01 ` Christian König
2025-10-20 19:38 ` [PATCH v3 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
2025-10-20 20:17 ` Alex Deucher
2025-10-21 5:16 ` Lazar, Lijo [this message]
2025-10-21 13:25 ` Rodrigo Siqueira
2025-10-21 14:46 ` Alex Deucher
2025-10-28 13:10 ` Christian König
2025-10-28 14:36 ` Rodrigo Siqueira
2025-10-20 19:38 ` [PATCH v3 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
2025-10-20 20:28 ` Alex Deucher
2025-10-21 9:30 ` Timur Kristóf
2025-10-21 14:55 ` Rodrigo Siqueira
2025-10-21 21:34 ` Alex Deucher
2025-10-21 5:24 ` Lazar, Lijo
2025-10-20 19:38 ` [PATCH v3 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-10-20 20:30 ` Alex Deucher
2025-10-20 19:38 ` [PATCH v3 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
2025-10-20 20:53 ` Alex Deucher
2025-10-21 12:52 ` [PATCH v3 0/5] Expand kernel-doc with more generic details and info about ring buffers Alex Deucher
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