[PATCH v2 0/7] Add sysfs to support OverDrive feature

[PATCH v2 0/7] Add sysfs to support OverDrive feature

[Rex Zhu]

v2: - Add patch 0003 to check whether vbios can support OD
    - Add patch 0004 to disable OD feature on CI/Iceland temporary
    - Check clk against OverDrive limits from VBIOS
    - Check voltage between level0 - 2000mV
    - Set OD flag when user commit the setting
    - Print the right clk/voltage range when user's setting out of range
    - refine OD flag's update when set power state

OD feature is disabled by default.
can be enabled by module parameter
ppfeaturemask=0x7fff
(ppfeaturemask default value is 0x3fff)

Add new sysfs pp_od_clk_voltage.

cat pp_od_clk_voltage output as
OD_SCLK: 
0:        300Mhz        800 mV
1:        466Mhz        818 mV
2:        751Mhz        824 mV
3:       1019Mhz        987 mV
4:       1074Mhz       1037 mV
5:       1126Mhz       1087 mV
6:       1169Mhz       1137 mV
7:       1206Mhz       1150 mV
OD_MCLK: 
0:        300Mhz        800 mV
1:       1650Mhz       1000 mV

user can change clock/voltage by 

echo "s/m level clock voltage">pp_od_clk_voltage to change the sclk/mclk clock/voltage value in od dpm table.
and
echo "c" to commit the user's setting

when need to reset to default dpm table,

echo "r" to restore the od dpm table
echo "c" to commit the setting.

the clock's range is level0-level7*1.2
the voltage range is level0-level7*1.2

Rex Zhu (7):
  drm/amd/pp: Add hwmgr interface for edit dpm table
  drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
  drm/amd/pp: Disable OD feature if VBIOS limits
  drm/amd/pp: Disable OD feature on CI/Iceland.
  drm/amd/pp: Implement edit_dpm_table on smu7
  drm/amd/pp: Update smu7 dpm table with OD clock/voltage
  drm/amd/pp: Add update_avfs call when set_power_state

 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h            |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c             |  98 +++++-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |   8 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  19 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |   2 +
 .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |   8 +-
 .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  |  11 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 366 ++++++++++++++-------
 .../amd/powerplay/hwmgr/vega10_processpptables.c   |   8 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   3 +
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  18 +-
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  18 +-
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    |  18 +-
 13 files changed, 434 insertions(+), 147 deletions(-)

-- 
1.9.1

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[PATCH v2 1/7] drm/amd/pp: Add hwmgr interface for edit dpm table

[Rex Zhu]

Add odn_edit_dpm_table function
points for setting user assigned clock/voltage.

Change-Id: I29d336123d1a78384b74b54d34f34f1e60dc5f51
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 7 +++++++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h      | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 103837c..e35dcd0 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -161,6 +161,13 @@ enum {
 	PP_GROUP_MAX
 };
 
+enum PP_OD_DPM_TABLE_COMMAND {
+	PP_OD_EDIT_SCLK_VDDC_TABLE,
+	PP_OD_EDIT_MCLK_VDDC_TABLE,
+	PP_OD_RESTORE_DEFAULT_TABLE,
+	PP_OD_COMMIT_DPM_TABLE
+};
+
 struct pp_states_info {
 	uint32_t nums;
 	uint32_t states[16];
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7caab09..604a7cb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -345,6 +345,9 @@ struct pp_hwmgr_func {
 					struct PP_TemperatureRange *range);
 	int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
 	int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
+	int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
+					enum PP_OD_DPM_TABLE_COMMAND type,
+					long *input, uint32_t size);
 };
 
 struct pp_table_func {
-- 
1.9.1

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[PATCH v2 2/7] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs

[Rex Zhu]

when cat pp_od_clk_voltage it show
OD_SCLK:
0:        300Mhz        800 mV
1:        466Mhz        818 mV
2:        751Mhz        824 mV
3:       1019Mhz        987 mV
4:       1074Mhz       1037 mV
5:       1126Mhz       1087 mV
6:       1169Mhz       1137 mV
7:       1206Mhz       1150 mV
OD_MCLK:
0:        300Mhz        800 mV
1:       1650Mhz       1000 mV

echo "s/m level clock voltage" to change
sclk/mclk's  clock and voltage

echo "r" to restore default value.
echo "c" to commit the user setting.

Change-Id: I4b45c09ff376caa53c1bf8333cf63f35b2839016
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h        |  4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         | 98 +++++++++++++++++++++++++-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 19 +++++
 4 files changed, 121 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 986f1d5..4b5755e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
 		((adev)->powerplay.pp_funcs->set_power_profile_mode(\
 			(adev)->powerplay.pp_handle, parameter, size))
 
+#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
+		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+			(adev)->powerplay.pp_handle, type, parameter, size))
+
 struct amdgpu_dpm {
 	struct amdgpu_ps        *ps;
 	/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ed9012a..fda858e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -360,6 +360,90 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
 	return count;
 }
 
+static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
+		struct device_attribute *attr,
+		const char *buf,
+		size_t count)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = ddev->dev_private;
+	int ret;
+	uint32_t parameter_size = 0;
+	long parameter[64];
+	char buf_cpy[128];
+	char *tmp_str;
+	char *sub_str;
+	const char delimiter[3] = {' ', '\n', '\0'};
+	uint32_t type;
+
+	if (count > 127)
+		return -EINVAL;
+
+	if (*buf == 's')
+		type = PP_OD_EDIT_SCLK_VDDC_TABLE;
+	else if (*buf == 'm')
+		type = PP_OD_EDIT_MCLK_VDDC_TABLE;
+	else if(*buf == 'r')
+		type = PP_OD_RESTORE_DEFAULT_TABLE;
+	else if (*buf == 'c')
+		type = PP_OD_COMMIT_DPM_TABLE;
+	else
+		return -EINVAL;
+
+	memcpy(buf_cpy, buf, count+1);
+
+	tmp_str = buf_cpy;
+
+	while (isspace(*++tmp_str));
+
+	while (tmp_str[0]) {
+		sub_str = strsep(&tmp_str, delimiter);
+		ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
+		if (ret)
+			return -EINVAL;
+		parameter_size++;
+
+		while (isspace(*tmp_str))
+			tmp_str++;
+	}
+
+	if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
+		ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+						parameter, parameter_size);
+
+	if (ret)
+		return -EINVAL;
+
+	if (type == PP_OD_COMMIT_DPM_TABLE) {
+		if (adev->powerplay.pp_funcs->dispatch_tasks) {
+			amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+			return count;
+		} else {
+			return -EINVAL;
+		}
+	}
+
+	return count;
+}
+
+static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+		struct device_attribute *attr,
+		char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = ddev->dev_private;
+	uint32_t size = 0;
+
+	if (adev->powerplay.pp_funcs->print_clock_levels) {
+		size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
+		size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
+		return size;
+	} else {
+		return snprintf(buf, PAGE_SIZE, "\n");
+	}
+
+}
+
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 		struct device_attribute *attr,
 		char *buf)
@@ -842,6 +926,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 		amdgpu_get_pp_power_profile_mode,
 		amdgpu_set_pp_power_profile_mode);
+static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
+		amdgpu_get_pp_od_clk_voltage,
+		amdgpu_set_pp_od_clk_voltage);
+
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 				      struct device_attribute *attr,
 				      char *buf)
@@ -1481,7 +1569,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 				"pp_power_profile_mode\n");
 		return ret;
 	}
-
+	ret = device_create_file(adev->dev,
+			&dev_attr_pp_od_clk_voltage);
+	if (ret) {
+		DRM_ERROR("failed to create device file	"
+				"pp_od_clk_voltage\n");
+		return ret;
+	}
 	ret = amdgpu_debugfs_pm_init(adev);
 	if (ret) {
 		DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1519,6 +1613,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 			&dev_attr_pp_compute_power_profile);
 	device_remove_file(adev->dev,
 			&dev_attr_pp_power_profile_mode);
+	device_remove_file(adev->dev,
+			&dev_attr_pp_od_clk_voltage);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index e35dcd0..b9aa9f4 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -310,6 +310,7 @@ struct amd_pm_funcs {
 		struct amd_pp_simple_clock_info *clocks);
 	int (*get_power_profile_mode)(void *handle, char *buf);
 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d9cb424..854c43c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
 	return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
 }
 
+static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
+{
+	struct pp_hwmgr *hwmgr;
+	struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+	if (pp_check(pp_handle))
+		return -EINVAL;
+
+	hwmgr = pp_handle->hwmgr;
+
+	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
+		pr_info("%s was not implemented.\n", __func__);
+		return -EINVAL;
+	}
+
+	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
+}
+
 static int pp_dpm_set_power_profile_state(void *handle,
 		struct amd_pp_profile *request)
 {
@@ -1507,6 +1525,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
 	.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
 	.get_power_profile_mode = pp_get_power_profile_mode,
 	.set_power_profile_mode = pp_set_power_profile_mode,
+	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
 /* export to DC */
 	.get_sclk = pp_dpm_get_sclk,
 	.get_mclk = pp_dpm_get_mclk,
-- 
1.9.1

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[PATCH v2 3/7] drm/amd/pp: Disable OD feature if VBIOS limits

[Rex Zhu]

Change-Id: Iea7d6ffe3d0139fa4780256e3975f966e2dc4d72
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c  |  8 ++++----
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c        | 11 +++++------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c |  8 ++++----
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index b49d65c..624c220 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -836,10 +836,10 @@ static int init_over_drive_limits(
 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
 
-	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
-		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
-		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_ACOverdriveSupport);
+	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 \
+		|| hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+		hwmgr->od_enabled = false;
+		pr_info("OverDrive feature not support by VBIOS\n");
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index c3e7e34..b1d4a10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -1074,12 +1074,11 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
 				powerplay_table,
 				(const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
 
-	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
-		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0
-		&& !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_OverdriveDisabledByPowerBudget))
-		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-				PHM_PlatformCaps_ACOverdriveSupport);
+	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0
+		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+		hwmgr->od_enabled = false;
+		pr_info("OverDrive feature not support by VBIOS\n");
+	}
 
 	return result;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index f14c761..8dc1aed 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -267,10 +267,10 @@ static int init_over_drive_limits(
 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
 
-	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 &&
-		hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
-		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-			PHM_PlatformCaps_ACOverdriveSupport);
+	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 ||
+		hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
+		hwmgr->od_enabled = false;
+		pr_info("OverDrive feature not support by VBIOS\n");
 	}
 
 	return 0;
-- 
1.9.1

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Re: [PATCH v2 3/7] drm/amd/pp: Disable OD feature if VBIOS limits

[Alex Deucher]

On Fri, Jan 19, 2018 at 3:10 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Iea7d6ffe3d0139fa4780256e3975f966e2dc4d72
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please add a commit message.  Something like:

drm/amd/pp: Disable OD feature if VBIOS limits

Check the vbios to determine whether we can enable OD.

You may want to make the messages pr_debug.  I could go either way on
that. With the commit message added:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c  |  8 ++++----
>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c        | 11 +++++------
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c |  8 ++++----
>  3 files changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> index b49d65c..624c220 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> @@ -836,10 +836,10 @@ static int init_over_drive_limits(
>         hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
>         hwmgr->platform_descriptor.overdriveVDDCStep = 0;
>
> -       if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 \
> -               && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
> -               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -                       PHM_PlatformCaps_ACOverdriveSupport);
> +       if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 \
> +               || hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
> +               hwmgr->od_enabled = false;
> +               pr_info("OverDrive feature not support by VBIOS\n");
>         }
>
>         return 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index c3e7e34..b1d4a10 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -1074,12 +1074,11 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
>                                 powerplay_table,
>                                 (const ATOM_FIRMWARE_INFO_V2_1 *)fw_info);
>
> -       if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
> -               && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0
> -               && !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> -                       PHM_PlatformCaps_OverdriveDisabledByPowerBudget))
> -               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -                               PHM_PlatformCaps_ACOverdriveSupport);
> +       if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0
> +               && hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
> +               hwmgr->od_enabled = false;
> +               pr_info("OverDrive feature not support by VBIOS\n");
> +       }
>
>         return result;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> index f14c761..8dc1aed 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> @@ -267,10 +267,10 @@ static int init_over_drive_limits(
>         hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
>         hwmgr->platform_descriptor.overdriveVDDCStep = 0;
>
> -       if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 &&
> -               hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) {
> -               phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> -                       PHM_PlatformCaps_ACOverdriveSupport);
> +       if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 ||
> +               hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
> +               hwmgr->od_enabled = false;
> +               pr_info("OverDrive feature not support by VBIOS\n");
>         }
>
>         return 0;
> --
> 1.9.1
>
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[PATCH v2 4/7] drm/amd/pp: Disable OD feature on CI/Iceland.

[Rex Zhu]

Change-Id: I9bb42d70b6a6b31c0eecc3ee2faf487982957356
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 2690446..c5411fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -167,6 +167,7 @@ int hwmgr_early_init(struct pp_instance *handle)
 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
 					PP_ENABLE_GFX_CG_THRU_SMU);
 		hwmgr->pp_table_version = PP_TABLE_V0;
+		hwmgr->od_enabled = false;
 		smu7_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_CZ:
@@ -181,6 +182,7 @@ int hwmgr_early_init(struct pp_instance *handle)
 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
 						PP_ENABLE_GFX_CG_THRU_SMU);
 			hwmgr->pp_table_version = PP_TABLE_V0;
+			hwmgr->od_enabled = false;
 			break;
 		case CHIP_TONGA:
 			hwmgr->smumgr_funcs = &tonga_smu_funcs;
-- 
1.9.1

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Re: [PATCH v2 4/7] drm/amd/pp: Disable OD feature on CI/Iceland.

[Alex Deucher]

On Fri, Jan 19, 2018 at 3:10 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I9bb42d70b6a6b31c0eecc3ee2faf487982957356
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Typo in the subject.  should be CZ/Iceland

Please also add a commit message.  Something like:

drm/amd/pp: Disable OD feature on CZ/Iceland

Not supported on APUs or Iceland.

With those fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 2690446..c5411fe 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -167,6 +167,7 @@ int hwmgr_early_init(struct pp_instance *handle)
>                 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
>                                         PP_ENABLE_GFX_CG_THRU_SMU);
>                 hwmgr->pp_table_version = PP_TABLE_V0;
> +               hwmgr->od_enabled = false;
>                 smu7_init_function_pointers(hwmgr);
>                 break;
>         case AMDGPU_FAMILY_CZ:
> @@ -181,6 +182,7 @@ int hwmgr_early_init(struct pp_instance *handle)
>                         hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
>                                                 PP_ENABLE_GFX_CG_THRU_SMU);
>                         hwmgr->pp_table_version = PP_TABLE_V0;
> +                       hwmgr->od_enabled = false;
>                         break;
>                 case CHIP_TONGA:
>                         hwmgr->smumgr_funcs = &tonga_smu_funcs;
> --
> 1.9.1
>
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[PATCH v2 5/7] drm/amd/pp: Implement edit_dpm_table on smu7

[Rex Zhu]

v2: - check clk against OverDrive limits from VBIOS
    - set OD flag when user commit the setting.

Change-Id: If7b4f6a1a7049f5d13d47603d3446b66cf6e9d4a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 165 ++++++++++++++++++++++-
 1 file changed, 164 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4ccc910..3ed4b4a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4808,6 +4808,169 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+					enum PP_OD_DPM_TABLE_COMMAND type,
+					uint32_t clk,
+					uint32_t voltage)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	uint32_t min_vddc;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+
+	if (table_info == NULL)
+		return -EINVAL;
+
+	dep_sclk_table = table_info->vdd_dep_on_sclk;
+	min_vddc = dep_sclk_table->entries[0].vddc;
+
+	if (voltage < min_vddc || voltage > 2000) {
+		pr_info("OD voltage is out of range [%d - 2000] mV\n", min_vddc);
+		return false;
+	}
+
+	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
+		if (data->vbios_boot_state.sclk_bootup_value > clk ||
+			hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
+			pr_info("OD engine clock is out of range [%d - %d] MHz\n",
+				data->vbios_boot_state.sclk_bootup_value,
+				hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
+			return false;
+		}
+	} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
+		if (data->vbios_boot_state.mclk_bootup_value > clk ||
+			hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
+			pr_info("OD memory clock is out of range [%d - %d] MHz\n",
+				data->vbios_boot_state.mclk_bootup_value/100,
+				hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
+			return false;
+		}
+	} else {
+		return false;
+	}
+
+	return true;
+}
+
+static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	uint32_t i;
+
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
+	struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
+
+	if (table_info == NULL)
+		return;
+
+	for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+		if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
+					data->dpm_table.sclk_table.dpm_levels[i].value) {
+			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+			break;
+		}
+	}
+
+	for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+		if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
+					data->dpm_table.mclk_table.dpm_levels[i].value) {
+			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+			break;
+		}
+	}
+
+	dep_table = table_info->vdd_dep_on_mclk;
+	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
+
+	for (i=0; i<dep_table->count; i++) {
+		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+			return;
+		}
+	}
+
+	dep_table = table_info->vdd_dep_on_sclk;
+	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
+	for (i=0; i<dep_table->count; i++) {
+		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+			return;
+		}
+	}
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+					enum PP_OD_DPM_TABLE_COMMAND type,
+					long *input, uint32_t size)
+{
+	uint32_t i;
+	struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+	struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	uint32_t input_clk;
+	uint32_t input_vol;
+	uint32_t input_level;
+
+	PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+				return -EINVAL);
+
+	if (!hwmgr->od_enabled) {
+		pr_info("OverDrive feature not enabled\n");
+		return -EINVAL;
+	}
+
+	if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
+		podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
+		podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
+		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+				"Failed to get ODN SCLK and Voltage tables",
+				return -EINVAL);
+	} else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
+		podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
+		podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
+
+		PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+			"Failed to get ODN MCLK and Voltage tables",
+			return -EINVAL);
+	} else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
+		smu7_odn_initial_default_setting(hwmgr);
+		return 0;
+	} else if (PP_OD_COMMIT_DPM_TABLE == type) {
+		smu7_check_dpm_table_updated(hwmgr);
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+
+	for (i = 0; i < size; i += 3) {
+		if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
+			pr_info("invalid clock voltage input \n");
+			return 0;
+		}
+		input_level = input[i];
+		input_clk = input[i+1] * 100;
+		input_vol = input[i+2];
+
+		if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
+			podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
+			podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
+			podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
+			podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
+		} else {
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.backend_init = &smu7_hwmgr_backend_init,
 	.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4862,6 +5025,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
 	.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
 	.get_max_high_clocks = smu7_get_max_high_clocks,
 	.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
+	.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
@@ -4893,4 +5057,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
 
 	return ret;
 }
-
-- 
1.9.1

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Re: [PATCH v2 5/7] drm/amd/pp: Implement edit_dpm_table on smu7

[Alex Deucher]

On Fri, Jan 19, 2018 at 3:10 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> v2: - check clk against OverDrive limits from VBIOS
>     - set OD flag when user commit the setting.
>
> Change-Id: If7b4f6a1a7049f5d13d47603d3446b66cf6e9d4a
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>


Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 165 ++++++++++++++++++++++-
>  1 file changed, 164 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 4ccc910..3ed4b4a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4808,6 +4808,169 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
>         return 0;
>  }
>
> +static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
> +                                       enum PP_OD_DPM_TABLE_COMMAND type,
> +                                       uint32_t clk,
> +                                       uint32_t voltage)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> +       struct phm_ppt_v1_information *table_info =
> +                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
> +       uint32_t min_vddc;
> +       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
> +
> +       if (table_info == NULL)
> +               return -EINVAL;
> +
> +       dep_sclk_table = table_info->vdd_dep_on_sclk;
> +       min_vddc = dep_sclk_table->entries[0].vddc;
> +
> +       if (voltage < min_vddc || voltage > 2000) {
> +               pr_info("OD voltage is out of range [%d - 2000] mV\n", min_vddc);
> +               return false;
> +       }
> +
> +       if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
> +               if (data->vbios_boot_state.sclk_bootup_value > clk ||
> +                       hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
> +                       pr_info("OD engine clock is out of range [%d - %d] MHz\n",
> +                               data->vbios_boot_state.sclk_bootup_value,
> +                               hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
> +                       return false;
> +               }
> +       } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
> +               if (data->vbios_boot_state.mclk_bootup_value > clk ||
> +                       hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
> +                       pr_info("OD memory clock is out of range [%d - %d] MHz\n",
> +                               data->vbios_boot_state.mclk_bootup_value/100,
> +                               hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
> +                       return false;
> +               }
> +       } else {
> +               return false;
> +       }
> +
> +       return true;
> +}
> +
> +static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +       struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> +       struct phm_ppt_v1_information *table_info =
> +                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
> +       uint32_t i;
> +
> +       struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
> +       struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
> +
> +       if (table_info == NULL)
> +               return;
> +
> +       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
> +               if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
> +                                       data->dpm_table.sclk_table.dpm_levels[i].value) {
> +                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
> +                       break;
> +               }
> +       }
> +
> +       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
> +               if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
> +                                       data->dpm_table.mclk_table.dpm_levels[i].value) {
> +                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
> +                       break;
> +               }
> +       }
> +
> +       dep_table = table_info->vdd_dep_on_mclk;
> +       odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
> +
> +       for (i=0; i<dep_table->count; i++) {
> +               if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
> +                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
> +                       return;
> +               }
> +       }
> +
> +       dep_table = table_info->vdd_dep_on_sclk;
> +       odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
> +       for (i=0; i<dep_table->count; i++) {
> +               if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
> +                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
> +                       return;
> +               }
> +       }
> +}
> +
> +static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
> +                                       enum PP_OD_DPM_TABLE_COMMAND type,
> +                                       long *input, uint32_t size)
> +{
> +       uint32_t i;
> +       struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
> +       struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> +       uint32_t input_clk;
> +       uint32_t input_vol;
> +       uint32_t input_level;
> +
> +       PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
> +                               return -EINVAL);
> +
> +       if (!hwmgr->od_enabled) {
> +               pr_info("OverDrive feature not enabled\n");
> +               return -EINVAL;
> +       }
> +
> +       if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
> +               podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
> +               podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
> +               PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> +                               "Failed to get ODN SCLK and Voltage tables",
> +                               return -EINVAL);
> +       } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
> +               podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
> +               podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
> +
> +               PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> +                       "Failed to get ODN MCLK and Voltage tables",
> +                       return -EINVAL);
> +       } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
> +               smu7_odn_initial_default_setting(hwmgr);
> +               return 0;
> +       } else if (PP_OD_COMMIT_DPM_TABLE == type) {
> +               smu7_check_dpm_table_updated(hwmgr);
> +               return 0;
> +       } else {
> +               return -EINVAL;
> +       }
> +
> +       for (i = 0; i < size; i += 3) {
> +               if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
> +                       pr_info("invalid clock voltage input \n");
> +                       return 0;
> +               }
> +               input_level = input[i];
> +               input_clk = input[i+1] * 100;
> +               input_vol = input[i+2];
> +
> +               if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
> +                       podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
> +                       podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
> +                       podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
> +                       podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
> +               } else {
> +                       return -EINVAL;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
>         .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -4862,6 +5025,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
>         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
>         .get_max_high_clocks = smu7_get_max_high_clocks,
>         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
> +       .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> @@ -4893,4 +5057,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
>
>         return ret;
>  }
> -
> --
> 1.9.1
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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答复: [PATCH v2 5/7] drm/amd/pp: Implement edit_dpm_table on smu7

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 10052 bytes --]

+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+               if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
+                                       data->dpm_table.sclk_table.dpm_levels[i].value) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+                       break;
+               }
+       }
+
+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {

typo? sclk_table -> mclk_table?
+               if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
+                                       data->dpm_table.mclk_table.dpm_levels[i].value) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+                       break;
+               }
+       }


Regards,

Evan

________________________________
发件人: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> 代表 Rex Zhu <Rex.Zhu@amd.com>
发送时间: 2018年1月19日 16:10:09
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Rex
主题: [PATCH v2 5/7] drm/amd/pp: Implement edit_dpm_table on smu7

v2: - check clk against OverDrive limits from VBIOS
    - set OD flag when user commit the setting.

Change-Id: If7b4f6a1a7049f5d13d47603d3446b66cf6e9d4a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 165 ++++++++++++++++++++++-
 1 file changed, 164 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4ccc910..3ed4b4a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4808,6 +4808,169 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         return 0;
 }

+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+                                       enum PP_OD_DPM_TABLE_COMMAND type,
+                                       uint32_t clk,
+                                       uint32_t voltage)
+{
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
+       uint32_t min_vddc;
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+
+       if (table_info == NULL)
+               return -EINVAL;
+
+       dep_sclk_table = table_info->vdd_dep_on_sclk;
+       min_vddc = dep_sclk_table->entries[0].vddc;
+
+       if (voltage < min_vddc || voltage > 2000) {
+               pr_info("OD voltage is out of range [%d - 2000] mV\n", min_vddc);
+               return false;
+       }
+
+       if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
+               if (data->vbios_boot_state.sclk_bootup_value > clk ||
+                       hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
+                       pr_info("OD engine clock is out of range [%d - %d] MHz\n",
+                               data->vbios_boot_state.sclk_bootup_value,
+                               hwmgr->platform_descriptor.overdriveLimit.engineClock / 100);
+                       return false;
+               }
+       } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
+               if (data->vbios_boot_state.mclk_bootup_value > clk ||
+                       hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
+                       pr_info("OD memory clock is out of range [%d - %d] MHz\n",
+                               data->vbios_boot_state.mclk_bootup_value/100,
+                               hwmgr->platform_descriptor.overdriveLimit.memoryClock / 100);
+                       return false;
+               }
+       } else {
+               return false;
+       }
+
+       return true;
+}
+
+static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
+{
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+       struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
+       uint32_t i;
+
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
+       struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
+
+       if (table_info == NULL)
+               return;
+
+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+               if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
+                                       data->dpm_table.sclk_table.dpm_levels[i].value) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+                       break;
+               }
+       }
+
+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+               if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
+                                       data->dpm_table.mclk_table.dpm_levels[i].value) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+                       break;
+               }
+       }
+
+       dep_table = table_info->vdd_dep_on_mclk;
+       odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
+
+       for (i=0; i<dep_table->count; i++) {
+               if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+                       return;
+               }
+       }
+
+       dep_table = table_info->vdd_dep_on_sclk;
+       odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
+       for (i=0; i<dep_table->count; i++) {
+               if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
+                       data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+                       return;
+               }
+       }
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+                                       enum PP_OD_DPM_TABLE_COMMAND type,
+                                       long *input, uint32_t size)
+{
+       uint32_t i;
+       struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+       struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+       uint32_t input_clk;
+       uint32_t input_vol;
+       uint32_t input_level;
+
+       PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+                               return -EINVAL);
+
+       if (!hwmgr->od_enabled) {
+               pr_info("OverDrive feature not enabled\n");
+               return -EINVAL;
+       }
+
+       if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
+               podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
+               podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
+               PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+                               "Failed to get ODN SCLK and Voltage tables",
+                               return -EINVAL);
+       } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
+               podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
+               podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
+
+               PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+                       "Failed to get ODN MCLK and Voltage tables",
+                       return -EINVAL);
+       } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
+               smu7_odn_initial_default_setting(hwmgr);
+               return 0;
+       } else if (PP_OD_COMMIT_DPM_TABLE == type) {
+               smu7_check_dpm_table_updated(hwmgr);
+               return 0;
+       } else {
+               return -EINVAL;
+       }
+
+       for (i = 0; i < size; i += 3) {
+               if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
+                       pr_info("invalid clock voltage input \n");
+                       return 0;
+               }
+               input_level = input[i];
+               input_clk = input[i+1] * 100;
+               input_vol = input[i+2];
+
+               if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
+                       podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
+                       podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
+                       podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
+                       podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
+               } else {
+                       return -EINVAL;
+               }
+       }
+
+       return 0;
+}
+
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
         .backend_init = &smu7_hwmgr_backend_init,
         .backend_fini = &smu7_hwmgr_backend_fini,
@@ -4862,6 +5025,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
         .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
         .get_max_high_clocks = smu7_get_max_high_clocks,
         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
+       .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
 };

 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
@@ -4893,4 +5057,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)

         return ret;
 }
-
--
1.9.1

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[-- Attachment #1.2: Type: text/html, Size: 30302 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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[PATCH v2 6/7] drm/amd/pp: Update smu7 dpm table with OD clock/voltage

[Rex Zhu]

delete old OD type code path when populate clk.

Change-Id: I23ce870ea5adf9227bb6f35e33c0ce99fa4e9ced
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 124 +++++----------------
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  18 ++-
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  18 ++-
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    |  18 ++-
 4 files changed, 71 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 3ed4b4a..cab1cf4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3482,8 +3482,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
 	uint32_t i;
 	struct cgs_display_info info = {0};
 
-	data->need_update_smu7_dpm_table = 0;
-
 	for (i = 0; i < sclk_table->count; i++) {
 		if (sclk == sclk_table->dpm_levels[i].value)
 			break;
@@ -3625,106 +3623,27 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
 		struct pp_hwmgr *hwmgr, const void *input)
 {
 	int result = 0;
-	const struct phm_set_power_state_input *states =
-			(const struct phm_set_power_state_input *)input;
-	const struct smu7_power_state *smu7_ps =
-			cast_const_phw_smu7_power_state(states->pnew_state);
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-	uint32_t sclk = smu7_ps->performance_levels
-			[smu7_ps->performance_level_count - 1].engine_clock;
-	uint32_t mclk = smu7_ps->performance_levels
-			[smu7_ps->performance_level_count - 1].memory_clock;
 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
-
-	struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
-	uint32_t dpm_count, clock_percent;
-	uint32_t i;
+	uint32_t count;
+	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+	struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+	struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
 
 	if (0 == data->need_update_smu7_dpm_table)
 		return 0;
 
-	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-		dpm_table->sclk_table.dpm_levels
-		[dpm_table->sclk_table.count - 1].value = sclk;
-
-		if (hwmgr->od_enabled) {
-		/* Need to do calculation based on the golden DPM table
-		 * as the Heatmap GPU Clock axis is also based on the default values
-		 */
-			PP_ASSERT_WITH_CODE(
-				(golden_dpm_table->sclk_table.dpm_levels
-						[golden_dpm_table->sclk_table.count - 1].value != 0),
-				"Divide by 0!",
-				return -EINVAL);
-			dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-
-			for (i = dpm_count; i > 1; i--) {
-				if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
-					clock_percent =
-					      ((sclk
-						- golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
-						) * 100)
-						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-					dpm_table->sclk_table.dpm_levels[i].value =
-							golden_dpm_table->sclk_table.dpm_levels[i].value +
-							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-								clock_percent)/100;
-
-				} else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
-					clock_percent =
-						((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
-						- sclk) * 100)
-						/ golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-					dpm_table->sclk_table.dpm_levels[i].value =
-							golden_dpm_table->sclk_table.dpm_levels[i].value -
-							(golden_dpm_table->sclk_table.dpm_levels[i].value *
-									clock_percent) / 100;
-				} else
-					dpm_table->sclk_table.dpm_levels[i].value =
-							golden_dpm_table->sclk_table.dpm_levels[i].value;
-			}
+	if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+		for (count = 0; count < dpm_table->sclk_table.count; count++) {
+			dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
+			dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
 		}
 	}
 
-	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-		dpm_table->mclk_table.dpm_levels
-			[dpm_table->mclk_table.count - 1].value = mclk;
-
-		if (hwmgr->od_enabled) {
-
-			PP_ASSERT_WITH_CODE(
-					(golden_dpm_table->mclk_table.dpm_levels
-						[golden_dpm_table->mclk_table.count-1].value != 0),
-					"Divide by 0!",
-					return -EINVAL);
-			dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
-			for (i = dpm_count; i > 1; i--) {
-				if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
-					clock_percent = ((mclk -
-					golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
-					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
-					dpm_table->mclk_table.dpm_levels[i].value =
-							golden_dpm_table->mclk_table.dpm_levels[i].value +
-							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-							clock_percent) / 100;
-
-				} else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
-					clock_percent = (
-					 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
-					* 100)
-					/ golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
-					dpm_table->mclk_table.dpm_levels[i].value =
-							golden_dpm_table->mclk_table.dpm_levels[i].value -
-							(golden_dpm_table->mclk_table.dpm_levels[i].value *
-									clock_percent) / 100;
-				} else
-					dpm_table->mclk_table.dpm_levels[i].value =
-							golden_dpm_table->mclk_table.dpm_levels[i].value;
-			}
+	if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
+		for (count = 0; count < dpm_table->mclk_table.count; count++) {
+			dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
+			dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
 		}
 	}
 
@@ -3846,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
 		    return -EINVAL);
 	}
 
-	data->need_update_smu7_dpm_table = 0;
+	data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
 
 	return 0;
 }
@@ -4114,6 +4033,7 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
 	const struct smu7_power_state *psa;
 	const struct smu7_power_state *psb;
 	int i;
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
 	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
 		return -EINVAL;
@@ -4138,6 +4058,10 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
 	*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
 	*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
 	*equal &= (psa->sclk_threshold == psb->sclk_threshold);
+	/* For OD call, set value based on flag */
+	*equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
+							DPMTABLE_OD_UPDATE_MCLK |
+							DPMTABLE_OD_UPDATE_VDDC));
 
 	return 0;
 }
@@ -4887,21 +4811,25 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
 	dep_table = table_info->vdd_dep_on_mclk;
 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
 
-	for (i=0; i<dep_table->count; i++) {
+	for (i=0; i < dep_table->count; i++) {
 		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-			return;
+			break;
 		}
 	}
+	if (i == dep_table->count)
+		data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 
 	dep_table = table_info->vdd_dep_on_sclk;
 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
-	for (i=0; i<dep_table->count; i++) {
+	for (i=0; i < dep_table->count; i++) {
 		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
 			data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-			return;
+			break;
 		}
 	}
+	if (i == dep_table->count)
+		data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 }
 
 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 7d9e2cb..73c6020 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -981,12 +981,18 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
 
 	result = fiji_calculate_sclk_params(hwmgr, clock, level);
 
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = table_info->vdd_dep_on_sclk;
+
 	/* populate graphics levels */
 	result = fiji_get_dependency_volt_by_clk(hwmgr,
-			table_info->vdd_dep_on_sclk, clock,
+			vdd_dep_table, clock,
 			(uint32_t *)(&level->MinVoltage), &mvdd);
 	PP_ASSERT_WITH_CODE((0 == result),
 			"can not find VDDC voltage value for "
@@ -1202,10 +1208,16 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	int result = 0;
 	uint32_t mclk_stutter_mode_threshold = 60000;
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = table_info->vdd_dep_on_mclk;
 
-	if (table_info->vdd_dep_on_mclk) {
+	if (vdd_dep_table) {
 		result = fiji_get_dependency_volt_by_clk(hwmgr,
-				table_info->vdd_dep_on_mclk, clock,
+				vdd_dep_table, clock,
 				(uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
 		PP_ASSERT_WITH_CODE((0 == result),
 				"can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f1a3bc8..a760a82 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -948,12 +948,18 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	SMU_SclkSetting curr_sclk_setting = { 0 };
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
 
 	result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
 
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = table_info->vdd_dep_on_sclk;
+
 	/* populate graphics levels */
 	result = polaris10_get_dependency_volt_by_clk(hwmgr,
-			table_info->vdd_dep_on_sclk, clock,
+			vdd_dep_table, clock,
 			&level->MinVoltage, &mvdd);
 
 	PP_ASSERT_WITH_CODE((0 == result),
@@ -1107,12 +1113,18 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
 	int result = 0;
 	struct cgs_display_info info = {0, 0, NULL};
 	uint32_t mclk_stutter_mode_threshold = 40000;
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
 
 	cgs_get_active_displays_info(hwmgr->device, &info);
 
-	if (table_info->vdd_dep_on_mclk) {
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = table_info->vdd_dep_on_mclk;
+
+	if (vdd_dep_table) {
 		result = polaris10_get_dependency_volt_by_clk(hwmgr,
-				table_info->vdd_dep_on_mclk, clock,
+				vdd_dep_table, clock,
 				&mem_level->MinVoltage, &mem_level->MinMvdd);
 		PP_ASSERT_WITH_CODE((0 == result),
 				"can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index a03a345..4b3fd04 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -620,12 +620,18 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *pptable_info =
 			    (struct phm_ppt_v1_information *)(hwmgr->pptable);
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
 
 	result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
 
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = pptable_info->vdd_dep_on_sclk;
+
 	/* populate graphics levels*/
 	result = tonga_get_dependency_volt_by_clk(hwmgr,
-		pptable_info->vdd_dep_on_sclk, engine_clock,
+		vdd_dep_table, engine_clock,
 		&graphic_level->MinVoltage, &mvdd);
 	PP_ASSERT_WITH_CODE((!result),
 		"can not find VDDC voltage value for VDDC "
@@ -966,10 +972,16 @@ static int tonga_populate_single_memory_level(
 	uint32_t mclk_stutter_mode_threshold = 30000;
 	uint32_t mclk_edc_enable_threshold = 40000;
 	uint32_t mclk_strobe_mode_threshold = 40000;
+	phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+	if (hwmgr->od_enabled)
+		vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+	else
+		vdd_dep_table = pptable_info->vdd_dep_on_mclk;
 
-	if (NULL != pptable_info->vdd_dep_on_mclk) {
+	if (NULL != vdd_dep_table) {
 		result = tonga_get_dependency_volt_by_clk(hwmgr,
-				pptable_info->vdd_dep_on_mclk,
+				vdd_dep_table,
 				memory_clock,
 				&memory_level->MinVoltage, &mvdd);
 		PP_ASSERT_WITH_CODE(
-- 
1.9.1

_______________________________________________
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答复: [PATCH v2 6/7] drm/amd/pp: Update smu7 dpm table with OD clock/voltage

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 21171 bytes --]

@@ -4887,21 +4811,25 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
         dep_table = table_info->vdd_dep_on_mclk;
         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);

-       for (i=0; i<dep_table->count; i++) {
+       for (i=0; i < dep_table->count; i++) {
                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-                       return;
+                       break;
                 }
         }
+       if (i == dep_table->count)
+               data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;

         dep_table = table_info->vdd_dep_on_sclk;
         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
-       for (i=0; i<dep_table->count; i++) {
+       for (i=0; i < dep_table->count; i++) {
                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-                       return;
+                       break;
                 }
         }
+       if (i == dep_table->count)
+               data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 }
 The logic here is a little confusing. It seems if vdd_dependency_on_mclk has vddc changes while no vddc change for vdd_dependency_on_sclk, the DPMTABLE_OD_UPDATE_VDDC flag will be cleared. Is this desired?


Regards,

Evan

________________________________
发件人: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> 代表 Rex Zhu <Rex.Zhu@amd.com>
发送时间: 2018年1月19日 16:10:10
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Rex
主题: [PATCH v2 6/7] drm/amd/pp: Update smu7 dpm table with OD clock/voltage

delete old OD type code path when populate clk.

Change-Id: I23ce870ea5adf9227bb6f35e33c0ce99fa4e9ced
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 124 +++++----------------
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  18 ++-
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  18 ++-
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    |  18 ++-
 4 files changed, 71 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 3ed4b4a..cab1cf4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3482,8 +3482,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
         uint32_t i;
         struct cgs_display_info info = {0};

-       data->need_update_smu7_dpm_table = 0;
-
         for (i = 0; i < sclk_table->count; i++) {
                 if (sclk == sclk_table->dpm_levels[i].value)
                         break;
@@ -3625,106 +3623,27 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
                 struct pp_hwmgr *hwmgr, const void *input)
 {
         int result = 0;
-       const struct phm_set_power_state_input *states =
-                       (const struct phm_set_power_state_input *)input;
-       const struct smu7_power_state *smu7_ps =
-                       cast_const_phw_smu7_power_state(states->pnew_state);
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
-       uint32_t sclk = smu7_ps->performance_levels
-                       [smu7_ps->performance_level_count - 1].engine_clock;
-       uint32_t mclk = smu7_ps->performance_levels
-                       [smu7_ps->performance_level_count - 1].memory_clock;
         struct smu7_dpm_table *dpm_table = &data->dpm_table;
-
-       struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
-       uint32_t dpm_count, clock_percent;
-       uint32_t i;
+       uint32_t count;
+       struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+       struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+       struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);

         if (0 == data->need_update_smu7_dpm_table)
                 return 0;

-       if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
-               dpm_table->sclk_table.dpm_levels
-               [dpm_table->sclk_table.count - 1].value = sclk;
-
-               if (hwmgr->od_enabled) {
-               /* Need to do calculation based on the golden DPM table
-                * as the Heatmap GPU Clock axis is also based on the default values
-                */
-                       PP_ASSERT_WITH_CODE(
-                               (golden_dpm_table->sclk_table.dpm_levels
-                                               [golden_dpm_table->sclk_table.count - 1].value != 0),
-                               "Divide by 0!",
-                               return -EINVAL);
-                       dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-
-                       for (i = dpm_count; i > 1; i--) {
-                               if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
-                                       clock_percent =
-                                             ((sclk
-                                               - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
-                                               ) * 100)
-                                               / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-                                       dpm_table->sclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->sclk_table.dpm_levels[i].value +
-                                                       (golden_dpm_table->sclk_table.dpm_levels[i].value *
-                                                               clock_percent)/100;
-
-                               } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
-                                       clock_percent =
-                                               ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
-                                               - sclk) * 100)
-                                               / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
-                                       dpm_table->sclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->sclk_table.dpm_levels[i].value -
-                                                       (golden_dpm_table->sclk_table.dpm_levels[i].value *
-                                                                       clock_percent) / 100;
-                               } else
-                                       dpm_table->sclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->sclk_table.dpm_levels[i].value;
-                       }
+       if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+               for (count = 0; count < dpm_table->sclk_table.count; count++) {
+                       dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
+                       dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
                 }
         }

-       if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
-               dpm_table->mclk_table.dpm_levels
-                       [dpm_table->mclk_table.count - 1].value = mclk;
-
-               if (hwmgr->od_enabled) {
-
-                       PP_ASSERT_WITH_CODE(
-                                       (golden_dpm_table->mclk_table.dpm_levels
-                                               [golden_dpm_table->mclk_table.count-1].value != 0),
-                                       "Divide by 0!",
-                                       return -EINVAL);
-                       dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
-                       for (i = dpm_count; i > 1; i--) {
-                               if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
-                                       clock_percent = ((mclk -
-                                       golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
-                                       / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
-                                       dpm_table->mclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->mclk_table.dpm_levels[i].value +
-                                                       (golden_dpm_table->mclk_table.dpm_levels[i].value *
-                                                       clock_percent) / 100;
-
-                               } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
-                                       clock_percent = (
-                                        (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
-                                       * 100)
-                                       / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
-                                       dpm_table->mclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->mclk_table.dpm_levels[i].value -
-                                                       (golden_dpm_table->mclk_table.dpm_levels[i].value *
-                                                                       clock_percent) / 100;
-                               } else
-                                       dpm_table->mclk_table.dpm_levels[i].value =
-                                                       golden_dpm_table->mclk_table.dpm_levels[i].value;
-                       }
+       if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
+               for (count = 0; count < dpm_table->mclk_table.count; count++) {
+                       dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
+                       dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
                 }
         }

@@ -3846,7 +3765,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                     return -EINVAL);
         }

-       data->need_update_smu7_dpm_table = 0;
+       data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;

         return 0;
 }
@@ -4114,6 +4033,7 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
         const struct smu7_power_state *psa;
         const struct smu7_power_state *psb;
         int i;
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);

         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
                 return -EINVAL;
@@ -4138,6 +4058,10 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
+       /* For OD call, set value based on flag */
+       *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
+                                                       DPMTABLE_OD_UPDATE_MCLK |
+                                                       DPMTABLE_OD_UPDATE_VDDC));

         return 0;
 }
@@ -4887,21 +4811,25 @@ static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
         dep_table = table_info->vdd_dep_on_mclk;
         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);

-       for (i=0; i<dep_table->count; i++) {
+       for (i=0; i < dep_table->count; i++) {
                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-                       return;
+                       break;
                 }
         }
+       if (i == dep_table->count)
+               data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;

         dep_table = table_info->vdd_dep_on_sclk;
         odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
-       for (i=0; i<dep_table->count; i++) {
+       for (i=0; i < dep_table->count; i++) {
                 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
                         data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
-                       return;
+                       break;
                 }
         }
+       if (i == dep_table->count)
+               data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
 }

 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 7d9e2cb..73c6020 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -981,12 +981,18 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
         struct phm_ppt_v1_information *table_info =
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;

         result = fiji_calculate_sclk_params(hwmgr, clock, level);

+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = table_info->vdd_dep_on_sclk;
+
         /* populate graphics levels */
         result = fiji_get_dependency_volt_by_clk(hwmgr,
-                       table_info->vdd_dep_on_sclk, clock,
+                       vdd_dep_table, clock,
                         (uint32_t *)(&level->MinVoltage), &mvdd);
         PP_ASSERT_WITH_CODE((0 == result),
                         "can not find VDDC voltage value for "
@@ -1202,10 +1208,16 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
         int result = 0;
         uint32_t mclk_stutter_mode_threshold = 60000;
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = table_info->vdd_dep_on_mclk;

-       if (table_info->vdd_dep_on_mclk) {
+       if (vdd_dep_table) {
                 result = fiji_get_dependency_volt_by_clk(hwmgr,
-                               table_info->vdd_dep_on_mclk, clock,
+                               vdd_dep_table, clock,
                                 (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
                 PP_ASSERT_WITH_CODE((0 == result),
                                 "can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f1a3bc8..a760a82 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -948,12 +948,18 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
         struct phm_ppt_v1_information *table_info =
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
         SMU_SclkSetting curr_sclk_setting = { 0 };
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;

         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);

+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = table_info->vdd_dep_on_sclk;
+
         /* populate graphics levels */
         result = polaris10_get_dependency_volt_by_clk(hwmgr,
-                       table_info->vdd_dep_on_sclk, clock,
+                       vdd_dep_table, clock,
                         &level->MinVoltage, &mvdd);

         PP_ASSERT_WITH_CODE((0 == result),
@@ -1107,12 +1113,18 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
         int result = 0;
         struct cgs_display_info info = {0, 0, NULL};
         uint32_t mclk_stutter_mode_threshold = 40000;
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;

         cgs_get_active_displays_info(hwmgr->device, &info);

-       if (table_info->vdd_dep_on_mclk) {
+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = table_info->vdd_dep_on_mclk;
+
+       if (vdd_dep_table) {
                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
-                               table_info->vdd_dep_on_mclk, clock,
+                               vdd_dep_table, clock,
                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
                 PP_ASSERT_WITH_CODE((0 == result),
                                 "can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index a03a345..4b3fd04 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -620,12 +620,18 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
         struct phm_ppt_v1_information *pptable_info =
                             (struct phm_ppt_v1_information *)(hwmgr->pptable);
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;

         result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);

+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = pptable_info->vdd_dep_on_sclk;
+
         /* populate graphics levels*/
         result = tonga_get_dependency_volt_by_clk(hwmgr,
-               pptable_info->vdd_dep_on_sclk, engine_clock,
+               vdd_dep_table, engine_clock,
                 &graphic_level->MinVoltage, &mvdd);
         PP_ASSERT_WITH_CODE((!result),
                 "can not find VDDC voltage value for VDDC "
@@ -966,10 +972,16 @@ static int tonga_populate_single_memory_level(
         uint32_t mclk_stutter_mode_threshold = 30000;
         uint32_t mclk_edc_enable_threshold = 40000;
         uint32_t mclk_strobe_mode_threshold = 40000;
+       phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+       if (hwmgr->od_enabled)
+               vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+       else
+               vdd_dep_table = pptable_info->vdd_dep_on_mclk;

-       if (NULL != pptable_info->vdd_dep_on_mclk) {
+       if (NULL != vdd_dep_table) {
                 result = tonga_get_dependency_volt_by_clk(hwmgr,
-                               pptable_info->vdd_dep_on_mclk,
+                               vdd_dep_table,
                                 memory_clock,
                                 &memory_level->MinVoltage, &mvdd);
                 PP_ASSERT_WITH_CODE(
--
1.9.1

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[PATCH v2 7/7] drm/amd/pp: Add update_avfs call when set_power_state

[Rex Zhu]

when Overdrive voltage, need to disable AVFS.
when OverDriv engine clock, need to recalculate
AVFS voltage by disable/enable avfs feature.

Change-Id: I8545becd405949e80d8ced05d6b61ac65f71010f
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 85 ++++++++++++++++--------
 1 file changed, 57 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index cab1cf4..54f569c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
 	DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 };
 
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,58 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+	if (smu_data == NULL)
+		return -EINVAL;
+
+	if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+		return 0;
+
+	if (enable) {
+		if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+				CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+			PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+					hwmgr, PPSMC_MSG_EnableAvfs),
+					"Failed to enable AVFS!",
+					return -EINVAL);
+		}
+	} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+			CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+				hwmgr, PPSMC_MSG_DisableAvfs),
+				"Failed to disable AVFS!",
+				return -EINVAL);
+	}
+
+	return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	if (smu_data == NULL)
+		return -EINVAL;
+
+	if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+		return 0;
+
+	if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+		smu7_avfs_control(hwmgr, false);
+	} else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+		smu7_avfs_control(hwmgr, false);
+		smu7_avfs_control(hwmgr, true);
+	} else {
+		smu7_avfs_control(hwmgr, true);
+	}
+
+	return 0;
+}
+
 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
 	int tmp_result, result = 0;
@@ -3842,6 +3893,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 			"Failed to populate and upload SCLK MCLK DPM levels!",
 			result = tmp_result);
 
+	tmp_result = smu7_update_avfs(hwmgr);
+	PP_ASSERT_WITH_CODE((0 == tmp_result),
+			"Failed to update avfs voltages!",
+			result = tmp_result);
+
 	tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
 	PP_ASSERT_WITH_CODE((0 == tmp_result),
 			"Failed to generate DPM level enabled mask!",
@@ -4626,33 +4682,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
 	return result;
 }
 
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
-	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
-	if (smu_data == NULL)
-		return -EINVAL;
-
-	if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
-		return 0;
-
-	if (enable) {
-		if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-				CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-			PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-					hwmgr, PPSMC_MSG_EnableAvfs),
-					"Failed to enable AVFS!",
-					return -EINVAL);
-	} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-			CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-				hwmgr, PPSMC_MSG_DisableAvfs),
-				"Failed to disable AVFS!",
-				return -EINVAL);
-
-	return 0;
-}
-
 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
 					uint32_t virtual_addr_low,
 					uint32_t virtual_addr_hi,
-- 
1.9.1

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答复: [PATCH v2 7/7] drm/amd/pp: Add update_avfs call when set_power_state

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 5926 bytes --]

Do we need to reset need_update_smu7_dpm_table flag as 0 in smu7_set_power_state_tasks?


Regards,

Evan

________________________________
发件人: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> 代表 Rex Zhu <Rex.Zhu@amd.com>
发送时间: 2018年1月19日 16:10:11
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhu, Rex
主题: [PATCH v2 7/7] drm/amd/pp: Add update_avfs call when set_power_state

when Overdrive voltage, need to disable AVFS.
when OverDriv engine clock, need to recalculate
AVFS voltage by disable/enable avfs feature.

Change-Id: I8545becd405949e80d8ced05d6b61ac65f71010f
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 85 ++++++++++++++++--------
 1 file changed, 57 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index cab1cf4..54f569c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 };

-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,58 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
         return 0;
 }

+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+       struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+       if (smu_data == NULL)
+               return -EINVAL;
+
+       if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+               return 0;
+
+       if (enable) {
+               if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+                               CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+                       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+                                       hwmgr, PPSMC_MSG_EnableAvfs),
+                                       "Failed to enable AVFS!",
+                                       return -EINVAL);
+               }
+       } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+                       CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+               PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+                               hwmgr, PPSMC_MSG_DisableAvfs),
+                               "Failed to disable AVFS!",
+                               return -EINVAL);
+       }
+
+       return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+       struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+       if (smu_data == NULL)
+               return -EINVAL;
+
+       if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+               return 0;
+
+       if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+               smu7_avfs_control(hwmgr, false);
+       } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+               smu7_avfs_control(hwmgr, false);
+               smu7_avfs_control(hwmgr, true);
+       } else {
+               smu7_avfs_control(hwmgr, true);
+       }
+
+       return 0;
+}
+
 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 {
         int tmp_result, result = 0;
@@ -3842,6 +3893,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
                         "Failed to populate and upload SCLK MCLK DPM levels!",
                         result = tmp_result);

+       tmp_result = smu7_update_avfs(hwmgr);
+       PP_ASSERT_WITH_CODE((0 == tmp_result),
+                       "Failed to update avfs voltages!",
+                       result = tmp_result);
+
         tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
         PP_ASSERT_WITH_CODE((0 == tmp_result),
                         "Failed to generate DPM level enabled mask!",
@@ -4626,33 +4682,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
         return result;
 }

-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
-       struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
-       if (smu_data == NULL)
-               return -EINVAL;
-
-       if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
-               return 0;
-
-       if (enable) {
-               if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-                               CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-                       PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-                                       hwmgr, PPSMC_MSG_EnableAvfs),
-                                       "Failed to enable AVFS!",
-                                       return -EINVAL);
-       } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
-                       CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
-               PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
-                               hwmgr, PPSMC_MSG_DisableAvfs),
-                               "Failed to disable AVFS!",
-                               return -EINVAL);
-
-       return 0;
-}
-
 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
                                         uint32_t virtual_addr_low,
                                         uint32_t virtual_addr_hi,
--
1.9.1

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