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* [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub
@ 2018-06-13 11:18 Rex Zhu
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

In order to keep consistent with powergate_uvd/vce.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h           | 4 ++--
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c           | 4 ++--
 drivers/gpu/drm/amd/include/kgd_pp_interface.h    | 2 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 8 ++++----
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         | 2 +-
 6 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 9acfbee..c6d6926 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -359,8 +359,8 @@ enum amdgpu_pcie_gen {
 		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
 			(adev)->powerplay.pp_handle, type, parameter, size))
 
-#define amdgpu_dpm_set_mmhub_powergating_by_smu(adev) \
-		((adev)->powerplay.pp_funcs->set_mmhub_powergating_by_smu( \
+#define amdgpu_dpm_powergate_mmhub(adev) \
+		((adev)->powerplay.pp_funcs->powergate_mmhub( \
 		(adev)->powerplay.pp_handle))
 
 struct amdgpu_dpm {
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 3d53c44..377f536 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 						RENG_EXECUTE_ON_REG_UPDATE, 1);
 		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 
-		if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu)
-			amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
+		if (adev->powerplay.pp_funcs->powergate_mmhub)
+			amdgpu_dpm_powergate_mmhub(adev);
 
 	} else {
 		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 06f08f3..0f98862 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -269,7 +269,7 @@ struct amd_pm_funcs {
 	int (*get_power_profile_mode)(void *handle, char *buf);
 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
-	int (*set_mmhub_powergating_by_smu)(void *handle);
+	int (*powergate_mmhub)(void *handle);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d567be4..da98208 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1168,19 +1168,19 @@ static int pp_get_display_mode_validation_clocks(void *handle,
 	return ret;
 }
 
-static int pp_set_mmhub_powergating_by_smu(void *handle)
+static int pp_dpm_powergate_mmhub(void *handle)
 {
 	struct pp_hwmgr *hwmgr = handle;
 
 	if (!hwmgr || !hwmgr->pm_en)
 		return -EINVAL;
 
-	if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu == NULL) {
+	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
 		pr_info("%s was not implemented.\n", __func__);
 		return 0;
 	}
 
-	return hwmgr->hwmgr_func->set_mmhub_powergating_by_smu(hwmgr);
+	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }
 
 static const struct amd_pm_funcs pp_dpm_funcs = {
@@ -1227,5 +1227,5 @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
 	.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
 	.display_clock_voltage_request = pp_display_clock_voltage_request,
 	.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
-	.set_mmhub_powergating_by_smu = pp_set_mmhub_powergating_by_smu,
+	.powergate_mmhub = pp_dpm_powergate_mmhub,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index d4bc83e..0f8352c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1126,7 +1126,7 @@ static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);
 }
 
-static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
+static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
 {
 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
 }
@@ -1182,7 +1182,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
 	.asic_setup = smu10_setup_asic_task,
 	.power_state_set = smu10_set_power_state_tasks,
 	.dynamic_state_management_disable = smu10_disable_dpm_tasks,
-	.set_mmhub_powergating_by_smu = smu10_set_mmhub_powergating_by_smu,
+	.powergate_mmhub = smu10_powergate_mmhub,
 	.smus_notify_pwe = smu10_smus_notify_pwe,
 	.gfx_off_control = smu10_gfx_off_control,
 	.display_clock_voltage_request = smu10_display_clock_voltage_request,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 40c98ca..9b07d6e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -327,7 +327,7 @@ struct pp_hwmgr_func {
 					enum PP_OD_DPM_TABLE_COMMAND type,
 					long *input, uint32_t size);
 	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
-	int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
+	int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
 	int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
 };
 
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-13 11:18   ` Rex Zhu
       [not found]     ` <1528888686-18896-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-06-13 11:18   ` [PATCH 3/7] drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu Rex Zhu
                     ` (5 subsequent siblings)
  6 siblings, 1 reply; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

keep consistent with powergate_uvd/vce/mmhub

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c               | 6 +++---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c            | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h                   | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index da98208..b69da11 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -236,13 +236,13 @@ static int pp_set_powergating_state(void *handle,
 			pr_err("gfx off control failed!\n");
 	}
 
-	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
-		pr_debug("%s was not implemented.\n", __func__);
+	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
+		pr_info("%s was not implemented.\n", __func__);
 		return 0;
 	}
 
 	/* Enable/disable GFX per cu powergating through SMU */
-	return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
+	return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
 			state == AMD_PG_STATE_GATE);
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 4149562..683b29a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -416,7 +416,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
  * Powerplay will only control the static per CU Power Gating.
  * Dynamic per CU Power Gating will be done in gfx.
  */
-int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
+int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
 {
 	struct amdgpu_device *adev = hwmgr->adev;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
index be7f66d..fc8f8a6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
@@ -33,6 +33,6 @@
 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
 					const uint32_t *msg_id);
-int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
+int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index b73e200..b4c93a9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5044,7 +5044,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
 	.get_fan_control_mode = smu7_get_fan_control_mode,
 	.force_clock_level = smu7_force_clock_level,
 	.print_clock_levels = smu7_print_clock_levels,
-	.enable_per_cu_power_gating = smu7_enable_per_cu_power_gating,
+	.powergate_gfx = smu7_powergate_gfx,
 	.get_sclk_od = smu7_get_sclk_od,
 	.set_sclk_od = smu7_set_sclk_od,
 	.get_mclk_od = smu7_get_mclk_od,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 9b07d6e..95e29a2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -302,7 +302,7 @@ struct pp_hwmgr_func {
 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
-	int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
+	int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
 	int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 	int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 	int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 3/7] drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-06-13 11:18   ` [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx Rex Zhu
@ 2018-06-13 11:18   ` Rex Zhu
  2018-06-13 11:18   ` [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu Rex Zhu
                     ` (4 subsequent siblings)
  6 siblings, 0 replies; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Some HW ip blocks need call SMU to enter/leave power gate state.
So export common set_powergating_by_smu interface.

1. keep consistent with set_clockgating_by_smu
2. scales easily to powergate other ip(gfx) if necessary

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h        | 14 ++++---------
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c         |  8 +++----
 drivers/gpu/drm/amd/amdgpu/ci_dpm.c            | 15 ++++++++++++-
 drivers/gpu/drm/amd/amdgpu/kv_dpm.c            | 15 ++++++++++++-
 drivers/gpu/drm/amd/include/kgd_pp_interface.h |  5 ++---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 29 +++++++++++++++++++++++---
 6 files changed, 64 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index c6d6926..ff24e1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
 #define amdgpu_dpm_force_performance_level(adev, l) \
 		((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
 
-#define amdgpu_dpm_powergate_uvd(adev, g) \
-		((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
-
-#define amdgpu_dpm_powergate_vce(adev, g) \
-		((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
-
 #define amdgpu_dpm_get_current_power_state(adev) \
 		((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
 
@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
 		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
 			(adev)->powerplay.pp_handle, msg_id))
 
+#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
+		((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
+			(adev)->powerplay.pp_handle, block_type, gate))
+
 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
 		((adev)->powerplay.pp_funcs->get_power_profile_mode(\
 			(adev)->powerplay.pp_handle, buf))
@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
 		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
 			(adev)->powerplay.pp_handle, type, parameter, size))
 
-#define amdgpu_dpm_powergate_mmhub(adev) \
-		((adev)->powerplay.pp_funcs->powergate_mmhub( \
-		(adev)->powerplay.pp_handle))
-
 struct amdgpu_dpm {
 	struct amdgpu_ps        *ps;
 	/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1c49103..90e84a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1668,10 +1668,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-	if (adev->powerplay.pp_funcs->powergate_uvd) {
+	if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
 		/* enable/disable UVD */
 		mutex_lock(&adev->pm.mutex);
-		amdgpu_dpm_powergate_uvd(adev, !enable);
+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
 		mutex_unlock(&adev->pm.mutex);
 	} else {
 		if (enable) {
@@ -1690,10 +1690,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-	if (adev->powerplay.pp_funcs->powergate_vce) {
+	if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
 		/* enable/disable VCE */
 		mutex_lock(&adev->pm.mutex);
-		amdgpu_dpm_powergate_vce(adev, !enable);
+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
 		mutex_unlock(&adev->pm.mutex);
 	} else {
 		if (enable) {
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index b6248c0..85b3f46 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6764,6 +6764,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
 	}
 }
 
+static int ci_set_powergating_by_smu(void *handle,
+				uint32_t block_type, bool gate)
+{
+	switch (block_type) {
+	case AMD_IP_BLOCK_TYPE_UVD:
+		ci_dpm_powergate_uvd(handle, gate);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
 static const struct amd_ip_funcs ci_dpm_ip_funcs = {
 	.name = "ci_dpm",
 	.early_init = ci_dpm_early_init,
@@ -6801,7 +6814,7 @@ static int ci_dpm_read_sensor(void *handle, int idx,
 	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
 	.force_performance_level = &ci_dpm_force_performance_level,
 	.vblank_too_short = &ci_dpm_vblank_too_short,
-	.powergate_uvd = &ci_dpm_powergate_uvd,
+	.set_powergating_by_smu = &ci_set_powergating_by_smu,
 	.set_fan_control_mode = &ci_dpm_set_fan_control_mode,
 	.get_fan_control_mode = &ci_dpm_get_fan_control_mode,
 	.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index d79e6f5..cee92f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3305,6 +3305,19 @@ static int kv_dpm_read_sensor(void *handle, int idx,
 	}
 }
 
+static int kv_set_powergating_by_smu(void *handle,
+				uint32_t block_type, bool gate)
+{
+	switch (block_type) {
+	case AMD_IP_BLOCK_TYPE_UVD:
+		kv_dpm_powergate_uvd(handle, gate);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
 static const struct amd_ip_funcs kv_dpm_ip_funcs = {
 	.name = "kv_dpm",
 	.early_init = kv_dpm_early_init,
@@ -3341,7 +3354,7 @@ static int kv_dpm_read_sensor(void *handle, int idx,
 	.print_power_state = &kv_dpm_print_power_state,
 	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
 	.force_performance_level = &kv_dpm_force_performance_level,
-	.powergate_uvd = &kv_dpm_powergate_uvd,
+	.set_powergating_by_smu = kv_set_powergating_by_smu,
 	.enable_bapm = &kv_dpm_enable_bapm,
 	.get_vce_clock_state = amdgpu_get_vce_clock_state,
 	.check_state_equal = kv_check_state_equal,
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 0f98862..4535756 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -232,13 +232,13 @@ struct amd_pm_funcs {
 	void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 	int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 /* export to amdgpu */
-	void (*powergate_uvd)(void *handle, bool gate);
-	void (*powergate_vce)(void *handle, bool gate);
 	struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 	int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 			enum amd_pm_state_type *user_state);
 	int (*load_firmware)(void *handle);
 	int (*wait_for_fw_loading_complete)(void *handle);
+	int (*set_powergating_by_smu)(void *handle,
+				uint32_t block_type, bool gate);
 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 	int (*set_power_limit)(void *handle, uint32_t n);
 	int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
@@ -269,7 +269,6 @@ struct amd_pm_funcs {
 	int (*get_power_profile_mode)(void *handle, char *buf);
 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
-	int (*powergate_mmhub)(void *handle);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b69da11..f68551f 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -244,6 +244,7 @@ static int pp_set_powergating_state(void *handle,
 	/* Enable/disable GFX per cu powergating through SMU */
 	return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
 			state == AMD_PG_STATE_GATE);
+
 }
 
 static int pp_suspend(void *handle)
@@ -1183,14 +1184,36 @@ static int pp_dpm_powergate_mmhub(void *handle)
 	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }
 
+static int pp_set_powergating_by_smu(void *handle,
+				uint32_t block_type, bool gate)
+{
+	int ret = 0;
+
+	switch (block_type) {
+	case AMD_IP_BLOCK_TYPE_UVD:
+	case AMD_IP_BLOCK_TYPE_VCN:
+		pp_dpm_powergate_uvd(handle, gate);
+		break;
+	case AMD_IP_BLOCK_TYPE_VCE:
+		pp_dpm_powergate_vce(handle, gate);
+		break;
+	case AMD_IP_BLOCK_TYPE_GMC:
+		pp_dpm_powergate_mmhub(handle);
+		break;
+	case AMD_IP_BLOCK_TYPE_GFX:
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
 	.load_firmware = pp_dpm_load_fw,
 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
 	.force_performance_level = pp_dpm_force_performance_level,
 	.get_performance_level = pp_dpm_get_performance_level,
 	.get_current_power_state = pp_dpm_get_current_power_state,
-	.powergate_vce = pp_dpm_powergate_vce,
-	.powergate_uvd = pp_dpm_powergate_uvd,
 	.dispatch_tasks = pp_dpm_dispatch_tasks,
 	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
 	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
@@ -1210,6 +1233,7 @@ static int pp_dpm_powergate_mmhub(void *handle)
 	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
 	.switch_power_profile = pp_dpm_switch_power_profile,
 	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
+	.set_powergating_by_smu = pp_set_powergating_by_smu,
 	.get_power_profile_mode = pp_get_power_profile_mode,
 	.set_power_profile_mode = pp_set_power_profile_mode,
 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
@@ -1227,5 +1251,4 @@ static int pp_dpm_powergate_mmhub(void *handle)
 	.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
 	.display_clock_voltage_request = pp_display_clock_voltage_request,
 	.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
-	.powergate_mmhub = pp_dpm_powergate_mmhub,
 };
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-06-13 11:18   ` [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx Rex Zhu
  2018-06-13 11:18   ` [PATCH 3/7] drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu Rex Zhu
@ 2018-06-13 11:18   ` Rex Zhu
       [not found]     ` <1528888686-18896-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-06-13 11:18   ` [PATCH 5/7] drm/amd/pp: Add powergate_gfx backend function on Raven Rex Zhu
                     ` (3 subsequent siblings)
  6 siblings, 1 reply; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

gfx ip block can call set_powergating_by_smu to set gfx pg state if
necessary.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 10 ++++------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  4 ++--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 ++++++++++++++++
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 807ee0d..916776a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5591,14 +5591,12 @@ static int gfx_v8_0_late_init(void *handle)
 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
 						       bool enable)
 {
-	if ((adev->asic_type == CHIP_POLARIS11) ||
+	if (((adev->asic_type == CHIP_POLARIS11) ||
 	    (adev->asic_type == CHIP_POLARIS12) ||
-	    (adev->asic_type == CHIP_VEGAM))
+	    (adev->asic_type == CHIP_VEGAM)) &&
+	    adev->powerplay.pp_funcs->set_powergating_by_smu)
 		/* Send msg to SMU via Powerplay */
-		amdgpu_device_ip_set_powergating_state(adev,
-						       AMD_IP_BLOCK_TYPE_SMC,
-						       enable ?
-						       AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
 
 	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 377f536..85cf2f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
 						RENG_EXECUTE_ON_REG_UPDATE, 1);
 		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 
-		if (adev->powerplay.pp_funcs->powergate_mmhub)
-			amdgpu_dpm_powergate_mmhub(adev);
+		if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, 0);
 
 	} else {
 		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f68551f..cb2dd7c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1184,6 +1184,21 @@ static int pp_dpm_powergate_mmhub(void *handle)
 	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }
 
+static int pp_dpm_powergate_gfx(void *handle, bool gate)
+{
+	struct pp_hwmgr *hwmgr = handle;
+
+	if (!hwmgr || !hwmgr->pm_en)
+		return 0;
+
+	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
+		pr_info("%s was not implemented.\n", __func__);
+		return 0;
+	}
+
+	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
+}
+
 static int pp_set_powergating_by_smu(void *handle,
 				uint32_t block_type, bool gate)
 {
@@ -1201,6 +1216,7 @@ static int pp_set_powergating_by_smu(void *handle,
 		pp_dpm_powergate_mmhub(handle);
 		break;
 	case AMD_IP_BLOCK_TYPE_GFX:
+		ret = pp_dpm_powergate_gfx(handle, gate);
 		break;
 	default:
 		break;
-- 
1.9.1

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 5/7] drm/amd/pp: Add powergate_gfx backend function on Raven
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2018-06-13 11:18   ` [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu Rex Zhu
@ 2018-06-13 11:18   ` Rex Zhu
  2018-06-13 11:18   ` [PATCH 6/7] drm/amdgpu: Change PG enable sequence Rex Zhu
                     ` (2 subsequent siblings)
  6 siblings, 0 replies; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Raven support gfx off feature instand of gfx powergate,
so use smu10_gfx_off_control as the powergate_gfx backend function.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 0f8352c..0bbf11d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1186,6 +1186,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
 	.smus_notify_pwe = smu10_smus_notify_pwe,
 	.gfx_off_control = smu10_gfx_off_control,
 	.display_clock_voltage_request = smu10_display_clock_voltage_request,
+	.powergate_gfx = smu10_gfx_off_control,
 };
 
 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 6/7] drm/amdgpu: Change PG enable sequence
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2018-06-13 11:18   ` [PATCH 5/7] drm/amd/pp: Add powergate_gfx backend function on Raven Rex Zhu
@ 2018-06-13 11:18   ` Rex Zhu
  2018-06-13 11:18   ` [PATCH 7/7] drm/amdgpu: Make gfx_off control by GFX ip Rex Zhu
  2018-06-20  2:03   ` [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub Quan, Evan
  6 siblings, 0 replies; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Enable PG state after CG enabled.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c      |  4 ----
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3adef57..5086f9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1746,6 +1746,34 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int amdgpu_device_ip_late_set_pg_state(struct amdgpu_device *adev)
+{
+	int i = 0, r;
+
+	if (amdgpu_emu_mode == 1)
+		return 0;
+
+	for (i = 0; i < adev->num_ip_blocks; i++) {
+		if (!adev->ip_blocks[i].status.valid)
+			continue;
+		/* skip CG for VCE/UVD, it's handled specially */
+		if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
+		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+		    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+		    adev->ip_blocks[i].version->funcs->set_powergating_state) {
+			/* enable powergating to save power */
+			r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+										     AMD_PG_STATE_GATE);
+			if (r) {
+				DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
+					  adev->ip_blocks[i].version->funcs->name, r);
+				return r;
+			}
+		}
+	}
+	return 0;
+}
+
 /**
  * amdgpu_device_ip_late_init - run late init for hardware IPs
  *
@@ -1903,6 +1931,7 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
 	struct amdgpu_device *adev =
 		container_of(work, struct amdgpu_device, late_init_work.work);
 	amdgpu_device_ip_late_set_cg_state(adev);
+	amdgpu_device_ip_late_set_pg_state(adev);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 916776a..2a860ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5581,10 +5581,6 @@ static int gfx_v8_0_late_init(void *handle)
 		return r;
 	}
 
-	amdgpu_device_ip_set_powergating_state(adev,
-					       AMD_IP_BLOCK_TYPE_GFX,
-					       AMD_PG_STATE_GATE);
-
 	return 0;
 }
 
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* [PATCH 7/7] drm/amdgpu: Make gfx_off control by GFX ip
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
                     ` (4 preceding siblings ...)
  2018-06-13 11:18   ` [PATCH 6/7] drm/amdgpu: Change PG enable sequence Rex Zhu
@ 2018-06-13 11:18   ` Rex Zhu
  2018-06-20  2:03   ` [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub Quan, Evan
  6 siblings, 0 replies; 10+ messages in thread
From: Rex Zhu @ 2018-06-13 11:18 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.

1. Delete the gfx pg/off ctrl code in pp_set_powergating_state
   this ip function is for smu pg enablement.
2. call set_powergating_by_smu to enable/disalbe power off feature.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 12 ++++++------
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c         |  4 ++++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 25 +------------------------
 3 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5086f9f..e50a053 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1842,6 +1842,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
 					  adev->ip_blocks[i].version->funcs->name, r);
 				return r;
 			}
+			if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+				amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
 			r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
 			/* XXX handle errors */
 			if (r) {
@@ -1952,12 +1954,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
 	if (amdgpu_sriov_vf(adev))
 		amdgpu_virt_request_full_gpu(adev, false);
 
-	/* ungate SMC block powergating */
-	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
-		amdgpu_device_ip_set_powergating_state(adev,
-						       AMD_IP_BLOCK_TYPE_SMC,
-						       AMD_CG_STATE_UNGATE);
-
 	/* ungate SMC block first */
 	r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
 						   AMD_CG_STATE_UNGATE);
@@ -1965,6 +1961,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
 		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
 	}
 
+	/* call smu to disable gfx off feature first when suspend */
+	if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
+
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae35bbe..bec5592 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3715,6 +3715,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
 
 		/* update mgcg state */
 		gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
+
+		/* set gfx off through smu */
+		if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
+			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
 		break;
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index cb2dd7c..387a1eb 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -221,30 +221,7 @@ static int pp_sw_reset(void *handle)
 static int pp_set_powergating_state(void *handle,
 				    enum amd_powergating_state state)
 {
-	struct amdgpu_device *adev = handle;
-	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
-	int ret;
-
-	if (!hwmgr || !hwmgr->pm_en)
-		return 0;
-
-	if (hwmgr->hwmgr_func->gfx_off_control) {
-		/* Enable/disable GFX off through SMU */
-		ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
-							 state == AMD_PG_STATE_GATE);
-		if (ret)
-			pr_err("gfx off control failed!\n");
-	}
-
-	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
-		pr_info("%s was not implemented.\n", __func__);
-		return 0;
-	}
-
-	/* Enable/disable GFX per cu powergating through SMU */
-	return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
-			state == AMD_PG_STATE_GATE);
-
+	return 0;
 }
 
 static int pp_suspend(void *handle)
-- 
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* Re: [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu
       [not found]     ` <1528888686-18896-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-13 15:10       ` Zhu, Rex
  0 siblings, 0 replies; 10+ messages in thread
From: Zhu, Rex @ 2018-06-13 15:10 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org


[-- Attachment #1.1: Type: text/plain, Size: 4950 bytes --]


-               if (adev->powerplay.pp_funcs->powergate_mmhub)
-                       amdgpu_dpm_powergate_mmhub(adev);
+               if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, 0);

Move this change to  patch3.


________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, June 13, 2018 7:18 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu

gfx ip block can call set_powergating_by_smu to set gfx pg state if
necessary.

Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c         | 10 ++++------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  4 ++--
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 16 ++++++++++++++++
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 807ee0d..916776a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5591,14 +5591,12 @@ static int gfx_v8_0_late_init(void *handle)
 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
                                                        bool enable)
 {
-       if ((adev->asic_type == CHIP_POLARIS11) ||
+       if (((adev->asic_type == CHIP_POLARIS11) ||
             (adev->asic_type == CHIP_POLARIS12) ||
-           (adev->asic_type == CHIP_VEGAM))
+           (adev->asic_type == CHIP_VEGAM)) &&
+           adev->powerplay.pp_funcs->set_powergating_by_smu)
                 /* Send msg to SMU via Powerplay */
-               amdgpu_device_ip_set_powergating_state(adev,
-                                                      AMD_IP_BLOCK_TYPE_SMC,
-                                                      enable ?
-                                                      AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);

         WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 377f536..85cf2f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
                                                 RENG_EXECUTE_ON_REG_UPDATE, 1);
                 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);

-               if (adev->powerplay.pp_funcs->powergate_mmhub)
-                       amdgpu_dpm_powergate_mmhub(adev);
+               if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, 0);

         } else {
                 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index f68551f..cb2dd7c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1184,6 +1184,21 @@ static int pp_dpm_powergate_mmhub(void *handle)
         return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }

+static int pp_dpm_powergate_gfx(void *handle, bool gate)
+{
+       struct pp_hwmgr *hwmgr = handle;
+
+       if (!hwmgr || !hwmgr->pm_en)
+               return 0;
+
+       if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
+               pr_info("%s was not implemented.\n", __func__);
+               return 0;
+       }
+
+       return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
+}
+
 static int pp_set_powergating_by_smu(void *handle,
                                 uint32_t block_type, bool gate)
 {
@@ -1201,6 +1216,7 @@ static int pp_set_powergating_by_smu(void *handle,
                 pp_dpm_powergate_mmhub(handle);
                 break;
         case AMD_IP_BLOCK_TYPE_GFX:
+               ret = pp_dpm_powergate_gfx(handle, gate);
                 break;
         default:
                 break;
--
1.9.1

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[-- Attachment #1.2: Type: text/html, Size: 13940 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread

* RE: [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub
       [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
                     ` (5 preceding siblings ...)
  2018-06-13 11:18   ` [PATCH 7/7] drm/amdgpu: Make gfx_off control by GFX ip Rex Zhu
@ 2018-06-20  2:03   ` Quan, Evan
  6 siblings, 0 replies; 10+ messages in thread
From: Quan, Evan @ 2018-06-20  2:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Zhu, Rex

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, June 13, 2018 7:18 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex <Rex.Zhu@amd.com>
> Subject: [PATCH 1/7] drm/amdgpu: Rename
> set_mmhub_powergating_by_smu to powergate_mmhub
> 
> In order to keep consistent with powergate_uvd/vce.
> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h           | 4 ++--
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c           | 4 ++--
>  drivers/gpu/drm/amd/include/kgd_pp_interface.h    | 2 +-
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c     | 8 ++++----
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         | 2 +-
>  6 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 9acfbee..c6d6926 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -359,8 +359,8 @@ enum amdgpu_pcie_gen {
>  		((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
>  			(adev)->powerplay.pp_handle, type, parameter,
> size))
> 
> -#define amdgpu_dpm_set_mmhub_powergating_by_smu(adev) \
> -		((adev)->powerplay.pp_funcs-
> >set_mmhub_powergating_by_smu( \
> +#define amdgpu_dpm_powergate_mmhub(adev) \
> +		((adev)->powerplay.pp_funcs->powergate_mmhub( \
>  		(adev)->powerplay.pp_handle))
> 
>  struct amdgpu_dpm {
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 3d53c44..377f536 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct
> amdgpu_device *adev,
> 
> 	RENG_EXECUTE_ON_REG_UPDATE, 1);
>  		WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE,
> pctl1_reng_execute);
> 
> -		if (adev->powerplay.pp_funcs-
> >set_mmhub_powergating_by_smu)
> -
> 	amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
> +		if (adev->powerplay.pp_funcs->powergate_mmhub)
> +			amdgpu_dpm_powergate_mmhub(adev);
> 
>  	} else {
>  		pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 06f08f3..0f98862 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -269,7 +269,7 @@ struct amd_pm_funcs {
>  	int (*get_power_profile_mode)(void *handle, char *buf);
>  	int (*set_power_profile_mode)(void *handle, long *input, uint32_t
> size);
>  	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input,
> uint32_t size);
> -	int (*set_mmhub_powergating_by_smu)(void *handle);
> +	int (*powergate_mmhub)(void *handle);
>  };
> 
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index d567be4..da98208 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1168,19 +1168,19 @@ static int
> pp_get_display_mode_validation_clocks(void *handle,
>  	return ret;
>  }
> 
> -static int pp_set_mmhub_powergating_by_smu(void *handle)
> +static int pp_dpm_powergate_mmhub(void *handle)
>  {
>  	struct pp_hwmgr *hwmgr = handle;
> 
>  	if (!hwmgr || !hwmgr->pm_en)
>  		return -EINVAL;
> 
> -	if (hwmgr->hwmgr_func->set_mmhub_powergating_by_smu ==
> NULL) {
> +	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
>  		pr_info("%s was not implemented.\n", __func__);
>  		return 0;
>  	}
> 
> -	return hwmgr->hwmgr_func-
> >set_mmhub_powergating_by_smu(hwmgr);
> +	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
>  }
> 
>  static const struct amd_pm_funcs pp_dpm_funcs = { @@ -1227,5 +1227,5
> @@ static int pp_set_mmhub_powergating_by_smu(void *handle)
>  	.set_watermarks_for_clocks_ranges =
> pp_set_watermarks_for_clocks_ranges,
>  	.display_clock_voltage_request = pp_display_clock_voltage_request,
>  	.get_display_mode_validation_clocks =
> pp_get_display_mode_validation_clocks,
> -	.set_mmhub_powergating_by_smu =
> pp_set_mmhub_powergating_by_smu,
> +	.powergate_mmhub = pp_dpm_powergate_mmhub,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index d4bc83e..0f8352c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1126,7 +1126,7 @@ static int smu10_smus_notify_pwe(struct
> pp_hwmgr *hwmgr)
>  	return smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_SetRccPfcPmeRestoreRegister);
>  }
> 
> -static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr
> *hwmgr)
> +static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
>  {
>  	return smum_send_msg_to_smc(hwmgr,
> PPSMC_MSG_PowerGateMmHub);  } @@ -1182,7 +1182,7 @@ static void
> smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
>  	.asic_setup = smu10_setup_asic_task,
>  	.power_state_set = smu10_set_power_state_tasks,
>  	.dynamic_state_management_disable = smu10_disable_dpm_tasks,
> -	.set_mmhub_powergating_by_smu =
> smu10_set_mmhub_powergating_by_smu,
> +	.powergate_mmhub = smu10_powergate_mmhub,
>  	.smus_notify_pwe = smu10_smus_notify_pwe,
>  	.gfx_off_control = smu10_gfx_off_control,
>  	.display_clock_voltage_request =
> smu10_display_clock_voltage_request,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 40c98ca..9b07d6e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -327,7 +327,7 @@ struct pp_hwmgr_func {
>  					enum
> PP_OD_DPM_TABLE_COMMAND type,
>  					long *input, uint32_t size);
>  	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
> -	int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr
> *hwmgr);
> +	int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
>  	int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);  };
> 
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread

* RE: [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx
       [not found]     ` <1528888686-18896-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-20  2:04       ` Quan, Evan
  0 siblings, 0 replies; 10+ messages in thread
From: Quan, Evan @ 2018-06-20  2:04 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Zhu, Rex

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, June 13, 2018 7:18 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex <Rex.Zhu@amd.com>
> Subject: [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating
> to powergate_gfx
> 
> keep consistent with powergate_uvd/vce/mmhub
> 
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c               | 6 +++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h | 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c            | 2 +-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h                   | 2 +-
>  5 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index da98208..b69da11 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -236,13 +236,13 @@ static int pp_set_powergating_state(void *handle,
>  			pr_err("gfx off control failed!\n");
>  	}
> 
> -	if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
> -		pr_debug("%s was not implemented.\n", __func__);
> +	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
> +		pr_info("%s was not implemented.\n", __func__);
>  		return 0;
>  	}
> 
>  	/* Enable/disable GFX per cu powergating through SMU */
> -	return hwmgr->hwmgr_func-
> >enable_per_cu_power_gating(hwmgr,
> +	return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
>  			state == AMD_PG_STATE_GATE);
>  }
> 
> diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> index 4149562..683b29a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
> @@ -416,7 +416,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr
> *hwmgr,
>   * Powerplay will only control the static per CU Power Gating.
>   * Dynamic per CU Power Gating will be done in gfx.
>   */
> -int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool
> enable)
> +int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
>  {
>  	struct amdgpu_device *adev = hwmgr->adev;
> 
> diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> index be7f66d..fc8f8a6 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h
> @@ -33,6 +33,6 @@
>  int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);  int
> smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
>  					const uint32_t *msg_id);
> -int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool
> enable);
> +int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
> 
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index b73e200..b4c93a9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5044,7 +5044,7 @@ static int smu7_set_power_profile_mode(struct
> pp_hwmgr *hwmgr, long *input, uint
>  	.get_fan_control_mode = smu7_get_fan_control_mode,
>  	.force_clock_level = smu7_force_clock_level,
>  	.print_clock_levels = smu7_print_clock_levels,
> -	.enable_per_cu_power_gating =
> smu7_enable_per_cu_power_gating,
> +	.powergate_gfx = smu7_powergate_gfx,
>  	.get_sclk_od = smu7_get_sclk_od,
>  	.set_sclk_od = smu7_set_sclk_od,
>  	.get_mclk_od = smu7_get_mclk_od,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 9b07d6e..95e29a2 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -302,7 +302,7 @@ struct pp_hwmgr_func {
>  	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
>  	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum
> pp_clock_type type, uint32_t mask);
>  	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum
> pp_clock_type type, char *buf);
> -	int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool
> enable);
> +	int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
>  	int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
>  	int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
>  	int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2018-06-20  2:04 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2018-06-13 11:18 [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub Rex Zhu
     [not found] ` <1528888686-18896-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-13 11:18   ` [PATCH 2/7] drm/amd/pp: Rename enable_per_cu_power_gating to powergate_gfx Rex Zhu
     [not found]     ` <1528888686-18896-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-20  2:04       ` Quan, Evan
2018-06-13 11:18   ` [PATCH 3/7] drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu Rex Zhu
2018-06-13 11:18   ` [PATCH 4/7] drm/amd/pp: Add gfx pg support in smu through set_powergating_by_smu Rex Zhu
     [not found]     ` <1528888686-18896-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-13 15:10       ` Zhu, Rex
2018-06-13 11:18   ` [PATCH 5/7] drm/amd/pp: Add powergate_gfx backend function on Raven Rex Zhu
2018-06-13 11:18   ` [PATCH 6/7] drm/amdgpu: Change PG enable sequence Rex Zhu
2018-06-13 11:18   ` [PATCH 7/7] drm/amdgpu: Make gfx_off control by GFX ip Rex Zhu
2018-06-20  2:03   ` [PATCH 1/7] drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhub Quan, Evan

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