* [PATCH 01/32] drm/amd/pm: add inst to dpm_set_vcn_enable
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 02/32] drm/amd/pm: power up or down vcn by instance boyuan.zhang
` (31 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add an instance parameter to the existing function dpm_set_vcn_enable()
for future implementation. Re-write all pptable functions accordingly.
v2: Remove duplicated dpm_set_vcn_enable() functions in v1. Instead,
adding instance parameter to existing functions.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 3 ++-
13 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5b0cdda96b38..6305fd7d2573 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -251,7 +251,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (atomic_read(&power_gate->vcn_gated) ^ enable)
return 0;
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff);
if (!ret)
atomic_set(&power_gate->vcn_gated, !enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 727da0c37e06..0f074b6c8b58 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -739,7 +739,7 @@ struct pptable_funcs {
* @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
* management.
*/
- int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
+ int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int inst);
/**
* @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index e58220a7ee2f..229b9d16452f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -255,7 +255,8 @@ int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
int smu_v13_0_set_vcn_enable(struct smu_context *smu,
- bool enable);
+ bool enable,
+ int inst);
int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 46b456590a08..c7071159f8ec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -210,7 +210,8 @@ int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
int smu_v14_0_set_vcn_enable(struct smu_context *smu,
- bool enable);
+ bool enable,
+ int inst);
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 5ad09323a29d..6c8e80f6b592 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1571,7 +1571,9 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 16af1a329621..29a3b96ffaec 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1135,7 +1135,9 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
return 0;
}
-static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int navi10_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3b29cb74c47b..2438f813d6db 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1152,7 +1152,9 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
return 0;
}
-static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
struct amdgpu_device *adev = smu->adev;
int i, ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 22737b11b1bf..656505d2404b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -459,7 +459,9 @@ static int vangogh_init_smc_tables(struct smu_context *smu)
return smu_v11_0_init_smc_tables(smu);
}
-static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int vangogh_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index cc0504b063fa..8d9fb80f36f7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -645,7 +645,9 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
return pm_type;
}
-static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int renoir_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index e17466cc1952..1d37b9e251d4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2088,7 +2088,8 @@ int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
}
int smu_v13_0_set_vcn_enable(struct smu_context *smu,
- bool enable)
+ bool enable,
+ int inst)
{
struct amdgpu_device *adev = smu->adev;
int i, ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index 9c2c43bfed0b..3204917f91bf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -193,7 +193,9 @@ static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
return ret;
}
-static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 260c339f89c5..0890951351f9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -220,7 +220,9 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
return ret;
}
-static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 865e916fc425..5e1165ecdf7b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -1492,7 +1492,8 @@ int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
}
int smu_v14_0_set_vcn_enable(struct smu_context *smu,
- bool enable)
+ bool enable,
+ int inst)
{
struct amdgpu_device *adev = smu->adev;
int i, ret = 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 02/32] drm/amd/pm: power up or down vcn by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 01/32] drm/amd/pm: add inst to dpm_set_vcn_enable boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable boyuan.zhang
` (30 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For smu ip with multiple vcn instances (smu 11/13/14), remove all the
for loop in dpm_set_vcn_enable() functions. And use the instance
argument to power up/down vcn for the given instance only, instead
of powering up/down for all vcn instances.
v2: remove all duplicated functions in v1.
remove for-loop from each ip, and temporarily move to dpm_set_vcn_enable,
in order to keep the exact same logic as before, until further separation
in the next patch.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 +++--
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 20 +++++------
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 16 ++++-----
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 35 ++++++++-----------
4 files changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 6305fd7d2573..246f81d73bd2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -237,6 +237,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
/*
@@ -251,9 +252,11 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (atomic_read(&power_gate->vcn_gated) ^ enable)
return 0;
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff);
- if (!ret)
- atomic_set(&power_gate->vcn_gated, !enable);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i);
+ if (ret)
+ return ret;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 2438f813d6db..f41d8fd09bce 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1157,19 +1157,15 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu,
int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* vcn dpm on is a prerequisite for vcn power gate messages */
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- 0x10000 * i, NULL);
- if (ret)
- return ret;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ 0x10000 * inst, NULL);
}
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 1d37b9e251d4..e57d4926250e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2092,18 +2092,14 @@ int smu_v13_0_set_vcn_enable(struct smu_context *smu,
int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- i << 16U, NULL);
- if (ret)
- return ret;
- }
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ inst << 16U, NULL);
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 5e1165ecdf7b..20822ac623c7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -1496,29 +1496,24 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- if (smu->is_apu) {
- if (i == 0)
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
- i << 16U, NULL);
- else if (i == 1)
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
- i << 16U, NULL);
- } else {
+ if (smu->is_apu) {
+ if (inst == 0)
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- i << 16U, NULL);
- }
-
- if (ret)
- return ret;
+ SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
+ inst << 16U, NULL);
+ else if (inst == 1)
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
+ inst << 16U, NULL);
+ } else {
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ inst << 16U, NULL);
}
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 01/32] drm/amd/pm: add inst to dpm_set_vcn_enable boyuan.zhang
2024-10-17 13:20 ` [PATCH 02/32] drm/amd/pm: power up or down vcn by instance boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 04/32] drm/amd/pm: add inst to set_powergating_by_smu boyuan.zhang
` (29 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
First, add an instance parameter to smu_dpm_set_vcn_enable() function,
and calling dpm_set_vcn_enable() with this given instance.
Second, modify vcn_gated to be an array, to track the gating status
for each vcn instance separately.
With these 2 changes, smu_dpm_set_vcn_enable() will check and set the
gating status for the given vcn instance ONLY.
v2: remove duplicated functions.
remove for-loop in dpm_set_vcn_enable(), and temporarily move it to
to smu_dpm_set_power_gate(), in order to keep the exact same logic as
before, until further separation in next patch.
v3: add instance number in error message.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 65 ++++++++++++-------
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
2 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 246f81d73bd2..639bc6d97b27 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -233,11 +233,11 @@ static bool is_vcn_enabled(struct amdgpu_device *adev)
}
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
- bool enable)
+ bool enable,
+ int inst)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- struct amdgpu_device *adev = smu->adev;
int ret = 0;
/*
@@ -249,14 +249,12 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (!smu->ppt_funcs->dpm_set_vcn_enable)
return 0;
- if (atomic_read(&power_gate->vcn_gated) ^ enable)
+ if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
return 0;
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i);
- if (ret)
- return ret;
- }
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
+ if (!ret)
+ atomic_set(&power_gate->vcn_gated[inst], !enable);
return ret;
}
@@ -358,6 +356,7 @@ static int smu_dpm_set_power_gate(void *handle,
bool gate)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
@@ -374,10 +373,12 @@ static int smu_dpm_set_power_gate(void *handle,
*/
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
- ret = smu_dpm_set_vcn_enable(smu, !gate);
- if (ret)
- dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
- gate ? "gate" : "ungate");
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, !gate, i);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
+ gate ? "gate" : "ungate", i);
+ }
break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
@@ -779,21 +780,25 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- int vcn_gate, jpeg_gate;
+ int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
int ret = 0;
if (!smu->ppt_funcs->set_default_dpm_table)
return 0;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- vcn_gate = atomic_read(&power_gate->vcn_gated);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
+ }
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
jpeg_gate = atomic_read(&power_gate->jpeg_gated);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
- ret = smu_dpm_set_vcn_enable(smu, true);
- if (ret)
- return ret;
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, true, i);
+ if (ret)
+ return ret;
+ }
}
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
@@ -810,8 +815,10 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
err_out:
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- smu_dpm_set_vcn_enable(smu, !vcn_gate);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, !vcn_gate[i], i);
+ }
return ret;
}
@@ -1256,7 +1263,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
- atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
@@ -1818,7 +1826,8 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block)
ret = smu_set_gfx_imu_enable(smu);
if (ret)
return ret;
- smu_dpm_set_vcn_enable(smu, true);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, true, i);
smu_dpm_set_jpeg_enable(smu, true);
smu_dpm_set_vpe_enable(smu, true);
smu_dpm_set_umsch_mm_enable(smu, true);
@@ -2021,7 +2030,8 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
- smu_dpm_set_vcn_enable(smu, false);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ smu_dpm_set_vcn_enable(smu, false, i);
smu_dpm_set_jpeg_enable(smu, false);
smu_dpm_set_vpe_enable(smu, false);
smu_dpm_set_umsch_mm_enable(smu, false);
@@ -2935,6 +2945,7 @@ static int smu_read_sensor(void *handle,
int *size_arg)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
int ret = 0;
@@ -2983,7 +2994,13 @@ static int smu_read_sensor(void *handle,
*size = 4;
break;
case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
- *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
+ *(uint32_t *)data = 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
+ *(uint32_t *)data = 1;
+ break;
+ }
+ }
*size = 4;
break;
case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 0f074b6c8b58..427441b469e0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -399,7 +399,7 @@ struct smu_dpm_context {
struct smu_power_gate {
bool uvd_gated;
bool vce_gated;
- atomic_t vcn_gated;
+ atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
atomic_t jpeg_gated;
atomic_t vpe_gated;
atomic_t umsch_mm_gated;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 04/32] drm/amd/pm: add inst to set_powergating_by_smu
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (2 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 05/32] drm/amd/pm: add inst to dpm_set_powergating_by_smu boyuan.zhang
` (28 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add an instance parameter to set_powergating_by_smu() function, and
re-write all amd_pm functions accordingly. Then use the instance to
call smu_dpm_set_vcn_enable().
v2: remove duplicated functions.
remove for-loop in smu_dpm_set_power_gate(), and temporarily move it to
to amdgpu_dpm_set_powergating_by_smu(), in order to keep the exact same
logic as before, until further separation in next patch.
v3: add instance number in error message.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 4 +++-
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 10 ++++++++--
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 +++-
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 14 ++++++--------
5 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 2fa71f68205e..f24bc61df9a7 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -405,7 +405,9 @@ struct amd_pm_funcs {
int (*load_firmware)(void *handle);
int (*wait_for_fw_loading_complete)(void *handle);
int (*set_powergating_by_smu)(void *handle,
- uint32_t block_type, bool gate);
+ uint32_t block_type,
+ bool gate,
+ int inst);
int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
int (*set_power_limit)(void *handle, uint32_t n);
int (*get_power_limit)(void *handle, uint32_t *limit,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 9dc82f4d7c93..bcedbeec082f 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -88,7 +88,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCE:
case AMD_IP_BLOCK_TYPE_GFX:
- case AMD_IP_BLOCK_TYPE_VCN:
case AMD_IP_BLOCK_TYPE_SDMA:
case AMD_IP_BLOCK_TYPE_JPEG:
case AMD_IP_BLOCK_TYPE_GMC:
@@ -96,7 +95,14 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
case AMD_IP_BLOCK_TYPE_VPE:
if (pp_funcs && pp_funcs->set_powergating_by_smu)
ret = (pp_funcs->set_powergating_by_smu(
- (adev)->powerplay.pp_handle, block_type, gate));
+ (adev)->powerplay.pp_handle, block_type, gate, 0));
+ break;
+ case AMD_IP_BLOCK_TYPE_VCN:
+ if (pp_funcs && pp_funcs->set_powergating_by_smu) {
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ ret = (pp_funcs->set_powergating_by_smu(
+ (adev)->powerplay.pp_handle, block_type, gate, i));
+ }
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 2cd6cb991f29..af7da780b58b 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3287,7 +3287,9 @@ static int kv_dpm_read_sensor(void *handle, int idx,
}
static int kv_set_powergating_by_smu(void *handle,
- uint32_t block_type, bool gate)
+ uint32_t block_type,
+ bool gate,
+ int inst)
{
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index f193c77cc141..de5ee1c5503f 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1241,7 +1241,9 @@ static void pp_dpm_powergate_sdma(void *handle, bool gate)
}
static int pp_set_powergating_by_smu(void *handle,
- uint32_t block_type, bool gate)
+ uint32_t block_type,
+ bool gate,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 639bc6d97b27..115931d1c461 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -353,10 +353,10 @@ static int smu_set_mall_enable(struct smu_context *smu)
*/
static int smu_dpm_set_power_gate(void *handle,
uint32_t block_type,
- bool gate)
+ bool gate,
+ int inst)
{
struct smu_context *smu = handle;
- struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
@@ -373,12 +373,10 @@ static int smu_dpm_set_power_gate(void *handle,
*/
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
- ret = smu_dpm_set_vcn_enable(smu, !gate, i);
- if (ret)
- dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
- gate ? "gate" : "ungate", i);
- }
+ ret = smu_dpm_set_vcn_enable(smu, !gate, inst);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VCN instance %d!\n",
+ gate ? "gate" : "ungate", inst);
break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 05/32] drm/amd/pm: add inst to dpm_set_powergating_by_smu
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (3 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 04/32] drm/amd/pm: add inst to set_powergating_by_smu boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 06/32] add inst to amdgpu_dpm_enable_vcn boyuan.zhang
` (27 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add an instance parameter to amdgpu_dpm_set_powergating_by_smu() function,
and use the instance to call set_powergating_by_smu().
v2: remove duplicated functions.
remove for-loop in amdgpu_dpm_set_powergating_by_smu(), and temporarily
move it to amdgpu_dpm_enable_vcn(), in order to keep the exact same logic
as before, until further separation in next patch.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 +-
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 51 +++++++++++++++++-----
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +-
16 files changed, 73 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 8e0725198dae..575826d220b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -140,7 +140,7 @@ static int acp_poweroff(struct generic_pm_domain *genpd)
* 2. power off the acp tiles
* 3. check and enter ulv state
*/
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
return 0;
}
@@ -157,7 +157,7 @@ static int acp_poweron(struct generic_pm_domain *genpd)
* 2. turn on acp clock
* 3. power on acp tiles
*/
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
return 0;
}
@@ -236,7 +236,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block)
ip_block->version->major, ip_block->version->minor);
/* -ENODEV means board uses AZ rather than ACP */
if (r == -ENODEV) {
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
return 0;
} else if (r) {
return r;
@@ -508,7 +508,7 @@ static int acp_hw_fini(struct amdgpu_ip_block *ip_block)
/* return early if no ACP */
if (!adev->acp.acp_genpd) {
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
return 0;
}
@@ -565,7 +565,7 @@ static int acp_suspend(struct amdgpu_ip_block *ip_block)
/* power up on suspend */
if (!adev->acp.acp_cell)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
return 0;
}
@@ -575,7 +575,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block)
/* power down again on resume */
if (!adev->acp.acp_cell)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
return 0;
}
@@ -606,7 +606,7 @@ static int acp_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_PG_STATE_GATE);
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 38a7423101f3..dbe4c26f63e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3425,7 +3425,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
WARN_ON_ONCE(adev->gfx.gfx_off_state);
WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
- if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
+ if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))
adev->gfx.gfx_off_state = true;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 2fe75c920a73..94ca2da07cec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -787,7 +787,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
/* If going to s2idle, no need to wait */
if (adev->in_s0ix) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
- AMD_IP_BLOCK_TYPE_GFX, true))
+ AMD_IP_BLOCK_TYPE_GFX, true, 0))
adev->gfx.gfx_off_state = true;
} else {
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
@@ -799,7 +799,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
if (adev->gfx.gfx_off_state &&
- !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
+ !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {
adev->gfx.gfx_off_state = false;
if (adev->gfx.funcs->init_spm_golden) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 88acf34e16fc..cb59ba3a6d1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5314,7 +5314,7 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
(adev->asic_type == CHIP_POLARIS12) ||
(adev->asic_type == CHIP_VEGAM))
/* Send msg to SMU via Powerplay */
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index e3ddd22aa172..21e66f81c5c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -307,7 +307,7 @@ static void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
if (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GMC,
- enable);
+ enable, 0);
}
static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index c1f98f6cf20d..3f5959557727 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1956,7 +1956,7 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
if (adev->flags & AMD_IS_APU)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
if (!amdgpu_sriov_vf(adev))
sdma_v4_0_init_golden_registers(adev);
@@ -1983,7 +1983,7 @@ static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
sdma_v4_0_enable(adev, false);
if (adev->flags & AMD_IS_APU)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 129c759772c2..746b3d282ca3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -303,7 +303,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
if (idle_work_unexecuted) {
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
}
r = vcn_v1_0_hw_fini(ip_block);
@@ -1856,7 +1856,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
if (fences == 0) {
amdgpu_gfx_off_ctrl(adev, true);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
@@ -1886,7 +1886,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
if (set_clocks) {
amdgpu_gfx_off_ctrl(adev, false);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 19bbd49f760e..d0c3895dcf6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -978,7 +978,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
int i, j, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
@@ -1235,7 +1235,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
power_off:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 30420ead7fc4..d4c062983bfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1013,7 +1013,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
int i, j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1486,7 +1486,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
}
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 13632c22d2f9..1da9a7dfb667 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1142,7 +1142,7 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
int i, j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1633,7 +1633,7 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
}
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e7b7a8150ea7..a04a64442809 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1089,7 +1089,7 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
int i, j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1615,7 +1615,7 @@ static int vcn_v4_0_stop(struct amdgpu_device *adev)
}
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 6dcae398b2dc..d433d2703995 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1092,7 +1092,7 @@ static int vcn_v4_0_3_start(struct amdgpu_device *adev)
uint32_t tmp;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
@@ -1366,7 +1366,7 @@ static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
}
Done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index edb9cd8390b6..133ebb3c14db 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1001,7 +1001,7 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev)
int i, j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1278,7 +1278,7 @@ static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
}
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 89bf29fa6f8d..c57894f1734a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -762,7 +762,7 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev)
int i, j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1009,7 +1009,7 @@ static int vcn_v5_0_0_stop(struct amdgpu_device *adev)
}
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index bcedbeec082f..8531e0993b17 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -70,13 +70,18 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
return ret;
}
-int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate)
+int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
+ uint32_t block_type,
+ bool gate,
+ int inst)
{
int ret = 0;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
+ bool is_vcn = (block_type == AMD_IP_BLOCK_TYPE_UVD || block_type == AMD_IP_BLOCK_TYPE_VCN);
- if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
+ if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
+ (!is_vcn || adev->vcn.num_vcn_inst == 1)) {
dev_dbg(adev->dev, "IP block%d already in the target %s state!",
block_type, gate ? "gate" : "ungate");
return 0;
@@ -98,11 +103,9 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
(adev)->powerplay.pp_handle, block_type, gate, 0));
break;
case AMD_IP_BLOCK_TYPE_VCN:
- if (pp_funcs && pp_funcs->set_powergating_by_smu) {
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
- ret = (pp_funcs->set_powergating_by_smu(
- (adev)->powerplay.pp_handle, block_type, gate, i));
- }
+ if (pp_funcs && pp_funcs->set_powergating_by_smu)
+ ret = (pp_funcs->set_powergating_by_smu(
+ (adev)->powerplay.pp_handle, block_type, gate, inst));
break;
default:
break;
@@ -572,12 +575,38 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
return;
}
- ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);
if (ret)
DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
enable ? "enable" : "disable", ret);
}
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable)
+{
+ int ret = 0;
+
+ if (adev->family == AMDGPU_FAMILY_SI) {
+ mutex_lock(&adev->pm.mutex);
+ if (enable) {
+ adev->pm.dpm.uvd_active = true;
+ adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
+ } else {
+ adev->pm.dpm.uvd_active = false;
+ }
+ mutex_unlock(&adev->pm.mutex);
+
+ amdgpu_dpm_compute_clocks(adev);
+ return;
+ }
+
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, i);
+ if (ret)
+ DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
+ enable ? "enable" : "disable", ret);
+ }
+}
+
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
@@ -597,7 +626,7 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
return;
}
- ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);
if (ret)
DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
enable ? "enable" : "disable", ret);
@@ -607,7 +636,7 @@ void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
- ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);
if (ret)
DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
enable ? "enable" : "disable", ret);
@@ -617,7 +646,7 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
- ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable);
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);
if (ret)
DRM_ERROR("Dpm %s vpe failed, ret = %d.\n",
enable ? "enable" : "disable", ret);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index f5bf41f21c41..e7c84d4a431a 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -393,7 +393,7 @@ int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit
int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
- uint32_t block_type, bool gate);
+ uint32_t block_type, bool gate, int inst);
extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
@@ -442,6 +442,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 06/32] add inst to amdgpu_dpm_enable_vcn
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (4 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 05/32] drm/amd/pm: add inst to dpm_set_powergating_by_smu boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
` (26 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add an instance parameter to amdgpu_dpm_enable_vcn() function, and change
all calls from vcn ip functions to add instance argument. vcn generations
with only one instance (v1.0, v2.0) always use 0 as instance number. vcn
generations with multiple instances (v2.5, v3.0, v4.0, v4.0.3, v4.0.5,
v5.0.0) use the actual instance number.
v2: remove for-loop in amdgpu_dpm_enable_vcn(), and temporarily move it
to vcn ip with multiple instances, in order to keep the exact same logic
as before, until further separation in next patch.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 12 ++++++++----
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 12 ++++++++----
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 12 +++++-------
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 +-
10 files changed, 59 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 746b3d282ca3..1d5b0f4e5b1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -303,7 +303,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
if (idle_work_unexecuted) {
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
}
r = vcn_v1_0_hw_fini(ip_block);
@@ -1856,7 +1856,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
if (fences == 0) {
amdgpu_gfx_off_ctrl(adev, true);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
@@ -1886,7 +1886,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
if (set_clocks) {
amdgpu_gfx_off_ctrl(adev, false);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 0);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index d0c3895dcf6b..d87e5505cf51 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -978,7 +978,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
int i, j, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 0);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
@@ -1235,7 +1235,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
power_off:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index d4c062983bfe..ad0922eb16c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1012,8 +1012,10 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
uint32_t rb_bufsz, tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1485,8 +1487,10 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 1da9a7dfb667..19c7f9cd4c15 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -1141,8 +1141,10 @@ static int vcn_v3_0_start(struct amdgpu_device *adev)
uint32_t rb_bufsz, tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1632,8 +1634,10 @@ static int vcn_v3_0_stop(struct amdgpu_device *adev)
vcn_v3_0_enable_static_power_gating(adev, i);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index a04a64442809..e97d7f4ae371 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1088,8 +1088,10 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
uint32_t tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1614,8 +1616,10 @@ static int vcn_v4_0_stop(struct amdgpu_device *adev)
vcn_v4_0_enable_static_power_gating(adev, i);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index d433d2703995..ba22913398ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1091,8 +1091,10 @@ static int vcn_v4_0_3_start(struct amdgpu_device *adev)
int i, j, k, r, vcn_inst;
uint32_t tmp;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
@@ -1365,8 +1367,10 @@ static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
vcn_v4_0_3_enable_clock_gating(adev, i);
}
Done:
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 133ebb3c14db..873672f64778 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1000,8 +1000,10 @@ static int vcn_v4_0_5_start(struct amdgpu_device *adev)
uint32_t tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1277,8 +1279,10 @@ static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
vcn_v4_0_5_enable_static_power_gating(adev, i);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index c57894f1734a..893e66c2b9a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -761,8 +761,10 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev)
uint32_t tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1008,8 +1010,10 @@ static int vcn_v5_0_0_stop(struct amdgpu_device *adev)
vcn_v5_0_0_enable_static_power_gating(adev, i);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 8531e0993b17..5a9006bfc3cd 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -581,7 +581,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
enable ? "enable" : "disable", ret);
}
-void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable)
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
{
int ret = 0;
@@ -599,12 +599,10 @@ void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable)
return;
}
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
- ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, i);
- if (ret)
- DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
- enable ? "enable" : "disable", ret);
- }
+ ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst);
+ if (ret)
+ DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
+ enable ? "enable" : "disable", ret);
}
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index e7c84d4a431a..251b389dcf6e 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -442,7 +442,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
-void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (5 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 06/32] add inst to amdgpu_dpm_enable_vcn boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-22 7:42 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state boyuan.zhang
` (25 subsequent siblings)
32 siblings, 1 reply; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass ip_block instead of adev in set_powergating_state callback function.
Modify set_powergating_state ip functions for all correspoding ip blocks.
v2: fix a ip block index error.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 ++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 13 +++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
82 files changed, 165 insertions(+), 157 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 575826d220b8..64828cb7c2f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -600,10 +600,10 @@ static int acp_set_clockgating_state(void *handle,
return 0;
}
-static int acp_set_powergating_state(void *handle,
+static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index b545940e512b..dd3ae5d74436 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -724,7 +724,10 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
/* Disable GFXOFF and PG. Temporary workaround
* to fix some compute applications issue on GFX9.
*/
- adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state);
+ for (int i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
+ adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i], state);
+ }
}
amdgpu_dpm_switch_power_profile(adev,
PP_SMC_POWER_PROFILE_COMPUTE,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index dbe4c26f63e6..fe5de35eef64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
continue;
r = adev->ip_blocks[i].version->funcs->set_powergating_state(
- (void *)adev, state);
+ (void *)&adev->ip_blocks[i], state);
if (r)
DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
@@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */
- r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+ r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i],
state);
if (r) {
DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
index adc0b80ca5db..844f71eeea27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
@@ -164,7 +164,7 @@ static int isp_set_clockgating_state(void *handle,
return 0;
}
-static int isp_set_powergating_state(void *handle,
+static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8ef6bf7c6b65..527470323c33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
return 0;
}
-static int psp_set_powergating_state(void *handle,
+static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index fd31e2e9feb9..f44ce5edba6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -647,7 +647,7 @@ static int amdgpu_vkms_set_clockgating_state(void *handle,
return 0;
}
-static int amdgpu_vkms_set_powergating_state(void *handle,
+static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index 6d96e1f21e20..f3a9ea3f6044 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -644,10 +644,10 @@ static int vpe_set_clockgating_state(void *handle,
return 0;
}
-static int vpe_set_powergating_state(void *handle,
+static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_vpe *vpe = &adev->vpe;
if (!adev->pm.dpm_enabled)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6c18ab35cf69..08b398aa6c6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2185,7 +2185,7 @@ static int cik_common_set_clockgating_state(void *handle,
return 0;
}
-static int cik_common_set_powergating_state(void *handle,
+static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 9e9a58fd86ce..42c3eb8b6a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -408,7 +408,7 @@ static int cik_ih_set_clockgating_state(void *handle,
return 0;
}
-static int cik_ih_set_powergating_state(void *handle,
+static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index df3f429e003e..5283b0e94f02 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1204,7 +1204,7 @@ static int cik_sdma_set_clockgating_state(void *handle,
return 0;
}
-static int cik_sdma_set_powergating_state(void *handle,
+static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index cadd69a243af..4bf5402bd3aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -405,7 +405,7 @@ static int cz_ih_set_clockgating_state(void *handle,
return 0;
}
-static int cz_ih_set_powergating_state(void *handle,
+static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
// TODO
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 2d0a24a343f7..e7505934cce2 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v10_0_set_powergating_state(void *handle,
+static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 386ece7bc389..8adee675f4d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v11_0_set_powergating_state(void *handle,
+static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index cd3e0118988d..66cb19f9b073 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v6_0_set_powergating_state(void *handle,
+static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 295bc1d47095..57a5207b4e76 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v8_0_set_powergating_state(void *handle,
+static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bf5c739c7058..b5da9a1e8216 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3673,7 +3673,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
unsigned int vmid);
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
{
@@ -7451,7 +7451,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
* otherwise the gfxoff disallowing will be failed to set.
*/
if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
- gfx_v10_0_set_powergating_state(ip_block->adev, AMD_PG_STATE_UNGATE);
+ gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
if (!adev->no_hw_access) {
if (amdgpu_async_gfx_ring) {
@@ -8339,10 +8339,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
};
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index c78a63da8d2e..92786e3bbf0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5424,10 +5424,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
}
-static int gfx_v11_0_set_powergating_state(void *handle,
+static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index dc25fcb89b13..4ff78c9e3e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
}
#endif
-static int gfx_v12_0_set_powergating_state(void *handle,
+static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 6ac6d4dfa49f..429aa895d6bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3400,11 +3400,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int gfx_v6_0_set_powergating_state(void *handle,
+static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 77150c9f1e18..7c04dccec8d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4869,11 +4869,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int gfx_v7_0_set_powergating_state(void *handle,
+static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index cb59ba3a6d1b..22ada2ede46b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5360,10 +5360,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
}
}
-static int gfx_v8_0_set_powergating_state(void *handle,
+static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d85b2968a7cf..6516e88c55aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
};
-static int gfx_v9_0_set_powergating_state(void *handle,
+static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 7d425d2e7ab0..627652cab308 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
.is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
};
-static int gfx_v9_4_3_set_powergating_state(void *handle,
+static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5cf2002fcba8..b398021d5b90 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1133,7 +1133,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
athub_v2_0_get_clockgating(adev, flags);
}
-static int gmc_v10_0_set_powergating_state(void *handle,
+static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 4df4d73038f8..36e2f4e5a865 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -1020,7 +1020,7 @@ static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
athub_v3_0_get_clockgating(adev, flags);
}
-static int gmc_v11_0_set_powergating_state(void *handle,
+static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index e33f9e9058cc..c6510f12afb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -1004,7 +1004,7 @@ static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
athub_v4_1_0_get_clockgating(adev, flags);
}
-static int gmc_v12_0_set_powergating_state(void *handle,
+static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c1e2f1d79e74..3965b9ca8e9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1100,7 +1100,7 @@ static int gmc_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v6_0_set_powergating_state(void *handle,
+static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 54a48662f3b5..b43eaa42e5c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1327,7 +1327,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v7_0_set_powergating_state(void *handle,
+static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index c4f2ad32c078..d36cf90d4133 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1679,7 +1679,7 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v8_0_set_powergating_state(void *handle,
+static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 94600e5c8ea3..5aac51d9db2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2485,7 +2485,7 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
athub_v1_0_get_clockgating(adev, flags);
}
-static int gmc_v9_0_set_powergating_state(void *handle,
+static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index a3fb01f905d4..879d34e88014 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -398,7 +398,7 @@ static int iceland_ih_set_clockgating_state(void *handle,
return 0;
}
-static int iceland_ih_set_powergating_state(void *handle,
+static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 09403eac483b..4f271d9f43ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -756,10 +756,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v6_0_set_powergating_state(void *handle,
+static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 9706d7593d26..5b0a1eaa1fd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -737,10 +737,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v6_1_set_powergating_state(void *handle,
+static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 9657145d7cce..a584863f1bed 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -727,10 +727,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v7_0_set_powergating_state(void *handle,
+static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 6762b5c64ccb..c5f692a45bee 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -35,7 +35,7 @@
static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
- jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -692,10 +692,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 4b8c801f204d..f1ddef8e60ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -38,7 +38,7 @@
static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
@@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
- jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
@@ -541,10 +541,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 7996209818b6..69f0a9006b96 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -36,7 +36,7 @@
static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
- jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -483,10 +483,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if(state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 20e1fe89c463..e304108d7024 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -39,7 +39,7 @@
static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
@@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
- jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
@@ -645,10 +645,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 2a53537db135..f4d6a4768ee2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -43,7 +43,7 @@ enum jpeg_engin_status {
static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
- ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
return ret;
@@ -960,10 +960,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index ef2d4237925b..2a28eb479a34 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -48,7 +48,7 @@
static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
- jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
return 0;
@@ -676,10 +676,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 7954a6fae464..692d0083b5f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -36,7 +36,7 @@
static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
- jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -570,10 +570,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 93da900b7ee2..9ca248ea3428 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -677,7 +677,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
return 0;
}
-static int navi10_ih_set_powergating_state(void *handle,
+static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4e8f9af1e2be..6481f72b32d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1085,7 +1085,7 @@ static int nv_common_set_clockgating_state(void *handle,
return 0;
}
-static int nv_common_set_powergating_state(void *handle,
+static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* TODO */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 10fd772cb80f..6a1028baf16d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1087,7 +1087,7 @@ static int sdma_v2_4_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v2_4_set_powergating_state(void *handle,
+static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 69fba087e09c..42d996d4136f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1506,7 +1506,7 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v3_0_set_powergating_state(void *handle,
+static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3f5959557727..a2f5f2be699b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2312,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v4_0_set_powergating_state(void *handle,
+static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
case IP_VERSION(4, 1, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 9c7cea0890c9..95d5de2bd186 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1830,7 +1830,7 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v4_4_2_set_powergating_state(void *handle,
+static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 6a675daf5620..82a8bbd53d49 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1859,7 +1859,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v5_0_set_powergating_state(void *handle,
+static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index e1413ccaf7e4..b84d5c27bb94 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1818,7 +1818,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v5_2_set_powergating_state(void *handle,
+static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 4b33bd6b776d..bc9fe03ab145 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1589,7 +1589,7 @@ static int sdma_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v6_0_set_powergating_state(void *handle,
+static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 24f24974ac1d..c224e7e7e103 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1524,7 +1524,7 @@ static int sdma_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v7_0_set_powergating_state(void *handle,
+static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index b9934661a92e..6b0211c94836 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2681,7 +2681,7 @@ static int si_common_set_clockgating_state(void *handle,
return 0;
}
-static int si_common_set_powergating_state(void *handle,
+static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index d44483ed3363..26782dad9311 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -672,12 +672,12 @@ static int si_dma_set_clockgating_state(void *handle,
return 0;
}
-static int si_dma_set_powergating_state(void *handle,
+static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
u32 tmp;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
WREG32(DMA_PGFSM_WRITE, 0x00002000);
WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index b018a3b90401..976d803bef8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -269,7 +269,7 @@ static int si_ih_set_clockgating_state(void *handle,
return 0;
}
-static int si_ih_set_powergating_state(void *handle,
+static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6ab34c526c86..9fbada694cd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1481,7 +1481,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
adev->df.funcs->get_clockgating_state(adev, flags);
}
-static int soc15_common_set_powergating_state(void *handle,
+static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* todo */
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index c4b950e75133..6497a65f9738 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -968,10 +968,10 @@ static int soc21_common_set_clockgating_state(void *handle,
return 0;
}
-static int soc21_common_set_powergating_state(void *handle,
+static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
case IP_VERSION(6, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index b20dc81dc257..7b43d8908448 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -557,10 +557,10 @@ static int soc24_common_set_clockgating_state(void *handle,
return 0;
}
-static int soc24_common_set_powergating_state(void *handle,
+static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
case IP_VERSION(7, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 45fb5140c8b7..77fba40e1dbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -454,7 +454,7 @@ static int tonga_ih_set_clockgating_state(void *handle,
return 0;
}
-static int tonga_ih_set_powergating_state(void *handle,
+static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 3011b5853fb4..561fc15173b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -796,7 +796,7 @@ static int uvd_v3_1_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v3_1_set_powergating_state(void *handle,
+static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 4852a2ab128f..6bd728153b4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -714,7 +714,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v4_2_set_powergating_state(void *handle,
+static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -724,7 +724,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE) {
uvd_v4_2_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index a24b210c79ac..02e0e5c9e701 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -817,7 +817,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v5_0_set_powergating_state(void *handle,
+static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -827,7 +827,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == AMD_PG_STATE_GATE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index b4eeeebfe095..fdf23d2b0e42 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1476,7 +1476,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v6_0_set_powergating_state(void *handle,
+static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -1486,7 +1486,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index a4531000ec0b..836643c99572 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -596,7 +596,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,
return 0;
}
-static int vce_v2_0_set_powergating_state(void *handle,
+static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -606,7 +606,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
return vce_v2_0_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 9f9a9d89bcdc..e985cf1e63f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -801,7 +801,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int vce_v3_0_set_powergating_state(void *handle,
+static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -811,7 +811,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == AMD_PG_STATE_GATE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index f4d2650e6b7a..30d64672f3c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
}
#endif
-static int vce_v4_0_set_powergating_state(void *handle,
+static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
return vce_v4_0_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1d5b0f4e5b1a..34b1e55a907a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state);
static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
- vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
return 0;
@@ -1799,7 +1800,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
}
}
-static int vcn_v1_0_set_powergating_state(void *handle,
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCN block.
@@ -1810,7 +1811,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
int ret;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == adev->vcn.cur_state)
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index d87e5505cf51..6c1f5d05f90a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
- vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -1796,7 +1796,7 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
}
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCN block.
@@ -1807,7 +1807,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
int ret;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index ad0922eb16c0..35ded346771d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -398,8 +398,9 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
- vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+ vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
+ }
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
@@ -1825,10 +1826,10 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
return 0;
}
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 19c7f9cd4c15..c02c9ef8ddeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -430,9 +430,9 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
- vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+ vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -2159,10 +2159,10 @@ static int vcn_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e97d7f4ae371..319eb5a3d061 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_set_powergating_state(void *handle,
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -357,9 +357,9 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
continue;
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, regUVD_STATUS))) {
+ vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_sta
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index ba22913398ec..b6c1135d6fec 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -319,7 +319,7 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
- vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -1623,10 +1623,10 @@ static int vcn_v4_0_3_set_clockgating_state(void *handle,
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 873672f64778..ebf6301b13be 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_5_set_powergating_state(void *handle,
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -309,7 +309,7 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -1531,9 +1531,10 @@ static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->vcn.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 893e66c2b9a5..50c102f1b5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v5_0_0_set_powergating_state(void *handle,
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -273,7 +273,7 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -1258,9 +1258,10 @@ static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
*
* Set VCN block powergating state
*/
-static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->vcn.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 73de5909f655..8df4f4352d65 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -616,7 +616,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
}
-static int vega10_ih_set_powergating_state(void *handle,
+static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index a42404a58015..4ac43aeb85c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -681,7 +681,7 @@ static int vega20_ih_set_clockgating_state(void *handle,
}
-static int vega20_ih_set_powergating_state(void *handle,
+static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 4996049dc199..6b58723f0b2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -2003,7 +2003,7 @@ static int vi_common_set_clockgating_state(void *handle,
return 0;
}
-static int vi_common_set_powergating_state(void *handle,
+static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7616d7a509b9..d5a0417f95df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
return 0;
}
-static int dm_set_powergating_state(void *handle,
+static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index f98b3a544477..03c77bbc2e6d 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -398,7 +398,7 @@ struct amd_ip_funcs {
int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*set_clockgating_state)(void *handle,
enum amd_clockgating_state state);
- int (*set_powergating_state)(void *handle,
+ int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
void (*get_clockgating_state)(void *handle, u64 *flags);
void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index af7da780b58b..d5130da88162 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void *handle,
return 0;
}
-static int kv_dpm_set_powergating_state(void *handle,
+static int kv_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index a4908f0402f1..18c47fa89bc1 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void *handle,
return 0;
}
-static int si_dpm_set_powergating_state(void *handle,
+static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index de5ee1c5503f..069b604d6e7a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -254,7 +254,7 @@ static int pp_sw_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int pp_set_powergating_state(void *handle,
+static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 115931d1c461..4aaaf0e0b851 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2184,7 +2184,7 @@ static int smu_set_clockgating_state(void *handle,
return 0;
}
-static int smu_set_powergating_state(void *handle,
+static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-17 13:20 ` [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
@ 2024-10-22 7:42 ` Khatri, Sunil
2024-10-25 2:46 ` Boyuan Zhang
0 siblings, 1 reply; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 7:42 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Pass ip_block instead of adev in set_powergating_state callback function.
> Modify set_powergating_state ip functions for all correspoding ip blocks.
>
> v2: fix a ip block index error.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> Suggested-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 ++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 13 +++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
> 82 files changed, 165 insertions(+), 157 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 575826d220b8..64828cb7c2f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -600,10 +600,10 @@ static int acp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int acp_set_powergating_state(void *handle,
> +static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index b545940e512b..dd3ae5d74436 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -724,7 +724,10 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
> /* Disable GFXOFF and PG. Temporary workaround
> * to fix some compute applications issue on GFX9.
> */
> - adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state);
We have the function for this requirement and i feel better use this
amdgpu_device_ip_get_ip_block
> + for (int i = 0; i < adev->num_ip_blocks; i++) {
> + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX)
> + adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i], state);
> + }
> }
> amdgpu_dpm_switch_power_profile(adev,
> PP_SMC_POWER_PROFILE_COMPUTE,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index dbe4c26f63e6..fe5de35eef64 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
> if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
> continue;
> r = adev->ip_blocks[i].version->funcs->set_powergating_state(
> - (void *)adev, state);
> + (void *)&adev->ip_blocks[i], state);
> We dont need type casting anymore by void * as we already have ip_block type ptr also valid at other places too and probably in other patches
> if (r)
> DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
> adev->ip_blocks[i].version->funcs->name, r);
> @@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
> adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
> adev->ip_blocks[i].version->funcs->set_powergating_state) {
> /* enable powergating to save power */
> - r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
> + r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i],
> state);
> Typecasting not needed.
> if (r) {
> DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> index adc0b80ca5db..844f71eeea27 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> @@ -164,7 +164,7 @@ static int isp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int isp_set_powergating_state(void *handle,
> +static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 8ef6bf7c6b65..527470323c33 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int psp_set_powergating_state(void *handle,
> +static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index fd31e2e9feb9..f44ce5edba6a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -647,7 +647,7 @@ static int amdgpu_vkms_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int amdgpu_vkms_set_powergating_state(void *handle,
> +static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> index 6d96e1f21e20..f3a9ea3f6044 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> @@ -644,10 +644,10 @@ static int vpe_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vpe_set_powergating_state(void *handle,
> +static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> struct amdgpu_vpe *vpe = &adev->vpe;
>
> if (!adev->pm.dpm_enabled)
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 6c18ab35cf69..08b398aa6c6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2185,7 +2185,7 @@ static int cik_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cik_common_set_powergating_state(void *handle,
> +static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 9e9a58fd86ce..42c3eb8b6a95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -408,7 +408,7 @@ static int cik_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> Function could be remove in another patch as this isnt doing anything by checking if the fuction is NULL or not.
> -static int cik_ih_set_powergating_state(void *handle,
> +static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index df3f429e003e..5283b0e94f02 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1204,7 +1204,7 @@ static int cik_sdma_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cik_sdma_set_powergating_state(void *handle,
> +static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index cadd69a243af..4bf5402bd3aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -405,7 +405,7 @@ static int cz_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cz_ih_set_powergating_state(void *handle,
> +static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> // TODO
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 2d0a24a343f7..e7505934cce2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void *handle,
> return 0;
> }
Clean up in a different patch as it returns 0 and all other functions
which return 0 in one separate patch.
>
> -static int dce_v10_0_set_powergating_state(void *handle,
> +static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 386ece7bc389..8adee675f4d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void *handle,
> return 0;
> }
> Same as above and please follow the clean up in one patch for a particular function for all files can take reference of any other function that i pushed as that code is merged.
>
> -static int dce_v11_0_set_powergating_state(void *handle,
> +static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index cd3e0118988d..66cb19f9b073 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v6_0_set_powergating_state(void *handle,
> +static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 295bc1d47095..57a5207b4e76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v8_0_set_powergating_state(void *handle,
> +static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bf5c739c7058..b5da9a1e8216 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3673,7 +3673,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> unsigned int vmid);
>
> -static int gfx_v10_0_set_powergating_state(void *handle,
> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
> {
> @@ -7451,7 +7451,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
> * otherwise the gfxoff disallowing will be failed to set.
> */
> if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
> - gfx_v10_0_set_powergating_state(ip_block->adev, AMD_PG_STATE_UNGATE);
> + gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
>
> if (!adev->no_hw_access) {
> if (amdgpu_async_gfx_ring) {
> @@ -8339,10 +8339,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
> .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
> };
>
> -static int gfx_v10_0_set_powergating_state(void *handle,
> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index c78a63da8d2e..92786e3bbf0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -5424,10 +5424,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> -static int gfx_v11_0_set_powergating_state(void *handle,
> +static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index dc25fcb89b13..4ff78c9e3e43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
> }
> #endif
>
> -static int gfx_v12_0_set_powergating_state(void *handle,
> +static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 6ac6d4dfa49f..429aa895d6bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3400,11 +3400,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gfx_v6_0_set_powergating_state(void *handle,
> +static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 77150c9f1e18..7c04dccec8d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4869,11 +4869,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gfx_v7_0_set_powergating_state(void *handle,
> +static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index cb59ba3a6d1b..22ada2ede46b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5360,10 +5360,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
> }
> }
>
> -static int gfx_v8_0_set_powergating_state(void *handle,
> +static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index d85b2968a7cf..6516e88c55aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
> .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
> };
>
> -static int gfx_v9_0_set_powergating_state(void *handle,
> +static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 7d425d2e7ab0..627652cab308 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
> .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
> };
>
> -static int gfx_v9_4_3_set_powergating_state(void *handle,
> +static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 5cf2002fcba8..b398021d5b90 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -1133,7 +1133,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v2_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v10_0_set_powergating_state(void *handle,
> +static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 4df4d73038f8..36e2f4e5a865 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -1020,7 +1020,7 @@ static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v3_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v11_0_set_powergating_state(void *handle,
> +static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> index e33f9e9058cc..c6510f12afb4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> @@ -1004,7 +1004,7 @@ static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v4_1_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v12_0_set_powergating_state(void *handle,
> +static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index c1e2f1d79e74..3965b9ca8e9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1100,7 +1100,7 @@ static int gmc_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v6_0_set_powergating_state(void *handle,
> +static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 54a48662f3b5..b43eaa42e5c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1327,7 +1327,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v7_0_set_powergating_state(void *handle,
> +static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index c4f2ad32c078..d36cf90d4133 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1679,7 +1679,7 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v8_0_set_powergating_state(void *handle,
> +static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 94600e5c8ea3..5aac51d9db2f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -2485,7 +2485,7 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v1_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v9_0_set_powergating_state(void *handle,
> +static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index a3fb01f905d4..879d34e88014 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -398,7 +398,7 @@ static int iceland_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int iceland_ih_set_powergating_state(void *handle,
> +static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 09403eac483b..4f271d9f43ba 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -756,10 +756,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v6_0_set_powergating_state(void *handle,
> +static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index 9706d7593d26..5b0a1eaa1fd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -737,10 +737,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v6_1_set_powergating_state(void *handle,
> +static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index 9657145d7cce..a584863f1bed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -727,10 +727,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v7_0_set_powergating_state(void *handle,
> +static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 6762b5c64ccb..c5f692a45bee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -35,7 +35,7 @@
>
> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v2_0_set_powergating_state(void *handle,
> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
> - jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -692,10 +692,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v2_0_set_powergating_state(void *handle,
> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index 4b8c801f204d..f1ddef8e60ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -38,7 +38,7 @@
>
> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v2_5_set_powergating_state(void *handle,
> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
>
> @@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
> - jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
> amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
> @@ -541,10 +541,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v2_5_set_powergating_state(void *handle,
> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 7996209818b6..69f0a9006b96 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -36,7 +36,7 @@
>
> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v3_0_set_powergating_state(void *handle,
> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
> - jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -483,10 +483,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v3_0_set_powergating_state(void *handle,
> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if(state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index 20e1fe89c463..e304108d7024 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -39,7 +39,7 @@
> static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_set_powergating_state(void *handle,
> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
>
> @@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
> - jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
> amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
> @@ -645,10 +645,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_set_powergating_state(void *handle,
> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index 2a53537db135..f4d6a4768ee2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -43,7 +43,7 @@ enum jpeg_engin_status {
>
> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
> @@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
> - ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
>
> return ret;
> @@ -960,10 +960,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> index ef2d4237925b..2a28eb479a34 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> @@ -48,7 +48,7 @@
>
> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
> @@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
> - jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> return 0;
> @@ -676,10 +676,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index 7954a6fae464..692d0083b5f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -36,7 +36,7 @@
>
> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
> - jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -570,10 +570,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 93da900b7ee2..9ca248ea3428 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -677,7 +677,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int navi10_ih_set_powergating_state(void *handle,
> +static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 4e8f9af1e2be..6481f72b32d6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1085,7 +1085,7 @@ static int nv_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int nv_common_set_powergating_state(void *handle,
> +static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* TODO */
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 10fd772cb80f..6a1028baf16d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1087,7 +1087,7 @@ static int sdma_v2_4_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v2_4_set_powergating_state(void *handle,
> +static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 69fba087e09c..42d996d4136f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1506,7 +1506,7 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v3_0_set_powergating_state(void *handle,
> +static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 3f5959557727..a2f5f2be699b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2312,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v4_0_set_powergating_state(void *handle,
> +static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
> case IP_VERSION(4, 1, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index 9c7cea0890c9..95d5de2bd186 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -1830,7 +1830,7 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v4_4_2_set_powergating_state(void *handle,
> +static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 6a675daf5620..82a8bbd53d49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -1859,7 +1859,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v5_0_set_powergating_state(void *handle,
> +static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index e1413ccaf7e4..b84d5c27bb94 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1818,7 +1818,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v5_2_set_powergating_state(void *handle,
> +static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index 4b33bd6b776d..bc9fe03ab145 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1589,7 +1589,7 @@ static int sdma_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v6_0_set_powergating_state(void *handle,
> +static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 24f24974ac1d..c224e7e7e103 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1524,7 +1524,7 @@ static int sdma_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v7_0_set_powergating_state(void *handle,
> +static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index b9934661a92e..6b0211c94836 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -2681,7 +2681,7 @@ static int si_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_common_set_powergating_state(void *handle,
> +static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index d44483ed3363..26782dad9311 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -672,12 +672,12 @@ static int si_dma_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_dma_set_powergating_state(void *handle,
> +static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> u32 tmp;
>
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> WREG32(DMA_PGFSM_WRITE, 0x00002000);
> WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index b018a3b90401..976d803bef8c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -269,7 +269,7 @@ static int si_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_ih_set_powergating_state(void *handle,
> +static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 6ab34c526c86..9fbada694cd7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1481,7 +1481,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
> adev->df.funcs->get_clockgating_state(adev, flags);
> }
>
> -static int soc15_common_set_powergating_state(void *handle,
> +static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* todo */
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index c4b950e75133..6497a65f9738 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -968,10 +968,10 @@ static int soc21_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int soc21_common_set_powergating_state(void *handle,
> +static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
> case IP_VERSION(6, 0, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
> index b20dc81dc257..7b43d8908448 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
> @@ -557,10 +557,10 @@ static int soc24_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int soc24_common_set_powergating_state(void *handle,
> +static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
> case IP_VERSION(7, 0, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 45fb5140c8b7..77fba40e1dbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -454,7 +454,7 @@ static int tonga_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int tonga_ih_set_powergating_state(void *handle,
> +static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index 3011b5853fb4..561fc15173b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -796,7 +796,7 @@ static int uvd_v3_1_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v3_1_set_powergating_state(void *handle,
> +static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 4852a2ab128f..6bd728153b4c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -714,7 +714,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v4_2_set_powergating_state(void *handle,
> +static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -724,7 +724,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE) {
> uvd_v4_2_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index a24b210c79ac..02e0e5c9e701 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -817,7 +817,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v5_0_set_powergating_state(void *handle,
> +static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -827,7 +827,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> if (state == AMD_PG_STATE_GATE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index b4eeeebfe095..fdf23d2b0e42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1476,7 +1476,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v6_0_set_powergating_state(void *handle,
> +static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -1486,7 +1486,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index a4531000ec0b..836643c99572 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -596,7 +596,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vce_v2_0_set_powergating_state(void *handle,
> +static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -606,7 +606,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> return vce_v2_0_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9f9a9d89bcdc..e985cf1e63f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -801,7 +801,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vce_v3_0_set_powergating_state(void *handle,
> +static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -811,7 +811,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> if (state == AMD_PG_STATE_GATE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index f4d2650e6b7a..30d64672f3c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
> }
> #endif
>
> -static int vce_v4_0_set_powergating_state(void *handle,
> +static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> return vce_v4_0_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 1d5b0f4e5b1a..34b1e55a907a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state);
> static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
>
> @@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
> - vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
>
> return 0;
> @@ -1799,7 +1800,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
> }
> }
>
> -static int vcn_v1_0_set_powergating_state(void *handle,
> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCN block.
> @@ -1810,7 +1811,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == adev->vcn.cur_state)
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index d87e5505cf51..6c1f5d05f90a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v2_0_set_powergating_state(void *handle,
> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
> - vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -1796,7 +1796,7 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> }
>
>
> -static int vcn_v2_0_set_powergating_state(void *handle,
> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCN block.
> @@ -1807,7 +1807,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev)) {
> adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index ad0922eb16c0..35ded346771d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v2_5_set_powergating_state(void *handle,
> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -398,8 +398,9 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, mmUVD_STATUS)))
> - vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> + vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> + }
> Dont really need braces here as its one line and continous check.
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
> @@ -1825,10 +1826,10 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vcn_v2_5_set_powergating_state(void *handle,
> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 19c7f9cd4c15..c02c9ef8ddeb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v3_0_set_powergating_state(void *handle,
> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -430,9 +430,9 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
>
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> - vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> + vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -2159,10 +2159,10 @@ static int vcn_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vcn_v3_0_set_powergating_state(void *handle,
> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> /* for SRIOV, guest should not control VCN Power-gating
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index e97d7f4ae371..319eb5a3d061 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
> static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_set_powergating_state(void *handle,
> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -357,9 +357,9 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
> continue;
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> + vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> @@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_sta
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> /* for SRIOV, guest should not control VCN Power-gating
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index ba22913398ec..b6c1135d6fec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
> static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_3_set_powergating_state(void *handle,
> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -319,7 +319,7 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
> cancel_delayed_work_sync(&adev->vcn.idle_work);
>
> if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -1623,10 +1623,10 @@ static int vcn_v4_0_3_set_clockgating_state(void *handle,
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_3_set_powergating_state(void *handle,
> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> /* for SRIOV, guest should not control VCN Power-gating
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 873672f64778..ebf6301b13be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>
> static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_5_set_powergating_state(void *handle,
> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -309,7 +309,7 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -1531,9 +1531,10 @@ static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->vcn.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 893e66c2b9a5..50c102f1b5fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>
> static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v5_0_0_set_powergating_state(void *handle,
> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -273,7 +273,7 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -1258,9 +1258,10 @@ static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
> *
> * Set VCN block powergating state
> */
> -static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->vcn.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 73de5909f655..8df4f4352d65 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -616,7 +616,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
>
> }
>
> -static int vega10_ih_set_powergating_state(void *handle,
> +static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> index a42404a58015..4ac43aeb85c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> @@ -681,7 +681,7 @@ static int vega20_ih_set_clockgating_state(void *handle,
>
> }
>
> -static int vega20_ih_set_powergating_state(void *handle,
> +static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 4996049dc199..6b58723f0b2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -2003,7 +2003,7 @@ static int vi_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vi_common_set_powergating_state(void *handle,
> +static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 7616d7a509b9..d5a0417f95df 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dm_set_powergating_state(void *handle,
> +static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index f98b3a544477..03c77bbc2e6d 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -398,7 +398,7 @@ struct amd_ip_funcs {
> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
> int (*set_clockgating_state)(void *handle,
> enum amd_clockgating_state state);
> - int (*set_powergating_state)(void *handle,
> + int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> void (*get_clockgating_state)(void *handle, u64 *flags);
> void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index af7da780b58b..d5130da88162 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int kv_dpm_set_powergating_state(void *handle,
> +static int kv_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index a4908f0402f1..18c47fa89bc1 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_dpm_set_powergating_state(void *handle,
> +static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index de5ee1c5503f..069b604d6e7a 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -254,7 +254,7 @@ static int pp_sw_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int pp_set_powergating_state(void *handle,
> +static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 115931d1c461..4aaaf0e0b851 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2184,7 +2184,7 @@ static int smu_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int smu_set_powergating_state(void *handle,
> +static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-22 7:42 ` Khatri, Sunil
@ 2024-10-25 2:46 ` Boyuan Zhang
0 siblings, 0 replies; 45+ messages in thread
From: Boyuan Zhang @ 2024-10-25 2:46 UTC (permalink / raw)
To: Khatri, Sunil, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
On 2024-10-22 03:42, Khatri, Sunil wrote:
>
> On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Pass ip_block instead of adev in set_powergating_state callback
>> function.
>> Modify set_powergating_state ip functions for all correspoding ip
>> blocks.
>>
>> v2: fix a ip block index error.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> Suggested-by: Christian König <christian.koenig@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 ++++-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 13 +++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
>> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
>> 82 files changed, 165 insertions(+), 157 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> index 575826d220b8..64828cb7c2f1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> @@ -600,10 +600,10 @@ static int acp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int acp_set_powergating_state(void *handle,
>> +static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> amdgpu_dpm_set_powergating_by_smu(adev,
>> AMD_IP_BLOCK_TYPE_ACP, enable, 0);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index b545940e512b..dd3ae5d74436 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -724,7 +724,10 @@ void amdgpu_amdkfd_set_compute_idle(struct
>> amdgpu_device *adev, bool idle)
>> /* Disable GFXOFF and PG. Temporary workaround
>> * to fix some compute applications issue on GFX9.
>> */
>> -
>> adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void
>> *)adev, state);
> We have the function for this requirement and i feel better use this
> amdgpu_device_ip_get_ip_block
Fixed in new patch-set just submitted (Patch 07/29)
>> + for (int i = 0; i < adev->num_ip_blocks; i++) {
>> + if (adev->ip_blocks[i].version->type ==
>> AMD_IP_BLOCK_TYPE_GFX)
>> + adev->ip_blocks[i].version->funcs->set_powergating_state((void
>> *)&adev->ip_blocks[i], state);
>> + }
>> }
>> amdgpu_dpm_switch_power_profile(adev,
>> PP_SMC_POWER_PROFILE_COMPUTE,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index dbe4c26f63e6..fe5de35eef64 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void
>> *dev,
>> if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
>> continue;
>> r = adev->ip_blocks[i].version->funcs->set_powergating_state(
>> - (void *)adev, state);
>> + (void *)&adev->ip_blocks[i], state);
>> We dont need type casting anymore by void * as we already have
>> ip_block type ptr also valid at other places too and probably in
>> other patches
>> if (r)
>> DRM_ERROR("set_powergating_state of IP block <%s>
>> failed %d\n",
>> adev->ip_blocks[i].version->funcs->name, r);
>> @@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct
>> amdgpu_device *adev,
>> adev->ip_blocks[i].version->type !=
>> AMD_IP_BLOCK_TYPE_JPEG &&
>> adev->ip_blocks[i].version->funcs->set_powergating_state) {
>> /* enable powergating to save power */
>> - r =
>> adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
>> + r =
>> adev->ip_blocks[i].version->funcs->set_powergating_state((void
>> *)&adev->ip_blocks[i],
>> state);
>> Typecasting not needed.
>> if (r) {
>> DRM_ERROR("set_powergating_state(gate) of IP block
>> <%s> failed %d\n",
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> index adc0b80ca5db..844f71eeea27 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> @@ -164,7 +164,7 @@ static int isp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int isp_set_powergating_state(void *handle,
>> +static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> index 8ef6bf7c6b65..527470323c33 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> @@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int psp_set_powergating_state(void *handle,
>> +static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> index fd31e2e9feb9..f44ce5edba6a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> @@ -647,7 +647,7 @@ static int amdgpu_vkms_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int amdgpu_vkms_set_powergating_state(void *handle,
>> +static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> index 6d96e1f21e20..f3a9ea3f6044 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> @@ -644,10 +644,10 @@ static int vpe_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vpe_set_powergating_state(void *handle,
>> +static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> struct amdgpu_vpe *vpe = &adev->vpe;
>> if (!adev->pm.dpm_enabled)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>> index 6c18ab35cf69..08b398aa6c6d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>> @@ -2185,7 +2185,7 @@ static int
>> cik_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int cik_common_set_powergating_state(void *handle,
>> +static int cik_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index 9e9a58fd86ce..42c3eb8b6a95 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -408,7 +408,7 @@ static int cik_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>>
>> Function could be remove in another patch as this isnt doing anything
>> by checking if the fuction is NULL or not.
>> -static int cik_ih_set_powergating_state(void *handle,
>> +static int cik_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index df3f429e003e..5283b0e94f02 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -1204,7 +1204,7 @@ static int cik_sdma_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int cik_sdma_set_powergating_state(void *handle,
>> +static int cik_sdma_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index cadd69a243af..4bf5402bd3aa 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -405,7 +405,7 @@ static int cz_ih_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int cz_ih_set_powergating_state(void *handle,
>> +static int cz_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> // TODO
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> index 2d0a24a343f7..e7505934cce2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> @@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
> Clean up in a different patch as it returns 0 and all other functions
> which return 0 in one separate patch.
>> -static int dce_v10_0_set_powergating_state(void *handle,
>> +static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> index 386ece7bc389..8adee675f4d5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> @@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> Same as above and please follow the clean up in one patch for a
>> particular function for all files can take reference of any other
>> function that i pushed as that code is merged.
>> -static int dce_v11_0_set_powergating_state(void *handle,
>> +static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> index cd3e0118988d..66cb19f9b073 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> @@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v6_0_set_powergating_state(void *handle,
>> +static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> index 295bc1d47095..57a5207b4e76 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> @@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v8_0_set_powergating_state(void *handle,
>> +static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index bf5c739c7058..b5da9a1e8216 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -3673,7 +3673,7 @@ static void
>> gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
>> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device
>> *adev,
>> unsigned int vmid);
>> -static int gfx_v10_0_set_powergating_state(void *handle,
>> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring,
>> uint64_t queue_mask)
>> {
>> @@ -7451,7 +7451,7 @@ static int gfx_v10_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> * otherwise the gfxoff disallowing will be failed to set.
>> */
>> if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
>> - gfx_v10_0_set_powergating_state(ip_block->adev,
>> AMD_PG_STATE_UNGATE);
>> + gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
>> if (!adev->no_hw_access) {
>> if (amdgpu_async_gfx_ring) {
>> @@ -8339,10 +8339,10 @@ static const struct amdgpu_rlc_funcs
>> gfx_v10_0_rlc_funcs_sriov = {
>> .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
>> };
>> -static int gfx_v10_0_set_powergating_state(void *handle,
>> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index c78a63da8d2e..92786e3bbf0e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -5424,10 +5424,10 @@ static void gfx_v11_cntl_pg(struct
>> amdgpu_device *adev, bool enable)
>> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
>> }
>> -static int gfx_v11_0_set_powergating_state(void *handle,
>> +static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> index dc25fcb89b13..4ff78c9e3e43 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> @@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct
>> amdgpu_device *adev, bool enable)
>> }
>> #endif
>> -static int gfx_v12_0_set_powergating_state(void *handle,
>> +static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 6ac6d4dfa49f..429aa895d6bf 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -3400,11 +3400,11 @@ static int
>> gfx_v6_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int gfx_v6_0_set_powergating_state(void *handle,
>> +static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index 77150c9f1e18..7c04dccec8d7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -4869,11 +4869,11 @@ static int
>> gfx_v7_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int gfx_v7_0_set_powergating_state(void *handle,
>> +static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index cb59ba3a6d1b..22ada2ede46b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -5360,10 +5360,10 @@ static void
>> cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
>> }
>> }
>> -static int gfx_v8_0_set_powergating_state(void *handle,
>> +static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index d85b2968a7cf..6516e88c55aa 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs
>> gfx_v9_0_rlc_funcs = {
>> .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
>> };
>> -static int gfx_v9_0_set_powergating_state(void *handle,
>> +static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> index 7d425d2e7ab0..627652cab308 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> @@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs
>> gfx_v9_4_3_rlc_funcs = {
>> .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
>> };
>> -static int gfx_v9_4_3_set_powergating_state(void *handle,
>> +static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> index 5cf2002fcba8..b398021d5b90 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> @@ -1133,7 +1133,7 @@ static void
>> gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v2_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v10_0_set_powergating_state(void *handle,
>> +static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> index 4df4d73038f8..36e2f4e5a865 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> @@ -1020,7 +1020,7 @@ static void
>> gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v3_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v11_0_set_powergating_state(void *handle,
>> +static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> index e33f9e9058cc..c6510f12afb4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> @@ -1004,7 +1004,7 @@ static void
>> gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v4_1_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v12_0_set_powergating_state(void *handle,
>> +static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index c1e2f1d79e74..3965b9ca8e9c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -1100,7 +1100,7 @@ static int gmc_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v6_0_set_powergating_state(void *handle,
>> +static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index 54a48662f3b5..b43eaa42e5c7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -1327,7 +1327,7 @@ static int gmc_v7_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v7_0_set_powergating_state(void *handle,
>> +static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index c4f2ad32c078..d36cf90d4133 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -1679,7 +1679,7 @@ static int gmc_v8_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v8_0_set_powergating_state(void *handle,
>> +static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 94600e5c8ea3..5aac51d9db2f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -2485,7 +2485,7 @@ static void gmc_v9_0_get_clockgating_state(void
>> *handle, u64 *flags)
>> athub_v1_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v9_0_set_powergating_state(void *handle,
>> +static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index a3fb01f905d4..879d34e88014 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -398,7 +398,7 @@ static int iceland_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int iceland_ih_set_powergating_state(void *handle,
>> +static int iceland_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> index 09403eac483b..4f271d9f43ba 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> @@ -756,10 +756,10 @@ static void
>> ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v6_0_set_powergating_state(void *handle,
>> +static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> index 9706d7593d26..5b0a1eaa1fd0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> @@ -737,10 +737,10 @@ static void
>> ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v6_1_set_powergating_state(void *handle,
>> +static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> index 9657145d7cce..a584863f1bed 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> @@ -727,10 +727,10 @@ static void
>> ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v7_0_set_powergating_state(void *handle,
>> +static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> index 6762b5c64ccb..c5f692a45bee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> @@ -35,7 +35,7 @@
>> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v2_0_set_powergating_state(void *handle,
>> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
>> - jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -692,10 +692,10 @@ static int jpeg_v2_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v2_0_set_powergating_state(void *handle,
>> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> index 4b8c801f204d..f1ddef8e60ee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> @@ -38,7 +38,7 @@
>> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v2_5_set_powergating_state(void *handle,
>> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
>> @@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
>> - jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v2_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
>> amdgpu_irq_put(adev,
>> &adev->jpeg.inst[i].ras_poison_irq, 0);
>> @@ -541,10 +541,10 @@ static int jpeg_v2_5_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v2_5_set_powergating_state(void *handle,
>> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> index 7996209818b6..69f0a9006b96 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> @@ -36,7 +36,7 @@
>> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v3_0_set_powergating_state(void *handle,
>> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
>> - jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -483,10 +483,10 @@ static int jpeg_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v3_0_set_powergating_state(void *handle,
>> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if(state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> index 20e1fe89c463..e304108d7024 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> @@ -39,7 +39,7 @@
>> static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
>> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
>> @@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
>> - jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v4_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
>> amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
>> @@ -645,10 +645,10 @@ static int jpeg_v4_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> index 2a53537db135..f4d6a4768ee2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> @@ -43,7 +43,7 @@ enum jpeg_engin_status {
>> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
>> static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
>> @@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
>> - ret = jpeg_v4_0_3_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + ret = jpeg_v4_0_3_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> return ret;
>> @@ -960,10 +960,10 @@ static int
>> jpeg_v4_0_3_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> index ef2d4237925b..2a28eb479a34 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> @@ -48,7 +48,7 @@
>> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
>> @@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
>> - jpeg_v4_0_5_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + jpeg_v4_0_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> return 0;
>> @@ -676,10 +676,10 @@ static int
>> jpeg_v4_0_5_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> index 7954a6fae464..692d0083b5f7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> @@ -36,7 +36,7 @@
>> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
>> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
>> - jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -570,10 +570,10 @@ static int
>> jpeg_v5_0_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
>> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index 93da900b7ee2..9ca248ea3428 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -677,7 +677,7 @@ static int navi10_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int navi10_ih_set_powergating_state(void *handle,
>> +static int navi10_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 4e8f9af1e2be..6481f72b32d6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -1085,7 +1085,7 @@ static int nv_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int nv_common_set_powergating_state(void *handle,
>> +static int nv_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* TODO */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> index 10fd772cb80f..6a1028baf16d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> @@ -1087,7 +1087,7 @@ static int sdma_v2_4_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v2_4_set_powergating_state(void *handle,
>> +static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index 69fba087e09c..42d996d4136f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -1506,7 +1506,7 @@ static int sdma_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v3_0_set_powergating_state(void *handle,
>> +static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index 3f5959557727..a2f5f2be699b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -2312,10 +2312,10 @@ static int
>> sdma_v4_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int sdma_v4_0_set_powergating_state(void *handle,
>> +static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
>> case IP_VERSION(4, 1, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> index 9c7cea0890c9..95d5de2bd186 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> @@ -1830,7 +1830,7 @@ static int
>> sdma_v4_4_2_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int sdma_v4_4_2_set_powergating_state(void *handle,
>> +static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> index 6a675daf5620..82a8bbd53d49 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> @@ -1859,7 +1859,7 @@ static int sdma_v5_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v5_0_set_powergating_state(void *handle,
>> +static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> index e1413ccaf7e4..b84d5c27bb94 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> @@ -1818,7 +1818,7 @@ static int sdma_v5_2_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v5_2_set_powergating_state(void *handle,
>> +static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> index 4b33bd6b776d..bc9fe03ab145 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> @@ -1589,7 +1589,7 @@ static int sdma_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v6_0_set_powergating_state(void *handle,
>> +static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> index 24f24974ac1d..c224e7e7e103 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> @@ -1524,7 +1524,7 @@ static int sdma_v7_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v7_0_set_powergating_state(void *handle,
>> +static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
>> b/drivers/gpu/drm/amd/amdgpu/si.c
>> index b9934661a92e..6b0211c94836 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
>> @@ -2681,7 +2681,7 @@ static int si_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_common_set_powergating_state(void *handle,
>> +static int si_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> index d44483ed3363..26782dad9311 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> @@ -672,12 +672,12 @@ static int si_dma_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_dma_set_powergating_state(void *handle,
>> +static int si_dma_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> u32 tmp;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> WREG32(DMA_PGFSM_WRITE, 0x00002000);
>> WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index b018a3b90401..976d803bef8c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -269,7 +269,7 @@ static int si_ih_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int si_ih_set_powergating_state(void *handle,
>> +static int si_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index 6ab34c526c86..9fbada694cd7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -1481,7 +1481,7 @@ static void
>> soc15_common_get_clockgating_state(void *handle, u64 *flags)
>> adev->df.funcs->get_clockgating_state(adev, flags);
>> }
>> -static int soc15_common_set_powergating_state(void *handle,
>> +static int soc15_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* todo */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> index c4b950e75133..6497a65f9738 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> @@ -968,10 +968,10 @@ static int
>> soc21_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int soc21_common_set_powergating_state(void *handle,
>> +static int soc21_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
>> case IP_VERSION(6, 0, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> index b20dc81dc257..7b43d8908448 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> @@ -557,10 +557,10 @@ static int
>> soc24_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int soc24_common_set_powergating_state(void *handle,
>> +static int soc24_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
>> case IP_VERSION(7, 0, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index 45fb5140c8b7..77fba40e1dbc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -454,7 +454,7 @@ static int tonga_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int tonga_ih_set_powergating_state(void *handle,
>> +static int tonga_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> index 3011b5853fb4..561fc15173b6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> @@ -796,7 +796,7 @@ static int uvd_v3_1_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v3_1_set_powergating_state(void *handle,
>> +static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> index 4852a2ab128f..6bd728153b4c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> @@ -714,7 +714,7 @@ static int uvd_v4_2_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v4_2_set_powergating_state(void *handle,
>> +static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -724,7 +724,7 @@ static int uvd_v4_2_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE) {
>> uvd_v4_2_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> index a24b210c79ac..02e0e5c9e701 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> @@ -817,7 +817,7 @@ static int uvd_v5_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v5_0_set_powergating_state(void *handle,
>> +static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -827,7 +827,7 @@ static int uvd_v5_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> if (state == AMD_PG_STATE_GATE) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index b4eeeebfe095..fdf23d2b0e42 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1476,7 +1476,7 @@ static int uvd_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v6_0_set_powergating_state(void *handle,
>> +static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -1486,7 +1486,7 @@ static int uvd_v6_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> index a4531000ec0b..836643c99572 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> @@ -596,7 +596,7 @@ static int vce_v2_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vce_v2_0_set_powergating_state(void *handle,
>> +static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -606,7 +606,7 @@ static int vce_v2_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> return vce_v2_0_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> index 9f9a9d89bcdc..e985cf1e63f1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> @@ -801,7 +801,7 @@ static int vce_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vce_v3_0_set_powergating_state(void *handle,
>> +static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -811,7 +811,7 @@ static int vce_v3_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> if (state == AMD_PG_STATE_GATE) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index f4d2650e6b7a..30d64672f3c5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void
>> *handle,
>> }
>> #endif
>> -static int vce_v4_0_set_powergating_state(void *handle,
>> +static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> return vce_v4_0_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> index 1d5b0f4e5b1a..34b1e55a907a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> @@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v1_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state);
>> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state);
>> static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
>> - vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> }
>> return 0;
>> @@ -1799,7 +1800,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct
>> amdgpu_ring *ring, uint32_t coun
>> }
>> }
>> -static int vcn_v1_0_set_powergating_state(void *handle,
>> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCN block.
>> @@ -1810,7 +1811,7 @@ static int vcn_v1_0_set_powergating_state(void
>> *handle,
>> * the smc and the hw blocks
>> */
>> int ret;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == adev->vcn.cur_state)
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index d87e5505cf51..6c1f5d05f90a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_2_0[] = {
>> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v2_0_set_powergating_state(void *handle,
>> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
>> - vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -1796,7 +1796,7 @@ int vcn_v2_0_dec_ring_test_ring(struct
>> amdgpu_ring *ring)
>> }
>> -static int vcn_v2_0_set_powergating_state(void *handle,
>> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCN block.
>> @@ -1807,7 +1807,7 @@ static int vcn_v2_0_set_powergating_state(void
>> *handle,
>> * the smc and the hw blocks
>> */
>> int ret;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev)) {
>> adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index ad0922eb16c0..35ded346771d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_2_5[] = {
>> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v2_5_set_powergating_state(void *handle,
>> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -398,8 +398,9 @@ static int vcn_v2_5_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, mmUVD_STATUS)))
>> - vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> + vcn_v2_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> + }
>> Dont really need braces here as its one line and continous check.
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq,
>> 0);
>> @@ -1825,10 +1826,10 @@ static int
>> vcn_v2_5_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vcn_v2_5_set_powergating_state(void *handle,
>> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 19c7f9cd4c15..c02c9ef8ddeb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct
>> amdgpu_device *adev);
>> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v3_0_set_powergating_state(void *handle,
>> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -430,9 +430,9 @@ static int vcn_v3_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> - vcn_v3_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> + vcn_v3_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -2159,10 +2159,10 @@ static int
>> vcn_v3_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vcn_v3_0_set_powergating_state(void *handle,
>> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> /* for SRIOV, guest should not control VCN Power-gating
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> index e97d7f4ae371..319eb5a3d061 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> @@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
>> static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device
>> *adev);
>> static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_set_powergating_state(void *handle,
>> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -357,9 +357,9 @@ static int vcn_v4_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> continue;
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v4_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> + vcn_v4_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> @@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void
>> *handle, enum amd_clockgating_sta
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> /* for SRIOV, guest should not control VCN Power-gating
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index ba22913398ec..b6c1135d6fec 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_4_0_3[] = {
>> static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
>> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device
>> *adev);
>> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_3_set_powergating_state(void *handle,
>> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -319,7 +319,7 @@ static int vcn_v4_0_3_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> cancel_delayed_work_sync(&adev->vcn.idle_work);
>> if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
>> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -1623,10 +1623,10 @@ static int
>> vcn_v4_0_3_set_clockgating_state(void *handle,
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_3_set_powergating_state(void *handle,
>> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> /* for SRIOV, guest should not control VCN Power-gating
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> index 873672f64778..ebf6301b13be 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> @@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static void vcn_v4_0_5_set_unified_ring_funcs(struct
>> amdgpu_device *adev);
>> static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_5_set_powergating_state(void *handle,
>> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -309,7 +309,7 @@ static int vcn_v4_0_5_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v4_0_5_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v4_0_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -1531,9 +1531,10 @@ static int
>> vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_5_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->vcn.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> index 893e66c2b9a5..50c102f1b5fe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> @@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static void vcn_v5_0_0_set_unified_ring_funcs(struct
>> amdgpu_device *adev);
>> static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v5_0_0_set_powergating_state(void *handle,
>> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -273,7 +273,7 @@ static int vcn_v5_0_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v5_0_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v5_0_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -1258,9 +1258,10 @@ static int
>> vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v5_0_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->vcn.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> index 73de5909f655..8df4f4352d65 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> @@ -616,7 +616,7 @@ static int vega10_ih_set_clockgating_state(void
>> *handle,
>> }
>> -static int vega10_ih_set_powergating_state(void *handle,
>> +static int vega10_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> index a42404a58015..4ac43aeb85c1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> @@ -681,7 +681,7 @@ static int vega20_ih_set_clockgating_state(void
>> *handle,
>> }
>> -static int vega20_ih_set_powergating_state(void *handle,
>> +static int vega20_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
>> b/drivers/gpu/drm/amd/amdgpu/vi.c
>> index 4996049dc199..6b58723f0b2e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -2003,7 +2003,7 @@ static int vi_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vi_common_set_powergating_state(void *handle,
>> +static int vi_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 7616d7a509b9..d5a0417f95df 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int dm_set_powergating_state(void *handle,
>> +static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
>> b/drivers/gpu/drm/amd/include/amd_shared.h
>> index f98b3a544477..03c77bbc2e6d 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -398,7 +398,7 @@ struct amd_ip_funcs {
>> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
>> int (*set_clockgating_state)(void *handle,
>> enum amd_clockgating_state state);
>> - int (*set_powergating_state)(void *handle,
>> + int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state);
>> void (*get_clockgating_state)(void *handle, u64 *flags);
>> void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> index af7da780b58b..d5130da88162 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> @@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int kv_dpm_set_powergating_state(void *handle,
>> +static int kv_dpm_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> index a4908f0402f1..18c47fa89bc1 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> @@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_dpm_set_powergating_state(void *handle,
>> +static int si_dpm_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> index de5ee1c5503f..069b604d6e7a 100644
>> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> @@ -254,7 +254,7 @@ static int pp_sw_reset(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static int pp_set_powergating_state(void *handle,
>> +static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 115931d1c461..4aaaf0e0b851 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -2184,7 +2184,7 @@ static int smu_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int smu_set_powergating_state(void *handle,
>> +static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (6 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-22 7:58 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 09/32] drm/amdgpu: track instances of the same IP block boyuan.zhang
` (24 subsequent siblings)
32 siblings, 1 reply; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass ip_block instead of adev in set_clockgating_state() and is_idle()
callback functions. Modify set_clockgating_state() and is_idle() ip
functions for all correspoding ip blocks.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 ++++++------
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/si.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/soc21.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/soc24.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 17 ++++++-----------
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++------------
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 14 +++++++-------
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vi.c | 6 +++---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
drivers/gpu/drm/amd/include/amd_shared.h | 4 ++--
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++--
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++--
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++--
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
82 files changed, 293 insertions(+), 299 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 64828cb7c2f1..5b0856b89801 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -579,7 +579,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool acp_is_idle(void *handle)
+static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -594,7 +594,7 @@ static int acp_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int acp_set_clockgating_state(void *handle,
+static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fe5de35eef64..af159ebe9cbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2120,7 +2120,7 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
continue;
r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
- (void *)adev, state);
+ (void *)&adev->ip_blocks[i], state);
if (r)
DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
@@ -3091,7 +3091,7 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
adev->ip_blocks[i].version->funcs->set_clockgating_state) {
/* enable clockgating to save power */
- r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+ r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)&adev->ip_blocks[i],
state);
if (r) {
DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
index 844f71eeea27..fc89dee1b972 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
@@ -143,7 +143,7 @@ static int isp_early_init(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool isp_is_idle(void *handle)
+static bool isp_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -158,7 +158,7 @@ static int isp_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int isp_set_clockgating_state(void *handle,
+static int isp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 527470323c33..86a68d5ee05f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3787,7 +3787,7 @@ int psp_config_sq_perfmon(struct psp_context *psp,
return ret;
}
-static int psp_set_clockgating_state(void *handle,
+static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index f44ce5edba6a..89ee35f980cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -626,7 +626,7 @@ static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block)
return drm_mode_config_helper_resume(adev_to_drm(ip_block->adev));
}
-static bool amdgpu_vkms_is_idle(void *handle)
+static bool amdgpu_vkms_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -641,7 +641,7 @@ static int amdgpu_vkms_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int amdgpu_vkms_set_clockgating_state(void *handle,
+static int amdgpu_vkms_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index f3a9ea3f6044..416d1a073173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -638,7 +638,7 @@ static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
return r;
}
-static int vpe_set_clockgating_state(void *handle,
+static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 08b398aa6c6d..1f637c7a256d 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2163,7 +2163,7 @@ static int cik_common_resume(struct amdgpu_ip_block *ip_block)
return cik_common_hw_init(ip_block);
}
-static bool cik_common_is_idle(void *handle)
+static bool cik_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -2179,7 +2179,7 @@ static int cik_common_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int cik_common_set_clockgating_state(void *handle,
+static int cik_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 42c3eb8b6a95..a1ad74f6d581 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -345,9 +345,9 @@ static int cik_ih_resume(struct amdgpu_ip_block *ip_block)
return cik_ih_hw_init(ip_block);
}
-static bool cik_ih_is_idle(void *handle)
+static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -402,7 +402,7 @@ static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int cik_ih_set_clockgating_state(void *handle,
+static int cik_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 5283b0e94f02..ef352d7be29c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1023,9 +1023,9 @@ static int cik_sdma_resume(struct amdgpu_ip_block *ip_block)
return cik_sdma_hw_init(ip_block);
}
-static bool cik_sdma_is_idle(void *handle)
+static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1189,11 +1189,11 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int cik_sdma_set_clockgating_state(void *handle,
+static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_CG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 4bf5402bd3aa..c9fa011308d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -341,9 +341,9 @@ static int cz_ih_resume(struct amdgpu_ip_block *ip_block)
return cz_ih_hw_init(ip_block);
}
-static bool cz_ih_is_idle(void *handle)
+static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -398,7 +398,7 @@ static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int cz_ih_set_clockgating_state(void *handle,
+static int cz_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
// TODO
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index e7505934cce2..96acbb56cd4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2943,7 +2943,7 @@ static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)
return amdgpu_display_resume_helper(adev);
}
-static bool dce_v10_0_is_idle(void *handle)
+static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -3307,7 +3307,7 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
return 0;
}
-static int dce_v10_0_set_clockgating_state(void *handle,
+static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 8adee675f4d5..48c5270b8a3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3081,7 +3081,7 @@ static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block)
return amdgpu_display_resume_helper(adev);
}
-static bool dce_v11_0_is_idle(void *handle)
+static bool dce_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -3439,7 +3439,7 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
return 0;
}
-static int dce_v11_0_set_clockgating_state(void *handle,
+static int dce_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 66cb19f9b073..65a9fdb36d06 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -2838,7 +2838,7 @@ static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block)
return amdgpu_display_resume_helper(adev);
}
-static bool dce_v6_0_is_idle(void *handle)
+static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -3129,7 +3129,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
}
-static int dce_v6_0_set_clockgating_state(void *handle,
+static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 57a5207b4e76..c48f8a1fdc4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2861,7 +2861,7 @@ static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block)
return amdgpu_display_resume_helper(adev);
}
-static bool dce_v8_0_is_idle(void *handle)
+static bool dce_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -3217,7 +3217,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
}
-static int dce_v8_0_set_clockgating_state(void *handle,
+static int dce_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index b5da9a1e8216..831beedcbaeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7486,9 +7486,9 @@ static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v10_0_hw_init(ip_block);
}
-static bool gfx_v10_0_is_idle(void *handle)
+static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
@@ -8377,10 +8377,10 @@ static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
-static int gfx_v10_0_set_clockgating_state(void *handle,
+static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 92786e3bbf0e..72ef40a6eb3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4737,9 +4737,9 @@ static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v11_0_hw_init(ip_block);
}
-static bool gfx_v11_0_is_idle(void *handle)
+static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
@@ -5460,10 +5460,10 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
-static int gfx_v11_0_set_clockgating_state(void *handle,
+static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 4ff78c9e3e43..64551c8cea97 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3653,9 +3653,9 @@ static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v12_0_hw_init(ip_block);
}
-static bool gfx_v12_0_is_idle(void *handle)
+static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
@@ -4097,10 +4097,10 @@ static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
return 0;
}
-static int gfx_v12_0_set_clockgating_state(void *handle,
+static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 429aa895d6bf..37ce7193701f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3163,9 +3163,9 @@ static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v6_0_hw_init(ip_block);
}
-static bool gfx_v6_0_is_idle(void *handle)
+static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
return false;
@@ -3179,7 +3179,7 @@ static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (gfx_v6_0_is_idle(adev))
+ if (gfx_v6_0_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -3378,11 +3378,11 @@ static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int gfx_v6_0_set_clockgating_state(void *handle,
+static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_CG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 7c04dccec8d7..fb8e56472e65 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4509,9 +4509,9 @@ static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v7_0_hw_init(ip_block);
}
-static bool gfx_v7_0_is_idle(void *handle)
+static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
return false;
@@ -4846,11 +4846,11 @@ static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int gfx_v7_0_set_clockgating_state(void *handle,
+static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_CG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 22ada2ede46b..15db88295288 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4830,9 +4830,9 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
return r;
}
-static bool gfx_v8_0_is_idle(void *handle)
+static bool gfx_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
|| RREG32(mmGRBM_STATUS2) != 0x8)
@@ -4871,7 +4871,7 @@ static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (gfx_v8_0_is_idle(adev))
+ if (gfx_v8_0_is_idle(ip_block))
return 0;
udelay(1);
@@ -5975,10 +5975,10 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
return 0;
}
-static int gfx_v8_0_set_clockgating_state(void *handle,
+static int gfx_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6516e88c55aa..bc8853b65787 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4084,9 +4084,9 @@ static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v9_0_hw_init(ip_block);
}
-static bool gfx_v9_0_is_idle(void *handle)
+static bool gfx_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
@@ -4101,7 +4101,7 @@ static int gfx_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (gfx_v9_0_is_idle(adev))
+ if (gfx_v9_0_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -5259,10 +5259,10 @@ static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
-static int gfx_v9_0_set_clockgating_state(void *handle,
+static int gfx_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 627652cab308..dd4b62764b23 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2396,9 +2396,9 @@ static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block)
return gfx_v9_4_3_hw_init(ip_block);
}
-static bool gfx_v9_4_3_is_idle(void *handle)
+static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, num_xcc;
num_xcc = NUM_XCC(adev->gfx.xcc_mask);
@@ -2416,7 +2416,7 @@ static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (gfx_v9_4_3_is_idle(adev))
+ if (gfx_v9_4_3_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -2766,10 +2766,10 @@ static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
}
-static int gfx_v9_4_3_set_clockgating_state(void *handle,
+static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, num_xcc;
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index b398021d5b90..22a158091674 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1073,7 +1073,7 @@ static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v10_0_is_idle(void *handle)
+static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* MC is always ready in GMC v10.*/
return true;
@@ -1090,11 +1090,11 @@ static int gmc_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int gmc_v10_0_set_clockgating_state(void *handle,
+static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
int r;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
/*
* The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 36e2f4e5a865..53ec799832ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -981,7 +981,7 @@ static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v11_0_is_idle(void *handle)
+static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* MC is always ready in GMC v11.*/
return true;
@@ -998,11 +998,11 @@ static int gmc_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int gmc_v11_0_set_clockgating_state(void *handle,
+static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
int r;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
r = adev->mmhub.funcs->set_clockgating(adev, state);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index c6510f12afb4..06472c90a58d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -965,7 +965,7 @@ static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v12_0_is_idle(void *handle)
+static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* MC is always ready in GMC v11.*/
return true;
@@ -982,11 +982,11 @@ static int gmc_v12_0_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int gmc_v12_0_set_clockgating_state(void *handle,
+static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
int r;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
r = adev->mmhub.funcs->set_clockgating(adev, state);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 3965b9ca8e9c..c7b3b18d6152 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -956,9 +956,9 @@ static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v6_0_is_idle(void *handle)
+static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
@@ -975,7 +975,7 @@ static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (gmc_v6_0_is_idle(adev))
+ if (gmc_v6_0_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -1094,7 +1094,7 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int gmc_v6_0_set_clockgating_state(void *handle,
+static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b43eaa42e5c7..7d084f98f3b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1131,9 +1131,9 @@ static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v7_0_is_idle(void *handle)
+static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
@@ -1307,11 +1307,11 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int gmc_v7_0_set_clockgating_state(void *handle,
+static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_CG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index d36cf90d4133..ee279518b5db 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1262,9 +1262,9 @@ static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v8_0_is_idle(void *handle)
+static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
@@ -1658,10 +1658,10 @@ static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
}
}
-static int gmc_v8_0_set_clockgating_state(void *handle,
+static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5aac51d9db2f..b2b907c82d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2446,7 +2446,7 @@ static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool gmc_v9_0_is_idle(void *handle)
+static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* MC is always ready in GMC v9.*/
return true;
@@ -2464,10 +2464,10 @@ static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int gmc_v9_0_set_clockgating_state(void *handle,
+static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
adev->mmhub.funcs->set_clockgating(adev, state);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 879d34e88014..784a77e06935 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -335,9 +335,9 @@ static int iceland_ih_resume(struct amdgpu_ip_block *ip_block)
return iceland_ih_hw_init(ip_block);
}
-static bool iceland_ih_is_idle(void *handle)
+static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -392,7 +392,7 @@ static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int iceland_ih_set_clockgating_state(void *handle,
+static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 4f271d9f43ba..47e105659177 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -652,7 +652,7 @@ static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block)
return ih_v6_0_hw_init(ip_block);
}
-static bool ih_v6_0_is_idle(void *handle)
+static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -693,10 +693,10 @@ static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,
}
}
-static int ih_v6_0_set_clockgating_state(void *handle,
+static int ih_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
ih_v6_0_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 5b0a1eaa1fd0..a18778a50272 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -631,7 +631,7 @@ static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block)
return ih_v6_1_hw_init(ip_block);
}
-static bool ih_v6_1_is_idle(void *handle)
+static bool ih_v6_1_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -674,10 +674,10 @@ static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
return;
}
-static int ih_v6_1_set_clockgating_state(void *handle,
+static int ih_v6_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
ih_v6_1_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index a584863f1bed..b5c3e7886167 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -621,7 +621,7 @@ static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block)
return ih_v7_0_hw_init(ip_block);
}
-static bool ih_v7_0_is_idle(void *handle)
+static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -664,10 +664,10 @@ static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
return;
}
-static int ih_v7_0_set_clockgating_state(void *handle,
+static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
ih_v7_0_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index c5f692a45bee..e13d1c2a9378 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -655,9 +655,9 @@ void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
}
}
-static bool jpeg_v2_0_is_idle(void *handle)
+static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
@@ -675,14 +675,14 @@ static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int jpeg_v2_0_set_clockgating_state(void *handle,
+static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
if (enable) {
- if (!jpeg_v2_0_is_idle(handle))
+ if (!jpeg_v2_0_is_idle(ip_block))
return -EBUSY;
jpeg_v2_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index f1ddef8e60ee..091baf408a86 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -482,9 +482,9 @@ static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14)));
}
-static bool jpeg_v2_5_is_idle(void *handle)
+static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
@@ -518,10 +518,10 @@ static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int jpeg_v2_5_set_clockgating_state(void *handle,
+static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
int i;
@@ -530,7 +530,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
continue;
if (enable) {
- if (!jpeg_v2_5_is_idle(handle))
+ if (!jpeg_v2_5_is_idle(ip_block))
return -EBUSY;
jpeg_v2_5_enable_clock_gating(adev, i);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 69f0a9006b96..1f284f1f29d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -445,9 +445,9 @@ static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
}
-static bool jpeg_v3_0_is_idle(void *handle)
+static bool jpeg_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 1;
ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
@@ -466,14 +466,14 @@ static int jpeg_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}
-static int jpeg_v3_0_set_clockgating_state(void *handle,
+static int jpeg_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
if (enable) {
- if (!jpeg_v3_0_is_idle(handle))
+ if (!jpeg_v3_0_is_idle(ip_block))
return -EBUSY;
jpeg_v3_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index e304108d7024..e78135cdddd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -607,9 +607,9 @@ static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
}
-static bool jpeg_v4_0_is_idle(void *handle)
+static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 1;
ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
@@ -628,14 +628,14 @@ static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}
-static int jpeg_v4_0_set_clockgating_state(void *handle,
+static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
if (enable) {
- if (!jpeg_v4_0_is_idle(handle))
+ if (!jpeg_v4_0_is_idle(ip_block))
return -EBUSY;
jpeg_v4_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index f4d6a4768ee2..83c211b48208 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -899,9 +899,9 @@ void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
}
}
-static bool jpeg_v4_0_3_is_idle(void *handle)
+static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool ret = false;
int i, j;
@@ -941,16 +941,16 @@ static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int jpeg_v4_0_3_set_clockgating_state(void *handle,
+static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
int i;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (enable) {
- if (!jpeg_v4_0_3_is_idle(handle))
+ if (!jpeg_v4_0_3_is_idle(ip_block))
return -EBUSY;
jpeg_v4_0_3_enable_clock_gating(adev, i);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index 2a28eb479a34..8f53f3a40084 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -619,9 +619,9 @@ static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
}
-static bool jpeg_v4_0_5_is_idle(void *handle)
+static bool jpeg_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
@@ -652,10 +652,10 @@ static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int jpeg_v4_0_5_set_clockgating_state(void *handle,
+static int jpeg_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
@@ -664,7 +664,7 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
continue;
if (enable) {
- if (!jpeg_v4_0_5_is_idle(handle))
+ if (!jpeg_v4_0_5_is_idle(ip_block))
return -EBUSY;
jpeg_v4_0_5_enable_clock_gating(adev, i);
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 692d0083b5f7..8329692dff07 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -532,9 +532,9 @@ static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
}
}
-static bool jpeg_v5_0_0_is_idle(void *handle)
+static bool jpeg_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 1;
ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
@@ -553,14 +553,14 @@ static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
}
-static int jpeg_v5_0_0_set_clockgating_state(void *handle,
+static int jpeg_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
if (enable) {
- if (!jpeg_v5_0_0_is_idle(handle))
+ if (!jpeg_v5_0_0_is_idle(ip_block))
return -EBUSY;
jpeg_v5_0_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 9ca248ea3428..6094e41d3960 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -626,7 +626,7 @@ static int navi10_ih_resume(struct amdgpu_ip_block *ip_block)
return navi10_ih_hw_init(ip_block);
}
-static bool navi10_ih_is_idle(void *handle)
+static bool navi10_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -667,10 +667,10 @@ static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
}
}
-static int navi10_ih_set_clockgating_state(void *handle,
+static int navi10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
navi10_ih_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 6481f72b32d6..bdad7ec60db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1039,7 +1039,7 @@ static int nv_common_resume(struct amdgpu_ip_block *ip_block)
return nv_common_hw_init(ip_block);
}
-static bool nv_common_is_idle(void *handle)
+static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -1054,10 +1054,10 @@ static int nv_common_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int nv_common_set_clockgating_state(void *handle,
+static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 6a1028baf16d..7cfab1adbcb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -909,9 +909,9 @@ static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block)
return sdma_v2_4_hw_init(ip_block);
}
-static bool sdma_v2_4_is_idle(void *handle)
+static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1080,7 +1080,7 @@ static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int sdma_v2_4_set_clockgating_state(void *handle,
+static int sdma_v2_4_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
/* XXX handled via the smc on VI */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 42d996d4136f..ca8cab33c026 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1198,9 +1198,9 @@ static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v3_0_hw_init(ip_block);
}
-static bool sdma_v3_0_is_idle(void *handle)
+static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
@@ -1483,10 +1483,10 @@ static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
}
}
-static int sdma_v3_0_set_clockgating_state(void *handle,
+static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index a2f5f2be699b..a57c2aedf182 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2015,9 +2015,9 @@ static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v4_0_hw_init(ip_block);
}
-static bool sdma_v4_0_is_idle(void *handle)
+static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -2297,10 +2297,10 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
}
}
-static int sdma_v4_0_set_clockgating_state(void *handle,
+static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 95d5de2bd186..12386220515e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1505,7 +1505,7 @@ static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int sdma_v4_4_2_set_clockgating_state(void *handle,
+static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
@@ -1513,7 +1513,7 @@ static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_in_reset(adev))
- sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
+ sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
return sdma_v4_4_2_hw_fini(ip_block);
}
@@ -1523,9 +1523,9 @@ static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
return sdma_v4_4_2_hw_init(ip_block);
}
-static bool sdma_v4_4_2_is_idle(void *handle)
+static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1812,10 +1812,10 @@ static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
}
}
-static int sdma_v4_4_2_set_clockgating_state(void *handle,
+static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
uint32_t inst_mask;
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 82a8bbd53d49..d4f2ece8c1f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1512,9 +1512,9 @@ static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v5_0_hw_init(ip_block);
}
-static bool sdma_v5_0_is_idle(void *handle)
+static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1835,10 +1835,10 @@ static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev
}
}
-static int sdma_v5_0_set_clockgating_state(void *handle,
+static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b84d5c27bb94..cc1eae69df68 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1412,9 +1412,9 @@ static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block)
return sdma_v5_2_hw_init(ip_block);
}
-static bool sdma_v5_2_is_idle(void *handle)
+static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1789,10 +1789,10 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
}
}
-static int sdma_v5_2_set_clockgating_state(void *handle,
+static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index bc9fe03ab145..911151c3d41b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1410,9 +1410,9 @@ static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v6_0_hw_init(ip_block);
}
-static bool sdma_v6_0_is_idle(void *handle)
+static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1583,7 +1583,7 @@ static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int sdma_v6_0_set_clockgating_state(void *handle,
+static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index c224e7e7e103..d265696553df 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1368,9 +1368,9 @@ static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v7_0_hw_init(ip_block);
}
-static bool sdma_v7_0_is_idle(void *handle)
+static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -1518,7 +1518,7 @@ static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static int sdma_v7_0_set_clockgating_state(void *handle,
+static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 6b0211c94836..8a1100bc4f17 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2660,7 +2660,7 @@ static int si_common_resume(struct amdgpu_ip_block *ip_block)
return si_common_hw_init(ip_block);
}
-static bool si_common_is_idle(void *handle)
+static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -2675,7 +2675,7 @@ static int si_common_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int si_common_set_clockgating_state(void *handle,
+static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 26782dad9311..7527731322f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -541,9 +541,9 @@ static int si_dma_resume(struct amdgpu_ip_block *ip_block)
return si_dma_hw_init(ip_block);
}
-static bool si_dma_is_idle(void *handle)
+static bool si_dma_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(SRBM_STATUS2);
@@ -559,7 +559,7 @@ static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (si_dma_is_idle(adev))
+ if (si_dma_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -629,13 +629,13 @@ static int si_dma_process_trap_irq(struct amdgpu_device *adev,
return 0;
}
-static int si_dma_set_clockgating_state(void *handle,
+static int si_dma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
u32 orig, data, offset;
int i;
bool enable;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
enable = (state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 976d803bef8c..f18887145887 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -210,9 +210,9 @@ static int si_ih_resume(struct amdgpu_ip_block *ip_block)
return si_ih_hw_init(ip_block);
}
-static bool si_ih_is_idle(void *handle)
+static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(SRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
@@ -227,7 +227,7 @@ static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (si_ih_is_idle(adev))
+ if (si_ih_is_idle(ip_block))
return 0;
udelay(1);
}
@@ -263,7 +263,7 @@ static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int si_ih_set_clockgating_state(void *handle,
+static int si_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 9fbada694cd7..c4c5f688ff26 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1334,7 +1334,7 @@ static int soc15_common_resume(struct amdgpu_ip_block *ip_block)
return soc15_common_hw_init(ip_block);
}
-static bool soc15_common_is_idle(void *handle)
+static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -1393,10 +1393,10 @@ static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable
WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
}
-static int soc15_common_set_clockgating_state(void *handle,
+static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 6497a65f9738..1f5f7ab4a304 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -927,7 +927,7 @@ static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
return soc21_common_hw_init(ip_block);
}
-static bool soc21_common_is_idle(void *handle)
+static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -942,10 +942,10 @@ static int soc21_common_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int soc21_common_set_clockgating_state(void *handle,
+static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
case IP_VERSION(4, 3, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 7b43d8908448..1392fc88b857 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -522,7 +522,7 @@ static int soc24_common_resume(struct amdgpu_ip_block *ip_block)
return soc24_common_hw_init(ip_block);
}
-static bool soc24_common_is_idle(void *handle)
+static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -537,10 +537,10 @@ static int soc24_common_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int soc24_common_set_clockgating_state(void *handle,
+static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
case IP_VERSION(6, 3, 1):
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 77fba40e1dbc..d987637b0394 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -353,9 +353,9 @@ static int tonga_ih_resume(struct amdgpu_ip_block *ip_block)
return tonga_ih_hw_init(ip_block);
}
-static bool tonga_ih_is_idle(void *handle)
+static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
@@ -448,7 +448,7 @@ static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int tonga_ih_set_clockgating_state(void *handle,
+static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 561fc15173b6..d5a5a5189ac6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -758,9 +758,9 @@ static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block)
return uvd_v3_1_hw_init(ip_block);
}
-static bool uvd_v3_1_is_idle(void *handle)
+static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
@@ -790,7 +790,7 @@ static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block)
return uvd_v3_1_start(adev);
}
-static int uvd_v3_1_set_clockgating_state(void *handle,
+static int uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 6bd728153b4c..9e3ac12d0127 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -44,7 +44,7 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v4_2_start(struct amdgpu_device *adev);
static void uvd_v4_2_stop(struct amdgpu_device *adev);
-static int uvd_v4_2_set_clockgating_state(void *handle,
+static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
bool sw_mode);
@@ -658,9 +658,9 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
}
-static bool uvd_v4_2_is_idle(void *handle)
+static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
@@ -708,7 +708,7 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int uvd_v4_2_set_clockgating_state(void *handle,
+static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 02e0e5c9e701..a16c99d0b85d 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -42,7 +42,7 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v5_0_start(struct amdgpu_device *adev);
static void uvd_v5_0_stop(struct amdgpu_device *adev);
-static int uvd_v5_0_set_clockgating_state(void *handle,
+static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
bool enable);
@@ -155,7 +155,7 @@ static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
int r;
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
- uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
+ uvd_v5_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
uvd_v5_0_enable_mgcg(adev, true);
r = amdgpu_ring_test_helper(ring);
@@ -580,9 +580,9 @@ static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
}
}
-static bool uvd_v5_0_is_idle(void *handle)
+static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
@@ -790,16 +790,11 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
}
}
-static int uvd_v5_0_set_clockgating_state(void *handle,
+static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
- struct amdgpu_ip_block *ip_block;
-
- ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD);
- if (!ip_block)
- return -EINVAL;
if (enable) {
/* wait for STATUS to clear */
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index fdf23d2b0e42..5da51118a184 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -48,7 +48,7 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v6_0_start(struct amdgpu_device *adev);
static void uvd_v6_0_stop(struct amdgpu_device *adev);
static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
-static int uvd_v6_0_set_clockgating_state(void *handle,
+static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
bool enable);
@@ -467,7 +467,7 @@ static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
int i, r;
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
- uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
+ uvd_v6_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
uvd_v6_0_enable_mgcg(adev, true);
r = amdgpu_ring_test_helper(ring);
@@ -1143,9 +1143,9 @@ static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, vmid);
}
-static bool uvd_v6_0_is_idle(void *handle)
+static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
@@ -1156,7 +1156,7 @@ static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++) {
- if (uvd_v6_0_is_idle(adev))
+ if (uvd_v6_0_is_idle(ip_block))
return 0;
}
return -ETIMEDOUT;
@@ -1450,17 +1450,12 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
}
}
-static int uvd_v6_0_set_clockgating_state(void *handle,
+static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- struct amdgpu_ip_block *ip_block;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
- ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD);
- if (!ip_block)
- return -EINVAL;
-
if (enable) {
/* wait for STATUS to clear */
if (uvd_v6_0_wait_for_idle(ip_block))
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 55fa858328f6..591db2da8067 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1779,7 +1779,7 @@ static int uvd_v7_0_set_powergating_state(void *handle,
}
#endif
-static int uvd_v7_0_set_clockgating_state(void *handle,
+static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
/* needed for driver unload*/
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 836643c99572..f4bd28af41e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -201,9 +201,9 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
}
-static bool vce_v2_0_is_idle(void *handle)
+static bool vce_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}
@@ -214,7 +214,7 @@ static int vce_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
unsigned i;
for (i = 0; i < adev->usec_timeout; i++) {
- if (vce_v2_0_is_idle(adev))
+ if (vce_v2_0_is_idle(ip_block))
return 0;
}
return -ETIMEDOUT;
@@ -578,13 +578,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int vce_v2_0_set_clockgating_state(void *handle,
+static int vce_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
bool gate = false;
bool sw_cg = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_CG_STATE_GATE) {
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index e985cf1e63f1..679033481616 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -65,7 +65,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
-static int vce_v3_0_set_clockgating_state(void *handle,
+static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
/**
* vce_v3_0_ring_get_rptr - get read pointer
@@ -497,7 +497,7 @@ static int vce_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
return r;
vce_v3_0_stop(adev);
- return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
+ return vce_v3_0_set_clockgating_state(ip_block, AMD_CG_STATE_GATE);
}
static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block)
@@ -597,9 +597,9 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
}
-static bool vce_v3_0_is_idle(void *handle)
+static bool vce_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
u32 mask = 0;
mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
@@ -614,7 +614,7 @@ static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
for (i = 0; i < adev->usec_timeout; i++)
- if (vce_v3_0_is_idle(adev))
+ if (vce_v3_0_is_idle(ip_block))
return 0;
return -ETIMEDOUT;
@@ -760,10 +760,10 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int vce_v3_0_set_clockgating_state(void *handle,
+static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 30d64672f3c5..adcbf61411b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -684,7 +684,7 @@ static void vce_v4_0_mc_resume(struct amdgpu_device *adev)
~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
}
-static int vce_v4_0_set_clockgating_state(void *handle,
+static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
/* needed for driver unload*/
@@ -911,10 +911,10 @@ static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
}
-static int vce_v4_0_set_clockgating_state(void *handle,
+static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 34b1e55a907a..37ff3c140e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1377,9 +1377,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
return 0;
}
-static bool vcn_v1_0_is_idle(void *handle)
+static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
@@ -1395,15 +1395,15 @@ static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int vcn_v1_0_set_clockgating_state(void *handle,
+static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
if (enable) {
/* wait for STATUS to clear */
- if (!vcn_v1_0_is_idle(handle))
+ if (!vcn_v1_0_is_idle(ip_block))
return -EBUSY;
vcn_v1_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 6c1f5d05f90a..bda39d2dd7be 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -1317,9 +1317,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
return 0;
}
-static bool vcn_v2_0_is_idle(void *handle)
+static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
@@ -1335,10 +1335,10 @@ static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int vcn_v2_0_set_clockgating_state(void *handle,
+static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
@@ -1346,7 +1346,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
if (enable) {
/* wait for STATUS to clear */
- if (!vcn_v2_0_is_idle(handle))
+ if (!vcn_v2_0_is_idle(ip_block))
return -EBUSY;
vcn_v2_0_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 35ded346771d..aa6c01f5854e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1775,14 +1775,15 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
}
}
-static bool vcn_v2_5_is_idle(void *handle)
+static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
+
ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
@@ -1806,17 +1807,17 @@ static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int vcn_v2_5_set_clockgating_state(void *handle,
+static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
return 0;
if (enable) {
- if (!vcn_v2_5_is_idle(handle))
+ if (!vcn_v2_5_is_idle(ip_block))
return -EBUSY;
vcn_v2_5_enable_clock_gating(adev);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c02c9ef8ddeb..dbe432e765c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2103,9 +2103,9 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
}
}
-static bool vcn_v3_0_is_idle(void *handle)
+static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
@@ -2136,10 +2136,10 @@ static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
return ret;
}
-static int vcn_v3_0_set_clockgating_state(void *handle,
+static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 319eb5a3d061..37e60d6e11b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1959,9 +1959,9 @@ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
*
* Check whether VCN block is idle
*/
-static bool vcn_v4_0_is_idle(void *handle)
+static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
@@ -2007,9 +2007,10 @@ static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
*
* Set VCN block clockgating state
*/
-static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
+static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index b6c1135d6fec..a7aab3102aca 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1553,14 +1553,14 @@ static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
*
* Check whether VCN block is idle
*/
-static bool vcn_v4_0_3_is_idle(void *handle)
+static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
- UVD_STATUS__IDLE);
+ UVD_STATUS__IDLE);
}
return ret;
@@ -1595,10 +1595,10 @@ static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
*
* Set VCN block clockgating state
*/
-static int vcn_v4_0_3_set_clockgating_state(void *handle,
+static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ebf6301b13be..895f82b9e81b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1453,9 +1453,9 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
*
* Check whether VCN block is idle
*/
-static bool vcn_v4_0_5_is_idle(void *handle)
+static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
@@ -1501,9 +1501,10 @@ static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
*
* Set VCN block clockgating state
*/
-static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state)
+static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 50c102f1b5fe..dfc974ff4f6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1180,9 +1180,9 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
*
* Check whether VCN block is idle
*/
-static bool vcn_v5_0_0_is_idle(void *handle)
+static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
@@ -1228,9 +1228,10 @@ static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
*
* Set VCN block clockgating state
*/
-static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
+static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
int i;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 8df4f4352d65..217df1d08cc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -556,7 +556,7 @@ static int vega10_ih_resume(struct amdgpu_ip_block *ip_block)
return vega10_ih_hw_init(ip_block);
}
-static bool vega10_ih_is_idle(void *handle)
+static bool vega10_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -605,10 +605,10 @@ static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
}
}
-static int vega10_ih_set_clockgating_state(void *handle,
+static int vega10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
vega10_ih_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 4ac43aeb85c1..35f1e9fa6430 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -624,7 +624,7 @@ static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)
return vega20_ih_hw_init(ip_block);
}
-static bool vega20_ih_is_idle(void *handle)
+static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
/* todo */
return true;
@@ -670,10 +670,10 @@ static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
}
}
-static int vega20_ih_set_clockgating_state(void *handle,
+static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
vega20_ih_update_clockgating_state(adev,
state == AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 6b58723f0b2e..614f049d88b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1741,7 +1741,7 @@ static int vi_common_resume(struct amdgpu_ip_block *ip_block)
return vi_common_hw_init(ip_block);
}
-static bool vi_common_is_idle(void *handle)
+static bool vi_common_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -1960,10 +1960,10 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
return 0;
}
-static int vi_common_set_clockgating_state(void *handle,
+static int vi_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev))
return 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d5a0417f95df..3297f2ed51af 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -314,7 +314,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
return 0;
}
-static bool dm_is_idle(void *handle)
+static bool dm_is_idle(struct amdgpu_ip_block *ip_block)
{
/* XXX todo */
return true;
@@ -955,7 +955,7 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
}
}
-static int dm_set_clockgating_state(void *handle,
+static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 03c77bbc2e6d..42445413b27b 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -390,13 +390,13 @@ struct amd_ip_funcs {
int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
int (*suspend)(struct amdgpu_ip_block *ip_block);
int (*resume)(struct amdgpu_ip_block *ip_block);
- bool (*is_idle)(void *handle);
+ bool (*is_idle)(struct amdgpu_ip_block *ip_block);
int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*soft_reset)(struct amdgpu_ip_block *ip_block);
int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
- int (*set_clockgating_state)(void *handle,
+ int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state);
int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index d5130da88162..3cafc9493e88 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3094,7 +3094,7 @@ static int kv_dpm_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool kv_dpm_is_idle(void *handle)
+static bool kv_dpm_is_idle(struct amdgpu_ip_block *ip_block)
{
return true;
}
@@ -3188,7 +3188,7 @@ static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int kv_dpm_set_clockgating_state(void *handle,
+static int kv_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 18c47fa89bc1..b61f44844d25 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7837,7 +7837,7 @@ static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
-static bool si_dpm_is_idle(void *handle)
+static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
{
/* XXX */
return true;
@@ -7854,7 +7854,7 @@ static int si_dpm_soft_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int si_dpm_set_clockgating_state(void *handle,
+static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 069b604d6e7a..8b678be90089 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -239,7 +239,7 @@ static void pp_late_fini(struct amdgpu_ip_block *ip_block)
}
-static bool pp_is_idle(void *handle)
+static bool pp_is_idle(struct amdgpu_ip_block *ip_block)
{
return false;
}
@@ -277,7 +277,7 @@ static int pp_resume(struct amdgpu_ip_block *ip_block)
return hwmgr_resume(hwmgr);
}
-static int pp_set_clockgating_state(void *handle,
+static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 4aaaf0e0b851..15310f74c483 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2178,7 +2178,7 @@ static int smu_display_configuration_change(void *handle,
return 0;
}
-static int smu_set_clockgating_state(void *handle,
+static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
enum amd_clockgating_state state)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state
2024-10-17 13:20 ` [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state boyuan.zhang
@ 2024-10-22 7:58 ` Khatri, Sunil
2024-10-25 2:48 ` Boyuan Zhang
0 siblings, 1 reply; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 7:58 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Pass ip_block instead of adev in set_clockgating_state() and is_idle()
> callback functions. Modify set_clockgating_state() and is_idle() ip
> functions for all correspoding ip blocks.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 ++++++------
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/si.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/soc24.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 17 ++++++-----------
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++------------
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 14 +++++++-------
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/vi.c | 6 +++---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
> drivers/gpu/drm/amd/include/amd_shared.h | 4 ++--
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++--
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++--
> .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++--
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
> 82 files changed, 293 insertions(+), 299 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 64828cb7c2f1..5b0856b89801 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -579,7 +579,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool acp_is_idle(void *handle)
> +static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> is_idle isnt used and based on last discussion with christian we left it as it is as this might be removed totally later.
> @@ -594,7 +594,7 @@ static int acp_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int acp_set_clockgating_state(void *handle,
> +static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index fe5de35eef64..af159ebe9cbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2120,7 +2120,7 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
> if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
> continue;
> r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
> - (void *)adev, state);
> + (void *)&adev->ip_blocks[i], state);
> Casting not needed anymore.
> if (r)
> DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
> adev->ip_blocks[i].version->funcs->name, r);
> @@ -3091,7 +3091,7 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
> adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
> adev->ip_blocks[i].version->funcs->set_clockgating_state) {
> /* enable clockgating to save power */
> - r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
> + r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)&adev->ip_blocks[i],
> state);
> if (r) {
> DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> index 844f71eeea27..fc89dee1b972 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> @@ -143,7 +143,7 @@ static int isp_early_init(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool isp_is_idle(void *handle)
> +static bool isp_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> Done need to change is_idle.
> @@ -158,7 +158,7 @@ static int isp_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int isp_set_clockgating_state(void *handle,
> +static int isp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 527470323c33..86a68d5ee05f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -3787,7 +3787,7 @@ int psp_config_sq_perfmon(struct psp_context *psp,
> return ret;
> }
>
> -static int psp_set_clockgating_state(void *handle,
> +static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index f44ce5edba6a..89ee35f980cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -626,7 +626,7 @@ static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block)
> return drm_mode_config_helper_resume(adev_to_drm(ip_block->adev));
> }
>
> -static bool amdgpu_vkms_is_idle(void *handle)
> +static bool amdgpu_vkms_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -641,7 +641,7 @@ static int amdgpu_vkms_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int amdgpu_vkms_set_clockgating_state(void *handle,
> +static int amdgpu_vkms_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> index f3a9ea3f6044..416d1a073173 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> @@ -638,7 +638,7 @@ static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
> return r;
> }
>
> -static int vpe_set_clockgating_state(void *handle,
> +static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 08b398aa6c6d..1f637c7a256d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2163,7 +2163,7 @@ static int cik_common_resume(struct amdgpu_ip_block *ip_block)
> return cik_common_hw_init(ip_block);
> }
>
> -static bool cik_common_is_idle(void *handle)
> +static bool cik_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -2179,7 +2179,7 @@ static int cik_common_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int cik_common_set_clockgating_state(void *handle,
> +static int cik_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 42c3eb8b6a95..a1ad74f6d581 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -345,9 +345,9 @@ static int cik_ih_resume(struct amdgpu_ip_block *ip_block)
> return cik_ih_hw_init(ip_block);
> }
>
> -static bool cik_ih_is_idle(void *handle)
> +static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> @@ -402,7 +402,7 @@ static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int cik_ih_set_clockgating_state(void *handle,
> +static int cik_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 5283b0e94f02..ef352d7be29c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1023,9 +1023,9 @@ static int cik_sdma_resume(struct amdgpu_ip_block *ip_block)
> return cik_sdma_hw_init(ip_block);
> }
>
> -static bool cik_sdma_is_idle(void *handle)
> +static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS2);
>
> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
> @@ -1189,11 +1189,11 @@ static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int cik_sdma_set_clockgating_state(void *handle,
> +static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_CG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 4bf5402bd3aa..c9fa011308d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -341,9 +341,9 @@ static int cz_ih_resume(struct amdgpu_ip_block *ip_block)
> return cz_ih_hw_init(ip_block);
> }
>
> -static bool cz_ih_is_idle(void *handle)
> +static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
> @@ -398,7 +398,7 @@ static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int cz_ih_set_clockgating_state(void *handle,
> +static int cz_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> // TODO
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index e7505934cce2..96acbb56cd4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -2943,7 +2943,7 @@ static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)
> return amdgpu_display_resume_helper(adev);
> }
>
> -static bool dce_v10_0_is_idle(void *handle)
> +static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -3307,7 +3307,7 @@ static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int dce_v10_0_set_clockgating_state(void *handle,
> +static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 8adee675f4d5..48c5270b8a3b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3081,7 +3081,7 @@ static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block)
> return amdgpu_display_resume_helper(adev);
> }
>
> -static bool dce_v11_0_is_idle(void *handle)
> +static bool dce_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -3439,7 +3439,7 @@ static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int dce_v11_0_set_clockgating_state(void *handle,
> +static int dce_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index 66cb19f9b073..65a9fdb36d06 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -2838,7 +2838,7 @@ static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block)
> return amdgpu_display_resume_helper(adev);
> }
>
> -static bool dce_v6_0_is_idle(void *handle)
> +static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -3129,7 +3129,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
>
> }
>
> -static int dce_v6_0_set_clockgating_state(void *handle,
> +static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 57a5207b4e76..c48f8a1fdc4d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -2861,7 +2861,7 @@ static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block)
> return amdgpu_display_resume_helper(adev);
> }
>
> -static bool dce_v8_0_is_idle(void *handle)
> +static bool dce_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -3217,7 +3217,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
>
> }
>
> -static int dce_v8_0_set_clockgating_state(void *handle,
> +static int dce_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index b5da9a1e8216..831beedcbaeb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7486,9 +7486,9 @@ static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v10_0_hw_init(ip_block);
> }
>
> -static bool gfx_v10_0_is_idle(void *handle)
> +static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
> GRBM_STATUS, GUI_ACTIVE))
> @@ -8377,10 +8377,10 @@ static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> return 0;
> }
>
> -static int gfx_v10_0_set_clockgating_state(void *handle,
> +static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 92786e3bbf0e..72ef40a6eb3d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4737,9 +4737,9 @@ static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v11_0_hw_init(ip_block);
> }
>
> -static bool gfx_v11_0_is_idle(void *handle)
> +static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
> GRBM_STATUS, GUI_ACTIVE))
> @@ -5460,10 +5460,10 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> return 0;
> }
>
> -static int gfx_v11_0_set_clockgating_state(void *handle,
> +static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 4ff78c9e3e43..64551c8cea97 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -3653,9 +3653,9 @@ static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v12_0_hw_init(ip_block);
> }
>
> -static bool gfx_v12_0_is_idle(void *handle)
> +static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
> GRBM_STATUS, GUI_ACTIVE))
> @@ -4097,10 +4097,10 @@ static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gfx_v12_0_set_clockgating_state(void *handle,
> +static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 429aa895d6bf..37ce7193701f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3163,9 +3163,9 @@ static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v6_0_hw_init(ip_block);
> }
>
> -static bool gfx_v6_0_is_idle(void *handle)
> +static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
> return false;
> @@ -3179,7 +3179,7 @@ static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (gfx_v6_0_is_idle(adev))
> + if (gfx_v6_0_is_idle(ip_block))
> return 0;
> udelay(1);
> }
> @@ -3378,11 +3378,11 @@ static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gfx_v6_0_set_clockgating_state(void *handle,
> +static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_CG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 7c04dccec8d7..fb8e56472e65 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4509,9 +4509,9 @@ static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v7_0_hw_init(ip_block);
> }
>
> -static bool gfx_v7_0_is_idle(void *handle)
> +static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
> return false;
> @@ -4846,11 +4846,11 @@ static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gfx_v7_0_set_clockgating_state(void *handle,
> +static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_CG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 22ada2ede46b..15db88295288 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4830,9 +4830,9 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
> return r;
> }
>
> -static bool gfx_v8_0_is_idle(void *handle)
> +static bool gfx_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
> || RREG32(mmGRBM_STATUS2) != 0x8)
> @@ -4871,7 +4871,7 @@ static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (gfx_v8_0_is_idle(adev))
> + if (gfx_v8_0_is_idle(ip_block))
> Can continue to use adev is not removing is_idle.
> return 0;
>
> udelay(1);
> @@ -5975,10 +5975,10 @@ static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gfx_v8_0_set_clockgating_state(void *handle,
> +static int gfx_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 6516e88c55aa..bc8853b65787 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4084,9 +4084,9 @@ static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v9_0_hw_init(ip_block);
> }
>
> -static bool gfx_v9_0_is_idle(void *handle)
> +static bool gfx_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
> GRBM_STATUS, GUI_ACTIVE))
> @@ -4101,7 +4101,7 @@ static int gfx_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (gfx_v9_0_is_idle(adev))
> + if (gfx_v9_0_is_idle(ip_block))
> Same as above and other places in this patch.
> return 0;
> udelay(1);
> }
> @@ -5259,10 +5259,10 @@ static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> return 0;
> }
>
> -static int gfx_v9_0_set_clockgating_state(void *handle,
> +static int gfx_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 627652cab308..dd4b62764b23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -2396,9 +2396,9 @@ static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block)
> return gfx_v9_4_3_hw_init(ip_block);
> }
>
> -static bool gfx_v9_4_3_is_idle(void *handle)
> +static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, num_xcc;
>
> num_xcc = NUM_XCC(adev->gfx.xcc_mask);
> @@ -2416,7 +2416,7 @@ static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (gfx_v9_4_3_is_idle(adev))
> + if (gfx_v9_4_3_is_idle(ip_block))
> return 0;
> udelay(1);
> }
> @@ -2766,10 +2766,10 @@ static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> return 0;
> }
>
> -static int gfx_v9_4_3_set_clockgating_state(void *handle,
> +static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, num_xcc;
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index b398021d5b90..22a158091674 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -1073,7 +1073,7 @@ static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v10_0_is_idle(void *handle)
> +static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* MC is always ready in GMC v10.*/
> return true;
> @@ -1090,11 +1090,11 @@ static int gmc_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int gmc_v10_0_set_clockgating_state(void *handle,
> +static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> int r;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> /*
> * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 36e2f4e5a865..53ec799832ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -981,7 +981,7 @@ static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v11_0_is_idle(void *handle)
> +static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* MC is always ready in GMC v11.*/
> return true;
> @@ -998,11 +998,11 @@ static int gmc_v11_0_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int gmc_v11_0_set_clockgating_state(void *handle,
> +static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> int r;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> r = adev->mmhub.funcs->set_clockgating(adev, state);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> index c6510f12afb4..06472c90a58d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> @@ -965,7 +965,7 @@ static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v12_0_is_idle(void *handle)
> +static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* MC is always ready in GMC v11.*/
> return true;
> @@ -982,11 +982,11 @@ static int gmc_v12_0_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int gmc_v12_0_set_clockgating_state(void *handle,
> +static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> int r;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> r = adev->mmhub.funcs->set_clockgating(adev, state);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 3965b9ca8e9c..c7b3b18d6152 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -956,9 +956,9 @@ static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v6_0_is_idle(void *handle)
> +static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> @@ -975,7 +975,7 @@ static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (gmc_v6_0_is_idle(adev))
> + if (gmc_v6_0_is_idle(ip_block))
> return 0;
> udelay(1);
> }
> @@ -1094,7 +1094,7 @@ static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gmc_v6_0_set_clockgating_state(void *handle,
> +static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index b43eaa42e5c7..7d084f98f3b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1131,9 +1131,9 @@ static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v7_0_is_idle(void *handle)
> +static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
> @@ -1307,11 +1307,11 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int gmc_v7_0_set_clockgating_state(void *handle,
> +static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_CG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index d36cf90d4133..ee279518b5db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1262,9 +1262,9 @@ static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v8_0_is_idle(void *handle)
> +static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
> @@ -1658,10 +1658,10 @@ static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
> }
> }
>
> -static int gmc_v8_0_set_clockgating_state(void *handle,
> +static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 5aac51d9db2f..b2b907c82d9b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -2446,7 +2446,7 @@ static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool gmc_v9_0_is_idle(void *handle)
> +static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* MC is always ready in GMC v9.*/
> return true;
> @@ -2464,10 +2464,10 @@ static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int gmc_v9_0_set_clockgating_state(void *handle,
> +static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> adev->mmhub.funcs->set_clockgating(adev, state);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 879d34e88014..784a77e06935 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -335,9 +335,9 @@ static int iceland_ih_resume(struct amdgpu_ip_block *ip_block)
> return iceland_ih_hw_init(ip_block);
> }
>
> -static bool iceland_ih_is_idle(void *handle)
> +static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
> @@ -392,7 +392,7 @@ static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int iceland_ih_set_clockgating_state(void *handle,
> +static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 4f271d9f43ba..47e105659177 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -652,7 +652,7 @@ static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block)
> return ih_v6_0_hw_init(ip_block);
> }
>
> -static bool ih_v6_0_is_idle(void *handle)
> +static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -693,10 +693,10 @@ static void ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,
> }
> }
>
> -static int ih_v6_0_set_clockgating_state(void *handle,
> +static int ih_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> ih_v6_0_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index 5b0a1eaa1fd0..a18778a50272 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -631,7 +631,7 @@ static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block)
> return ih_v6_1_hw_init(ip_block);
> }
>
> -static bool ih_v6_1_is_idle(void *handle)
> +static bool ih_v6_1_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -674,10 +674,10 @@ static void ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
> return;
> }
>
> -static int ih_v6_1_set_clockgating_state(void *handle,
> +static int ih_v6_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> ih_v6_1_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index a584863f1bed..b5c3e7886167 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -621,7 +621,7 @@ static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block)
> return ih_v7_0_hw_init(ip_block);
> }
>
> -static bool ih_v7_0_is_idle(void *handle)
> +static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -664,10 +664,10 @@ static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
> return;
> }
>
> -static int ih_v7_0_set_clockgating_state(void *handle,
> +static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> ih_v7_0_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index c5f692a45bee..e13d1c2a9378 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -655,9 +655,9 @@ void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
> }
> }
>
> -static bool jpeg_v2_0_is_idle(void *handle)
> +static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
> UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
> @@ -675,14 +675,14 @@ static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int jpeg_v2_0_set_clockgating_state(void *handle,
> +static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> if (enable) {
> - if (!jpeg_v2_0_is_idle(handle))
> + if (!jpeg_v2_0_is_idle(ip_block))
> Same as above.
> return -EBUSY;
> jpeg_v2_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index f1ddef8e60ee..091baf408a86 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -482,9 +482,9 @@ static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
> amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14)));
> }
>
> -static bool jpeg_v2_5_is_idle(void *handle)
> +static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
> @@ -518,10 +518,10 @@ static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int jpeg_v2_5_set_clockgating_state(void *handle,
> +static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
> int i;
>
> @@ -530,7 +530,7 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
> continue;
>
> if (enable) {
> - if (!jpeg_v2_5_is_idle(handle))
> + if (!jpeg_v2_5_is_idle(ip_block))
> return -EBUSY;
> jpeg_v2_5_enable_clock_gating(adev, i);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 69f0a9006b96..1f284f1f29d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -445,9 +445,9 @@ static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
> }
> }
>
> -static bool jpeg_v3_0_is_idle(void *handle)
> +static bool jpeg_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 1;
>
> ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
> @@ -466,14 +466,14 @@ static int jpeg_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
> }
>
> -static int jpeg_v3_0_set_clockgating_state(void *handle,
> +static int jpeg_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
>
> if (enable) {
> - if (!jpeg_v3_0_is_idle(handle))
> + if (!jpeg_v3_0_is_idle(ip_block))
> return -EBUSY;
> jpeg_v3_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index e304108d7024..e78135cdddd8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -607,9 +607,9 @@ static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
> }
> }
>
> -static bool jpeg_v4_0_is_idle(void *handle)
> +static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 1;
>
> ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
> @@ -628,14 +628,14 @@ static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
> }
>
> -static int jpeg_v4_0_set_clockgating_state(void *handle,
> +static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
>
> if (enable) {
> - if (!jpeg_v4_0_is_idle(handle))
> + if (!jpeg_v4_0_is_idle(ip_block))
> return -EBUSY;
> jpeg_v4_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index f4d6a4768ee2..83c211b48208 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -899,9 +899,9 @@ void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
> }
> }
>
> -static bool jpeg_v4_0_3_is_idle(void *handle)
> +static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool ret = false;
> int i, j;
>
> @@ -941,16 +941,16 @@ static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int jpeg_v4_0_3_set_clockgating_state(void *handle,
> +static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> int i;
>
> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
> if (enable) {
> - if (!jpeg_v4_0_3_is_idle(handle))
> + if (!jpeg_v4_0_3_is_idle(ip_block))
> return -EBUSY;
> jpeg_v4_0_3_enable_clock_gating(adev, i);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> index 2a28eb479a34..8f53f3a40084 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> @@ -619,9 +619,9 @@ static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
> }
> }
>
> -static bool jpeg_v4_0_5_is_idle(void *handle)
> +static bool jpeg_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
> @@ -652,10 +652,10 @@ static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int jpeg_v4_0_5_set_clockgating_state(void *handle,
> +static int jpeg_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> @@ -664,7 +664,7 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
> continue;
>
> if (enable) {
> - if (!jpeg_v4_0_5_is_idle(handle))
> + if (!jpeg_v4_0_5_is_idle(ip_block))
> return -EBUSY;
>
> jpeg_v4_0_5_enable_clock_gating(adev, i);
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index 692d0083b5f7..8329692dff07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -532,9 +532,9 @@ static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
> }
> }
>
> -static bool jpeg_v5_0_0_is_idle(void *handle)
> +static bool jpeg_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 1;
>
> ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
> @@ -553,14 +553,14 @@ static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
> }
>
> -static int jpeg_v5_0_0_set_clockgating_state(void *handle,
> +static int jpeg_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>
> if (enable) {
> - if (!jpeg_v5_0_0_is_idle(handle))
> + if (!jpeg_v5_0_0_is_idle(ip_block))
> return -EBUSY;
> jpeg_v5_0_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 9ca248ea3428..6094e41d3960 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -626,7 +626,7 @@ static int navi10_ih_resume(struct amdgpu_ip_block *ip_block)
> return navi10_ih_hw_init(ip_block);
> }
>
> -static bool navi10_ih_is_idle(void *handle)
> +static bool navi10_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -667,10 +667,10 @@ static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
> }
> }
>
> -static int navi10_ih_set_clockgating_state(void *handle,
> +static int navi10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> navi10_ih_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 6481f72b32d6..bdad7ec60db4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1039,7 +1039,7 @@ static int nv_common_resume(struct amdgpu_ip_block *ip_block)
> return nv_common_hw_init(ip_block);
> }
>
> -static bool nv_common_is_idle(void *handle)
> +static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -1054,10 +1054,10 @@ static int nv_common_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int nv_common_set_clockgating_state(void *handle,
> +static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 6a1028baf16d..7cfab1adbcb1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -909,9 +909,9 @@ static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v2_4_hw_init(ip_block);
> }
>
> -static bool sdma_v2_4_is_idle(void *handle)
> +static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS2);
>
> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
> @@ -1080,7 +1080,7 @@ static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int sdma_v2_4_set_clockgating_state(void *handle,
> +static int sdma_v2_4_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> /* XXX handled via the smc on VI */
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 42d996d4136f..ca8cab33c026 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1198,9 +1198,9 @@ static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v3_0_hw_init(ip_block);
> }
>
> -static bool sdma_v3_0_is_idle(void *handle)
> +static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS2);
>
> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
> @@ -1483,10 +1483,10 @@ static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
> }
> }
>
> -static int sdma_v3_0_set_clockgating_state(void *handle,
> +static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index a2f5f2be699b..a57c2aedf182 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2015,9 +2015,9 @@ static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v4_0_hw_init(ip_block);
> }
>
> -static bool sdma_v4_0_is_idle(void *handle)
> +static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -2297,10 +2297,10 @@ static void sdma_v4_0_update_medium_grain_light_sleep(
> }
> }
>
> -static int sdma_v4_0_set_clockgating_state(void *handle,
> +static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index 95d5de2bd186..12386220515e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -1505,7 +1505,7 @@ static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int sdma_v4_4_2_set_clockgating_state(void *handle,
> +static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
>
> static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
> @@ -1513,7 +1513,7 @@ static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_in_reset(adev))
> - sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
> + sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
>
> return sdma_v4_4_2_hw_fini(ip_block);
> }
> @@ -1523,9 +1523,9 @@ static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v4_4_2_hw_init(ip_block);
> }
>
> -static bool sdma_v4_4_2_is_idle(void *handle)
> +static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -1812,10 +1812,10 @@ static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
> }
> }
>
> -static int sdma_v4_4_2_set_clockgating_state(void *handle,
> +static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> uint32_t inst_mask;
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 82a8bbd53d49..d4f2ece8c1f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -1512,9 +1512,9 @@ static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v5_0_hw_init(ip_block);
> }
>
> -static bool sdma_v5_0_is_idle(void *handle)
> +static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -1835,10 +1835,10 @@ static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev
> }
> }
>
> -static int sdma_v5_0_set_clockgating_state(void *handle,
> +static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index b84d5c27bb94..cc1eae69df68 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1412,9 +1412,9 @@ static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v5_2_hw_init(ip_block);
> }
>
> -static bool sdma_v5_2_is_idle(void *handle)
> +static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -1789,10 +1789,10 @@ static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
> }
> }
>
> -static int sdma_v5_2_set_clockgating_state(void *handle,
> +static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index bc9fe03ab145..911151c3d41b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1410,9 +1410,9 @@ static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v6_0_hw_init(ip_block);
> }
>
> -static bool sdma_v6_0_is_idle(void *handle)
> +static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -1583,7 +1583,7 @@ static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int sdma_v6_0_set_clockgating_state(void *handle,
> +static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index c224e7e7e103..d265696553df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1368,9 +1368,9 @@ static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block)
> return sdma_v7_0_hw_init(ip_block);
> }
>
> -static bool sdma_v7_0_is_idle(void *handle)
> +static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 i;
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> @@ -1518,7 +1518,7 @@ static int sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int sdma_v7_0_set_clockgating_state(void *handle,
> +static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 6b0211c94836..8a1100bc4f17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -2660,7 +2660,7 @@ static int si_common_resume(struct amdgpu_ip_block *ip_block)
> return si_common_hw_init(ip_block);
> }
>
> -static bool si_common_is_idle(void *handle)
> +static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -2675,7 +2675,7 @@ static int si_common_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int si_common_set_clockgating_state(void *handle,
> +static int si_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 26782dad9311..7527731322f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -541,9 +541,9 @@ static int si_dma_resume(struct amdgpu_ip_block *ip_block)
> return si_dma_hw_init(ip_block);
> }
>
> -static bool si_dma_is_idle(void *handle)
> +static bool si_dma_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> u32 tmp = RREG32(SRBM_STATUS2);
>
> @@ -559,7 +559,7 @@ static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (si_dma_is_idle(adev))
> + if (si_dma_is_idle(ip_block))
> return 0;
> udelay(1);
> }
> @@ -629,13 +629,13 @@ static int si_dma_process_trap_irq(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int si_dma_set_clockgating_state(void *handle,
> +static int si_dma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> u32 orig, data, offset;
> int i;
> bool enable;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> enable = (state == AMD_CG_STATE_GATE);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 976d803bef8c..f18887145887 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -210,9 +210,9 @@ static int si_ih_resume(struct amdgpu_ip_block *ip_block)
> return si_ih_hw_init(ip_block);
> }
>
> -static bool si_ih_is_idle(void *handle)
> +static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(SRBM_STATUS);
>
> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
> @@ -227,7 +227,7 @@ static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (si_ih_is_idle(adev))
> + if (si_ih_is_idle(ip_block))
> return 0;
> udelay(1);
> }
> @@ -263,7 +263,7 @@ static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int si_ih_set_clockgating_state(void *handle,
> +static int si_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 9fbada694cd7..c4c5f688ff26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1334,7 +1334,7 @@ static int soc15_common_resume(struct amdgpu_ip_block *ip_block)
> return soc15_common_hw_init(ip_block);
> }
>
> -static bool soc15_common_is_idle(void *handle)
> +static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -1393,10 +1393,10 @@ static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable
> WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
> }
>
> -static int soc15_common_set_clockgating_state(void *handle,
> +static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 6497a65f9738..1f5f7ab4a304 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -927,7 +927,7 @@ static int soc21_common_resume(struct amdgpu_ip_block *ip_block)
> return soc21_common_hw_init(ip_block);
> }
>
> -static bool soc21_common_is_idle(void *handle)
> +static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -942,10 +942,10 @@ static int soc21_common_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int soc21_common_set_clockgating_state(void *handle,
> +static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
> case IP_VERSION(4, 3, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
> index 7b43d8908448..1392fc88b857 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
> @@ -522,7 +522,7 @@ static int soc24_common_resume(struct amdgpu_ip_block *ip_block)
> return soc24_common_hw_init(ip_block);
> }
>
> -static bool soc24_common_is_idle(void *handle)
> +static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -537,10 +537,10 @@ static int soc24_common_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int soc24_common_set_clockgating_state(void *handle,
> +static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
> case IP_VERSION(6, 3, 1):
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index 77fba40e1dbc..d987637b0394 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -353,9 +353,9 @@ static int tonga_ih_resume(struct amdgpu_ip_block *ip_block)
> return tonga_ih_hw_init(ip_block);
> }
>
> -static bool tonga_ih_is_idle(void *handle)
> +static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 tmp = RREG32(mmSRBM_STATUS);
>
> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
> @@ -448,7 +448,7 @@ static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int tonga_ih_set_clockgating_state(void *handle,
> +static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index 561fc15173b6..d5a5a5189ac6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -758,9 +758,9 @@ static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block)
> return uvd_v3_1_hw_init(ip_block);
> }
>
> -static bool uvd_v3_1_is_idle(void *handle)
> +static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
> }
> @@ -790,7 +790,7 @@ static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block)
> return uvd_v3_1_start(adev);
> }
>
> -static int uvd_v3_1_set_clockgating_state(void *handle,
> +static int uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 6bd728153b4c..9e3ac12d0127 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -44,7 +44,7 @@ static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
> static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
> static int uvd_v4_2_start(struct amdgpu_device *adev);
> static void uvd_v4_2_stop(struct amdgpu_device *adev);
> -static int uvd_v4_2_set_clockgating_state(void *handle,
> +static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
> static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
> bool sw_mode);
> @@ -658,9 +658,9 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
> WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
> }
>
> -static bool uvd_v4_2_is_idle(void *handle)
> +static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
> }
> @@ -708,7 +708,7 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int uvd_v4_2_set_clockgating_state(void *handle,
> +static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 02e0e5c9e701..a16c99d0b85d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -42,7 +42,7 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
> static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
> static int uvd_v5_0_start(struct amdgpu_device *adev);
> static void uvd_v5_0_stop(struct amdgpu_device *adev);
> -static int uvd_v5_0_set_clockgating_state(void *handle,
> +static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
> static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
> bool enable);
> @@ -155,7 +155,7 @@ static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
> int r;
>
> amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
> - uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
> + uvd_v5_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
> uvd_v5_0_enable_mgcg(adev, true);
>
> r = amdgpu_ring_test_helper(ring);
> @@ -580,9 +580,9 @@ static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> }
> }
>
> -static bool uvd_v5_0_is_idle(void *handle)
> +static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
> }
> @@ -790,16 +790,11 @@ static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
> }
> }
>
> -static int uvd_v5_0_set_clockgating_state(void *handle,
> +static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
> - struct amdgpu_ip_block *ip_block;
> -
> - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD);
> - if (!ip_block)
> - return -EINVAL;
>
> if (enable) {
> /* wait for STATUS to clear */
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index fdf23d2b0e42..5da51118a184 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -48,7 +48,7 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
> static int uvd_v6_0_start(struct amdgpu_device *adev);
> static void uvd_v6_0_stop(struct amdgpu_device *adev);
> static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
> -static int uvd_v6_0_set_clockgating_state(void *handle,
> +static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
> static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
> bool enable);
> @@ -467,7 +467,7 @@ static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
> int i, r;
>
> amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
> - uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
> + uvd_v6_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
> uvd_v6_0_enable_mgcg(adev, true);
>
> r = amdgpu_ring_test_helper(ring);
> @@ -1143,9 +1143,9 @@ static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
> amdgpu_ring_write(ring, vmid);
> }
>
> -static bool uvd_v6_0_is_idle(void *handle)
> +static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
> }
> @@ -1156,7 +1156,7 @@ static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (uvd_v6_0_is_idle(adev))
> + if (uvd_v6_0_is_idle(ip_block))
> return 0;
> }
> return -ETIMEDOUT;
> @@ -1450,17 +1450,12 @@ static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
> }
> }
>
> -static int uvd_v6_0_set_clockgating_state(void *handle,
> +static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> - struct amdgpu_ip_block *ip_block;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD);
> - if (!ip_block)
> - return -EINVAL;
> -
> if (enable) {
> /* wait for STATUS to clear */
> if (uvd_v6_0_wait_for_idle(ip_block))
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 55fa858328f6..591db2da8067 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -1779,7 +1779,7 @@ static int uvd_v7_0_set_powergating_state(void *handle,
> }
> #endif
>
> -static int uvd_v7_0_set_clockgating_state(void *handle,
> +static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> /* needed for driver unload*/
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 836643c99572..f4bd28af41e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -201,9 +201,9 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
> WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
> }
>
> -static bool vce_v2_0_is_idle(void *handle)
> +static bool vce_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
> }
> @@ -214,7 +214,7 @@ static int vce_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> unsigned i;
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (vce_v2_0_is_idle(adev))
> + if (vce_v2_0_is_idle(ip_block))
> return 0;
> }
> return -ETIMEDOUT;
> @@ -578,13 +578,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int vce_v2_0_set_clockgating_state(void *handle,
> +static int vce_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> bool gate = false;
> bool sw_cg = false;
>
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_CG_STATE_GATE) {
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index e985cf1e63f1..679033481616 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -65,7 +65,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
> static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
> static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
> static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
> -static int vce_v3_0_set_clockgating_state(void *handle,
> +static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
> /**
> * vce_v3_0_ring_get_rptr - get read pointer
> @@ -497,7 +497,7 @@ static int vce_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
> return r;
>
> vce_v3_0_stop(adev);
> - return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
> + return vce_v3_0_set_clockgating_state(ip_block, AMD_CG_STATE_GATE);
> }
>
> static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block)
> @@ -597,9 +597,9 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
> WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
> }
>
> -static bool vce_v3_0_is_idle(void *handle)
> +static bool vce_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> u32 mask = 0;
>
> mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
> @@ -614,7 +614,7 @@ static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> struct amdgpu_device *adev = ip_block->adev;
>
> for (i = 0; i < adev->usec_timeout; i++)
> - if (vce_v3_0_is_idle(adev))
> + if (vce_v3_0_is_idle(ip_block))
> return 0;
>
> return -ETIMEDOUT;
> @@ -760,10 +760,10 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int vce_v3_0_set_clockgating_state(void *handle,
> +static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 30d64672f3c5..adcbf61411b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -684,7 +684,7 @@ static void vce_v4_0_mc_resume(struct amdgpu_device *adev)
> ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
> }
>
> -static int vce_v4_0_set_clockgating_state(void *handle,
> +static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> /* needed for driver unload*/
> @@ -911,10 +911,10 @@ static void vce_v4_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
> WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
> }
>
> -static int vce_v4_0_set_clockgating_state(void *handle,
> +static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 34b1e55a907a..37ff3c140e81 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1377,9 +1377,9 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
> return 0;
> }
>
> -static bool vcn_v1_0_is_idle(void *handle)
> +static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
> }
> @@ -1395,15 +1395,15 @@ static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int vcn_v1_0_set_clockgating_state(void *handle,
> +static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> if (enable) {
> /* wait for STATUS to clear */
> - if (!vcn_v1_0_is_idle(handle))
> + if (!vcn_v1_0_is_idle(ip_block))
> return -EBUSY;
> vcn_v1_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 6c1f5d05f90a..bda39d2dd7be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -1317,9 +1317,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
> return 0;
> }
>
> -static bool vcn_v2_0_is_idle(void *handle)
> +static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
> }
> @@ -1335,10 +1335,10 @@ static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int vcn_v2_0_set_clockgating_state(void *handle,
> +static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> @@ -1346,7 +1346,7 @@ static int vcn_v2_0_set_clockgating_state(void *handle,
>
> if (enable) {
> /* wait for STATUS to clear */
> - if (!vcn_v2_0_is_idle(handle))
> + if (!vcn_v2_0_is_idle(ip_block))
> return -EBUSY;
> vcn_v2_0_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 35ded346771d..aa6c01f5854e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1775,14 +1775,15 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
> }
> }
>
> -static bool vcn_v2_5_is_idle(void *handle)
> +static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> +
> ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
> }
>
> @@ -1806,17 +1807,17 @@ static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int vcn_v2_5_set_clockgating_state(void *handle,
> +static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> if (enable) {
> - if (!vcn_v2_5_is_idle(handle))
> + if (!vcn_v2_5_is_idle(ip_block))
> return -EBUSY;
> vcn_v2_5_enable_clock_gating(adev);
> } else {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c02c9ef8ddeb..dbe432e765c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2103,9 +2103,9 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
> }
> }
>
> -static bool vcn_v3_0_is_idle(void *handle)
> +static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> @@ -2136,10 +2136,10 @@ static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> return ret;
> }
>
> -static int vcn_v3_0_set_clockgating_state(void *handle,
> +static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 319eb5a3d061..37e60d6e11b5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -1959,9 +1959,9 @@ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
> *
> * Check whether VCN block is idle
> */
> -static bool vcn_v4_0_is_idle(void *handle)
> +static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> @@ -2007,9 +2007,10 @@ static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> *
> * Set VCN block clockgating state
> */
> -static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
> +static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index b6c1135d6fec..a7aab3102aca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1553,14 +1553,14 @@ static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
> *
> * Check whether VCN block is idle
> */
> -static bool vcn_v4_0_3_is_idle(void *handle)
> +static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
> - UVD_STATUS__IDLE);
> + UVD_STATUS__IDLE);
> }
>
> return ret;
> @@ -1595,10 +1595,10 @@ static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
> *
> * Set VCN block clockgating state
> */
> -static int vcn_v4_0_3_set_clockgating_state(void *handle,
> +static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = state == AMD_CG_STATE_GATE;
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index ebf6301b13be..895f82b9e81b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1453,9 +1453,9 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
> *
> * Check whether VCN block is idle
> */
> -static bool vcn_v4_0_5_is_idle(void *handle)
> +static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> @@ -1501,9 +1501,10 @@ static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
> *
> * Set VCN block clockgating state
> */
> -static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_state state)
> +static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 50c102f1b5fe..dfc974ff4f6b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1180,9 +1180,9 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
> *
> * Check whether VCN block is idle
> */
> -static bool vcn_v5_0_0_is_idle(void *handle)
> +static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int i, ret = 1;
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> @@ -1228,9 +1228,10 @@ static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
> *
> * Set VCN block clockgating state
> */
> -static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
> +static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 8df4f4352d65..217df1d08cc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -556,7 +556,7 @@ static int vega10_ih_resume(struct amdgpu_ip_block *ip_block)
> return vega10_ih_hw_init(ip_block);
> }
>
> -static bool vega10_ih_is_idle(void *handle)
> +static bool vega10_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -605,10 +605,10 @@ static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
> }
> }
>
> -static int vega10_ih_set_clockgating_state(void *handle,
> +static int vega10_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> vega10_ih_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> index 4ac43aeb85c1..35f1e9fa6430 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> @@ -624,7 +624,7 @@ static int vega20_ih_resume(struct amdgpu_ip_block *ip_block)
> return vega20_ih_hw_init(ip_block);
> }
>
> -static bool vega20_ih_is_idle(void *handle)
> +static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* todo */
> return true;
> @@ -670,10 +670,10 @@ static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
> }
> }
>
> -static int vega20_ih_set_clockgating_state(void *handle,
> +static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> vega20_ih_update_clockgating_state(adev,
> state == AMD_CG_STATE_GATE);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 6b58723f0b2e..614f049d88b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -1741,7 +1741,7 @@ static int vi_common_resume(struct amdgpu_ip_block *ip_block)
> return vi_common_hw_init(ip_block);
> }
>
> -static bool vi_common_is_idle(void *handle)
> +static bool vi_common_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -1960,10 +1960,10 @@ static int vi_common_set_clockgating_state_by_smu(void *handle,
> return 0;
> }
>
> -static int vi_common_set_clockgating_state(void *handle,
> +static int vi_common_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index d5a0417f95df..3297f2ed51af 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -314,7 +314,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
> return 0;
> }
>
> -static bool dm_is_idle(void *handle)
> +static bool dm_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* XXX todo */
> return true;
> @@ -955,7 +955,7 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
> }
> }
>
> -static int dm_set_clockgating_state(void *handle,
> +static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 03c77bbc2e6d..42445413b27b 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -390,13 +390,13 @@ struct amd_ip_funcs {
> int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
> int (*suspend)(struct amdgpu_ip_block *ip_block);
> int (*resume)(struct amdgpu_ip_block *ip_block);
> - bool (*is_idle)(void *handle);
> + bool (*is_idle)(struct amdgpu_ip_block *ip_block);
> let it be same as original code.
> int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
> bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
> int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
> int (*soft_reset)(struct amdgpu_ip_block *ip_block);
> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
> - int (*set_clockgating_state)(void *handle,
> + int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state);
> int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index d5130da88162..3cafc9493e88 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -3094,7 +3094,7 @@ static int kv_dpm_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool kv_dpm_is_idle(void *handle)
> +static bool kv_dpm_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return true;
> }
> @@ -3188,7 +3188,7 @@ static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int kv_dpm_set_clockgating_state(void *handle,
> +static int kv_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 18c47fa89bc1..b61f44844d25 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -7837,7 +7837,7 @@ static int si_dpm_resume(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static bool si_dpm_is_idle(void *handle)
> +static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
> {
> /* XXX */
> return true;
> @@ -7854,7 +7854,7 @@ static int si_dpm_soft_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int si_dpm_set_clockgating_state(void *handle,
> +static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index 069b604d6e7a..8b678be90089 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -239,7 +239,7 @@ static void pp_late_fini(struct amdgpu_ip_block *ip_block)
> }
>
>
> -static bool pp_is_idle(void *handle)
> +static bool pp_is_idle(struct amdgpu_ip_block *ip_block)
> {
> return false;
> }
> @@ -277,7 +277,7 @@ static int pp_resume(struct amdgpu_ip_block *ip_block)
> return hwmgr_resume(hwmgr);
> }
>
> -static int pp_set_clockgating_state(void *handle,
> +static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 4aaaf0e0b851..15310f74c483 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2178,7 +2178,7 @@ static int smu_display_configuration_change(void *handle,
> return 0;
> }
>
> -static int smu_set_clockgating_state(void *handle,
> +static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
> enum amd_clockgating_state state)
> {
> return 0;
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state
2024-10-22 7:58 ` Khatri, Sunil
@ 2024-10-25 2:48 ` Boyuan Zhang
0 siblings, 0 replies; 45+ messages in thread
From: Boyuan Zhang @ 2024-10-25 2:48 UTC (permalink / raw)
To: Khatri, Sunil, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
On 2024-10-22 03:58, Khatri, Sunil wrote:
>
> On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Pass ip_block instead of adev in set_clockgating_state() and is_idle()
>> callback functions. Modify set_clockgating_state() and is_idle() ip
>> functions for all correspoding ip blocks.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 ++++++------
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/si.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/soc24.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 17 ++++++-----------
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++------------
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 14 +++++++-------
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/vi.c | 6 +++---
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
>> drivers/gpu/drm/amd/include/amd_shared.h | 4 ++--
>> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++--
>> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++--
>> .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++--
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
>> 82 files changed, 293 insertions(+), 299 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> index 64828cb7c2f1..5b0856b89801 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> @@ -579,7 +579,7 @@ static int acp_resume(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static bool acp_is_idle(void *handle)
>> +static bool acp_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> is_idle isnt used and based on last discussion with christian we left
>> it as it is as this might be removed totally later.
>> @@ -594,7 +594,7 @@ static int acp_soft_reset(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static int acp_set_clockgating_state(void *handle,
>> +static int acp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index fe5de35eef64..af159ebe9cbc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -2120,7 +2120,7 @@ int amdgpu_device_ip_set_clockgating_state(void
>> *dev,
>> if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
>> continue;
>> r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
>> - (void *)adev, state);
>> + (void *)&adev->ip_blocks[i], state);
>> Casting not needed anymore.
>> if (r)
>> DRM_ERROR("set_clockgating_state of IP block <%s>
>> failed %d\n",
>> adev->ip_blocks[i].version->funcs->name, r);
>> @@ -3091,7 +3091,7 @@ int amdgpu_device_set_cg_state(struct
>> amdgpu_device *adev,
>> adev->ip_blocks[i].version->type !=
>> AMD_IP_BLOCK_TYPE_JPEG &&
>> adev->ip_blocks[i].version->funcs->set_clockgating_state) {
>> /* enable clockgating to save power */
>> - r =
>> adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
>> + r =
>> adev->ip_blocks[i].version->funcs->set_clockgating_state((void
>> *)&adev->ip_blocks[i],
>> state);
>> if (r) {
>> DRM_ERROR("set_clockgating_state(gate) of IP block
>> <%s> failed %d\n",
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> index 844f71eeea27..fc89dee1b972 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> @@ -143,7 +143,7 @@ static int isp_early_init(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static bool isp_is_idle(void *handle)
>> +static bool isp_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> Done need to change is_idle.
Fixed in new patch-set just submitted (patch 08/29)
>> @@ -158,7 +158,7 @@ static int isp_soft_reset(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static int isp_set_clockgating_state(void *handle,
>> +static int isp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> index 527470323c33..86a68d5ee05f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> @@ -3787,7 +3787,7 @@ int psp_config_sq_perfmon(struct psp_context *psp,
>> return ret;
>> }
>> -static int psp_set_clockgating_state(void *handle,
>> +static int psp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> index f44ce5edba6a..89ee35f980cd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> @@ -626,7 +626,7 @@ static int amdgpu_vkms_resume(struct
>> amdgpu_ip_block *ip_block)
>> return drm_mode_config_helper_resume(adev_to_drm(ip_block->adev));
>> }
>> -static bool amdgpu_vkms_is_idle(void *handle)
>> +static bool amdgpu_vkms_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -641,7 +641,7 @@ static int amdgpu_vkms_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int amdgpu_vkms_set_clockgating_state(void *handle,
>> +static int amdgpu_vkms_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> index f3a9ea3f6044..416d1a073173 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> @@ -638,7 +638,7 @@ static int vpe_ring_preempt_ib(struct amdgpu_ring
>> *ring)
>> return r;
>> }
>> -static int vpe_set_clockgating_state(void *handle,
>> +static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>> index 08b398aa6c6d..1f637c7a256d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>> @@ -2163,7 +2163,7 @@ static int cik_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return cik_common_hw_init(ip_block);
>> }
>> -static bool cik_common_is_idle(void *handle)
>> +static bool cik_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -2179,7 +2179,7 @@ static int cik_common_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int cik_common_set_clockgating_state(void *handle,
>> +static int cik_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index 42c3eb8b6a95..a1ad74f6d581 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -345,9 +345,9 @@ static int cik_ih_resume(struct amdgpu_ip_block
>> *ip_block)
>> return cik_ih_hw_init(ip_block);
>> }
>> -static bool cik_ih_is_idle(void *handle)
>> +static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
>> @@ -402,7 +402,7 @@ static int cik_ih_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int cik_ih_set_clockgating_state(void *handle,
>> +static int cik_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index 5283b0e94f02..ef352d7be29c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -1023,9 +1023,9 @@ static int cik_sdma_resume(struct
>> amdgpu_ip_block *ip_block)
>> return cik_sdma_hw_init(ip_block);
>> }
>> -static bool cik_sdma_is_idle(void *handle)
>> +static bool cik_sdma_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS2);
>> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
>> @@ -1189,11 +1189,11 @@ static int
>> cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int cik_sdma_set_clockgating_state(void *handle,
>> +static int cik_sdma_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_CG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index 4bf5402bd3aa..c9fa011308d9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -341,9 +341,9 @@ static int cz_ih_resume(struct amdgpu_ip_block
>> *ip_block)
>> return cz_ih_hw_init(ip_block);
>> }
>> -static bool cz_ih_is_idle(void *handle)
>> +static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
>> @@ -398,7 +398,7 @@ static int cz_ih_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int cz_ih_set_clockgating_state(void *handle,
>> +static int cz_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> // TODO
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> index e7505934cce2..96acbb56cd4b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> @@ -2943,7 +2943,7 @@ static int dce_v10_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return amdgpu_display_resume_helper(adev);
>> }
>> -static bool dce_v10_0_is_idle(void *handle)
>> +static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -3307,7 +3307,7 @@ static int dce_v10_0_hpd_irq(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int dce_v10_0_set_clockgating_state(void *handle,
>> +static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> index 8adee675f4d5..48c5270b8a3b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> @@ -3081,7 +3081,7 @@ static int dce_v11_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return amdgpu_display_resume_helper(adev);
>> }
>> -static bool dce_v11_0_is_idle(void *handle)
>> +static bool dce_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -3439,7 +3439,7 @@ static int dce_v11_0_hpd_irq(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int dce_v11_0_set_clockgating_state(void *handle,
>> +static int dce_v11_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> index 66cb19f9b073..65a9fdb36d06 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> @@ -2838,7 +2838,7 @@ static int dce_v6_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return amdgpu_display_resume_helper(adev);
>> }
>> -static bool dce_v6_0_is_idle(void *handle)
>> +static bool dce_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -3129,7 +3129,7 @@ static int dce_v6_0_hpd_irq(struct
>> amdgpu_device *adev,
>> }
>> -static int dce_v6_0_set_clockgating_state(void *handle,
>> +static int dce_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> index 57a5207b4e76..c48f8a1fdc4d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> @@ -2861,7 +2861,7 @@ static int dce_v8_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return amdgpu_display_resume_helper(adev);
>> }
>> -static bool dce_v8_0_is_idle(void *handle)
>> +static bool dce_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -3217,7 +3217,7 @@ static int dce_v8_0_hpd_irq(struct
>> amdgpu_device *adev,
>> }
>> -static int dce_v8_0_set_clockgating_state(void *handle,
>> +static int dce_v8_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index b5da9a1e8216..831beedcbaeb 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -7486,9 +7486,9 @@ static int gfx_v10_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v10_0_hw_init(ip_block);
>> }
>> -static bool gfx_v10_0_is_idle(void *handle)
>> +static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
>> GRBM_STATUS, GUI_ACTIVE))
>> @@ -8377,10 +8377,10 @@ static int
>> gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> return 0;
>> }
>> -static int gfx_v10_0_set_clockgating_state(void *handle,
>> +static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index 92786e3bbf0e..72ef40a6eb3d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -4737,9 +4737,9 @@ static int gfx_v11_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v11_0_hw_init(ip_block);
>> }
>> -static bool gfx_v11_0_is_idle(void *handle)
>> +static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
>> GRBM_STATUS, GUI_ACTIVE))
>> @@ -5460,10 +5460,10 @@ static int
>> gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> return 0;
>> }
>> -static int gfx_v11_0_set_clockgating_state(void *handle,
>> +static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> index 4ff78c9e3e43..64551c8cea97 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> @@ -3653,9 +3653,9 @@ static int gfx_v12_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v12_0_hw_init(ip_block);
>> }
>> -static bool gfx_v12_0_is_idle(void *handle)
>> +static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
>> GRBM_STATUS, GUI_ACTIVE))
>> @@ -4097,10 +4097,10 @@ static int
>> gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int gfx_v12_0_set_clockgating_state(void *handle,
>> +static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 429aa895d6bf..37ce7193701f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -3163,9 +3163,9 @@ static int gfx_v6_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v6_0_hw_init(ip_block);
>> }
>> -static bool gfx_v6_0_is_idle(void *handle)
>> +static bool gfx_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
>> return false;
>> @@ -3179,7 +3179,7 @@ static int gfx_v6_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (gfx_v6_0_is_idle(adev))
>> + if (gfx_v6_0_is_idle(ip_block))
>> return 0;
>> udelay(1);
>> }
>> @@ -3378,11 +3378,11 @@ static int gfx_v6_0_priv_inst_irq(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int gfx_v6_0_set_clockgating_state(void *handle,
>> +static int gfx_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_CG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index 7c04dccec8d7..fb8e56472e65 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -4509,9 +4509,9 @@ static int gfx_v7_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v7_0_hw_init(ip_block);
>> }
>> -static bool gfx_v7_0_is_idle(void *handle)
>> +static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
>> return false;
>> @@ -4846,11 +4846,11 @@ static int gfx_v7_0_priv_inst_irq(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int gfx_v7_0_set_clockgating_state(void *handle,
>> +static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_CG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 22ada2ede46b..15db88295288 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -4830,9 +4830,9 @@ static int gfx_v8_0_kcq_disable(struct
>> amdgpu_device *adev)
>> return r;
>> }
>> -static bool gfx_v8_0_is_idle(void *handle)
>> +static bool gfx_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS,
>> GUI_ACTIVE)
>> || RREG32(mmGRBM_STATUS2) != 0x8)
>> @@ -4871,7 +4871,7 @@ static int gfx_v8_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (gfx_v8_0_is_idle(adev))
>> + if (gfx_v8_0_is_idle(ip_block))
>> Can continue to use adev is not removing is_idle.
>> return 0;
>> udelay(1);
>> @@ -5975,10 +5975,10 @@ static int
>> gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int gfx_v8_0_set_clockgating_state(void *handle,
>> +static int gfx_v8_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 6516e88c55aa..bc8853b65787 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -4084,9 +4084,9 @@ static int gfx_v9_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v9_0_hw_init(ip_block);
>> }
>> -static bool gfx_v9_0_is_idle(void *handle)
>> +static bool gfx_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
>> GRBM_STATUS, GUI_ACTIVE))
>> @@ -4101,7 +4101,7 @@ static int gfx_v9_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (gfx_v9_0_is_idle(adev))
>> + if (gfx_v9_0_is_idle(ip_block))
>> Same as above and other places in this patch.
>> return 0;
>> udelay(1);
>> }
>> @@ -5259,10 +5259,10 @@ static int
>> gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> return 0;
>> }
>> -static int gfx_v9_0_set_clockgating_state(void *handle,
>> +static int gfx_v9_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> index 627652cab308..dd4b62764b23 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> @@ -2396,9 +2396,9 @@ static int gfx_v9_4_3_resume(struct
>> amdgpu_ip_block *ip_block)
>> return gfx_v9_4_3_hw_init(ip_block);
>> }
>> -static bool gfx_v9_4_3_is_idle(void *handle)
>> +static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, num_xcc;
>> num_xcc = NUM_XCC(adev->gfx.xcc_mask);
>> @@ -2416,7 +2416,7 @@ static int gfx_v9_4_3_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (gfx_v9_4_3_is_idle(adev))
>> + if (gfx_v9_4_3_is_idle(ip_block))
>> return 0;
>> udelay(1);
>> }
>> @@ -2766,10 +2766,10 @@ static int
>> gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> return 0;
>> }
>> -static int gfx_v9_4_3_set_clockgating_state(void *handle,
>> +static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, num_xcc;
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> index b398021d5b90..22a158091674 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> @@ -1073,7 +1073,7 @@ static int gmc_v10_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v10_0_is_idle(void *handle)
>> +static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* MC is always ready in GMC v10.*/
>> return true;
>> @@ -1090,11 +1090,11 @@ static int gmc_v10_0_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int gmc_v10_0_set_clockgating_state(void *handle,
>> +static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> int r;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> /*
>> * The issue mmhub can't disconnect from DF with MMHUB clock
>> gating being disabled
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> index 36e2f4e5a865..53ec799832ca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> @@ -981,7 +981,7 @@ static int gmc_v11_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v11_0_is_idle(void *handle)
>> +static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* MC is always ready in GMC v11.*/
>> return true;
>> @@ -998,11 +998,11 @@ static int gmc_v11_0_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int gmc_v11_0_set_clockgating_state(void *handle,
>> +static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> int r;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> r = adev->mmhub.funcs->set_clockgating(adev, state);
>> if (r)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> index c6510f12afb4..06472c90a58d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> @@ -965,7 +965,7 @@ static int gmc_v12_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v12_0_is_idle(void *handle)
>> +static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* MC is always ready in GMC v11.*/
>> return true;
>> @@ -982,11 +982,11 @@ static int gmc_v12_0_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int gmc_v12_0_set_clockgating_state(void *handle,
>> +static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> int r;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> r = adev->mmhub.funcs->set_clockgating(adev, state);
>> if (r)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index 3965b9ca8e9c..c7b3b18d6152 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -956,9 +956,9 @@ static int gmc_v6_0_resume(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static bool gmc_v6_0_is_idle(void *handle)
>> +static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> @@ -975,7 +975,7 @@ static int gmc_v6_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (gmc_v6_0_is_idle(adev))
>> + if (gmc_v6_0_is_idle(ip_block))
>> return 0;
>> udelay(1);
>> }
>> @@ -1094,7 +1094,7 @@ static int gmc_v6_0_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int gmc_v6_0_set_clockgating_state(void *handle,
>> +static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index b43eaa42e5c7..7d084f98f3b6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -1131,9 +1131,9 @@ static int gmc_v7_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v7_0_is_idle(void *handle)
>> +static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (tmp & (SRBM_STATUS__MCB_BUSY_MASK |
>> SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
>> @@ -1307,11 +1307,11 @@ static int gmc_v7_0_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int gmc_v7_0_set_clockgating_state(void *handle,
>> +static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_CG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index d36cf90d4133..ee279518b5db 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -1262,9 +1262,9 @@ static int gmc_v8_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v8_0_is_idle(void *handle)
>> +static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (tmp & (SRBM_STATUS__MCB_BUSY_MASK |
>> SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
>> @@ -1658,10 +1658,10 @@ static void fiji_update_mc_light_sleep(struct
>> amdgpu_device *adev,
>> }
>> }
>> -static int gmc_v8_0_set_clockgating_state(void *handle,
>> +static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 5aac51d9db2f..b2b907c82d9b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -2446,7 +2446,7 @@ static int gmc_v9_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static bool gmc_v9_0_is_idle(void *handle)
>> +static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* MC is always ready in GMC v9.*/
>> return true;
>> @@ -2464,10 +2464,10 @@ static int gmc_v9_0_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int gmc_v9_0_set_clockgating_state(void *handle,
>> +static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> adev->mmhub.funcs->set_clockgating(adev, state);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index 879d34e88014..784a77e06935 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -335,9 +335,9 @@ static int iceland_ih_resume(struct
>> amdgpu_ip_block *ip_block)
>> return iceland_ih_hw_init(ip_block);
>> }
>> -static bool iceland_ih_is_idle(void *handle)
>> +static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
>> @@ -392,7 +392,7 @@ static int iceland_ih_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int iceland_ih_set_clockgating_state(void *handle,
>> +static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> index 4f271d9f43ba..47e105659177 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> @@ -652,7 +652,7 @@ static int ih_v6_0_resume(struct amdgpu_ip_block
>> *ip_block)
>> return ih_v6_0_hw_init(ip_block);
>> }
>> -static bool ih_v6_0_is_idle(void *handle)
>> +static bool ih_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -693,10 +693,10 @@ static void
>> ih_v6_0_update_clockgating_state(struct amdgpu_device *adev,
>> }
>> }
>> -static int ih_v6_0_set_clockgating_state(void *handle,
>> +static int ih_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> ih_v6_0_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> index 5b0a1eaa1fd0..a18778a50272 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> @@ -631,7 +631,7 @@ static int ih_v6_1_resume(struct amdgpu_ip_block
>> *ip_block)
>> return ih_v6_1_hw_init(ip_block);
>> }
>> -static bool ih_v6_1_is_idle(void *handle)
>> +static bool ih_v6_1_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -674,10 +674,10 @@ static void
>> ih_v6_1_update_clockgating_state(struct amdgpu_device *adev,
>> return;
>> }
>> -static int ih_v6_1_set_clockgating_state(void *handle,
>> +static int ih_v6_1_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> ih_v6_1_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> index a584863f1bed..b5c3e7886167 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> @@ -621,7 +621,7 @@ static int ih_v7_0_resume(struct amdgpu_ip_block
>> *ip_block)
>> return ih_v7_0_hw_init(ip_block);
>> }
>> -static bool ih_v7_0_is_idle(void *handle)
>> +static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -664,10 +664,10 @@ static void
>> ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
>> return;
>> }
>> -static int ih_v7_0_set_clockgating_state(void *handle,
>> +static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> ih_v7_0_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> index c5f692a45bee..e13d1c2a9378 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> @@ -655,9 +655,9 @@ void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring
>> *ring, uint32_t count)
>> }
>> }
>> -static bool jpeg_v2_0_is_idle(void *handle)
>> +static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
>> UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
>> @@ -675,14 +675,14 @@ static int jpeg_v2_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int jpeg_v2_0_set_clockgating_state(void *handle,
>> +static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> if (enable) {
>> - if (!jpeg_v2_0_is_idle(handle))
>> + if (!jpeg_v2_0_is_idle(ip_block))
>> Same as above.
>> return -EBUSY;
>> jpeg_v2_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> index f1ddef8e60ee..091baf408a86 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> @@ -482,9 +482,9 @@ static void jpeg_v2_6_dec_ring_insert_end(struct
>> amdgpu_ring *ring)
>> amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14)));
>> }
>> -static bool jpeg_v2_5_is_idle(void *handle)
>> +static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
>> @@ -518,10 +518,10 @@ static int jpeg_v2_5_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int jpeg_v2_5_set_clockgating_state(void *handle,
>> +static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> int i;
>> @@ -530,7 +530,7 @@ static int jpeg_v2_5_set_clockgating_state(void
>> *handle,
>> continue;
>> if (enable) {
>> - if (!jpeg_v2_5_is_idle(handle))
>> + if (!jpeg_v2_5_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v2_5_enable_clock_gating(adev, i);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> index 69f0a9006b96..1f284f1f29d2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> @@ -445,9 +445,9 @@ static void jpeg_v3_0_dec_ring_set_wptr(struct
>> amdgpu_ring *ring)
>> }
>> }
>> -static bool jpeg_v3_0_is_idle(void *handle)
>> +static bool jpeg_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 1;
>> ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
>> @@ -466,14 +466,14 @@ static int jpeg_v3_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
>> }
>> -static int jpeg_v3_0_set_clockgating_state(void *handle,
>> +static int jpeg_v3_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> if (enable) {
>> - if (!jpeg_v3_0_is_idle(handle))
>> + if (!jpeg_v3_0_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v3_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> index e304108d7024..e78135cdddd8 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> @@ -607,9 +607,9 @@ static void jpeg_v4_0_dec_ring_set_wptr(struct
>> amdgpu_ring *ring)
>> }
>> }
>> -static bool jpeg_v4_0_is_idle(void *handle)
>> +static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 1;
>> ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
>> @@ -628,14 +628,14 @@ static int jpeg_v4_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
>> }
>> -static int jpeg_v4_0_set_clockgating_state(void *handle,
>> +static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> if (enable) {
>> - if (!jpeg_v4_0_is_idle(handle))
>> + if (!jpeg_v4_0_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v4_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> index f4d6a4768ee2..83c211b48208 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> @@ -899,9 +899,9 @@ void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring
>> *ring, uint32_t count)
>> }
>> }
>> -static bool jpeg_v4_0_3_is_idle(void *handle)
>> +static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool ret = false;
>> int i, j;
>> @@ -941,16 +941,16 @@ static int jpeg_v4_0_3_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int jpeg_v4_0_3_set_clockgating_state(void *handle,
>> +static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> int i;
>> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
>> if (enable) {
>> - if (!jpeg_v4_0_3_is_idle(handle))
>> + if (!jpeg_v4_0_3_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v4_0_3_enable_clock_gating(adev, i);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> index 2a28eb479a34..8f53f3a40084 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> @@ -619,9 +619,9 @@ static void jpeg_v4_0_5_dec_ring_set_wptr(struct
>> amdgpu_ring *ring)
>> }
>> }
>> -static bool jpeg_v4_0_5_is_idle(void *handle)
>> +static bool jpeg_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
>> @@ -652,10 +652,10 @@ static int jpeg_v4_0_5_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int jpeg_v4_0_5_set_clockgating_state(void *handle,
>> +static int jpeg_v4_0_5_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>> int i;
>> @@ -664,7 +664,7 @@ static int
>> jpeg_v4_0_5_set_clockgating_state(void *handle,
>> continue;
>> if (enable) {
>> - if (!jpeg_v4_0_5_is_idle(handle))
>> + if (!jpeg_v4_0_5_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v4_0_5_enable_clock_gating(adev, i);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> index 692d0083b5f7..8329692dff07 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> @@ -532,9 +532,9 @@ static void jpeg_v5_0_0_dec_ring_set_wptr(struct
>> amdgpu_ring *ring)
>> }
>> }
>> -static bool jpeg_v5_0_0_is_idle(void *handle)
>> +static bool jpeg_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 1;
>> ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
>> @@ -553,14 +553,14 @@ static int jpeg_v5_0_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
>> }
>> -static int jpeg_v5_0_0_set_clockgating_state(void *handle,
>> +static int jpeg_v5_0_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>> if (enable) {
>> - if (!jpeg_v5_0_0_is_idle(handle))
>> + if (!jpeg_v5_0_0_is_idle(ip_block))
>> return -EBUSY;
>> jpeg_v5_0_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index 9ca248ea3428..6094e41d3960 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -626,7 +626,7 @@ static int navi10_ih_resume(struct
>> amdgpu_ip_block *ip_block)
>> return navi10_ih_hw_init(ip_block);
>> }
>> -static bool navi10_ih_is_idle(void *handle)
>> +static bool navi10_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -667,10 +667,10 @@ static void
>> navi10_ih_update_clockgating_state(struct amdgpu_device *adev,
>> }
>> }
>> -static int navi10_ih_set_clockgating_state(void *handle,
>> +static int navi10_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> navi10_ih_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 6481f72b32d6..bdad7ec60db4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -1039,7 +1039,7 @@ static int nv_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return nv_common_hw_init(ip_block);
>> }
>> -static bool nv_common_is_idle(void *handle)
>> +static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -1054,10 +1054,10 @@ static int nv_common_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int nv_common_set_clockgating_state(void *handle,
>> +static int nv_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> index 6a1028baf16d..7cfab1adbcb1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> @@ -909,9 +909,9 @@ static int sdma_v2_4_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v2_4_hw_init(ip_block);
>> }
>> -static bool sdma_v2_4_is_idle(void *handle)
>> +static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS2);
>> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
>> @@ -1080,7 +1080,7 @@ static int
>> sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int sdma_v2_4_set_clockgating_state(void *handle,
>> +static int sdma_v2_4_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> /* XXX handled via the smc on VI */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index 42d996d4136f..ca8cab33c026 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -1198,9 +1198,9 @@ static int sdma_v3_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v3_0_hw_init(ip_block);
>> }
>> -static bool sdma_v3_0_is_idle(void *handle)
>> +static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS2);
>> if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
>> @@ -1483,10 +1483,10 @@ static void
>> sdma_v3_0_update_sdma_medium_grain_light_sleep(
>> }
>> }
>> -static int sdma_v3_0_set_clockgating_state(void *handle,
>> +static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index a2f5f2be699b..a57c2aedf182 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -2015,9 +2015,9 @@ static int sdma_v4_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v4_0_hw_init(ip_block);
>> }
>> -static bool sdma_v4_0_is_idle(void *handle)
>> +static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -2297,10 +2297,10 @@ static void
>> sdma_v4_0_update_medium_grain_light_sleep(
>> }
>> }
>> -static int sdma_v4_0_set_clockgating_state(void *handle,
>> +static int sdma_v4_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> index 95d5de2bd186..12386220515e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> @@ -1505,7 +1505,7 @@ static int sdma_v4_4_2_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int sdma_v4_4_2_set_clockgating_state(void *handle,
>> +static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state);
>> static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
>> @@ -1513,7 +1513,7 @@ static int sdma_v4_4_2_suspend(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_in_reset(adev))
>> - sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
>> + sdma_v4_4_2_set_clockgating_state(ip_block,
>> AMD_CG_STATE_UNGATE);
>> return sdma_v4_4_2_hw_fini(ip_block);
>> }
>> @@ -1523,9 +1523,9 @@ static int sdma_v4_4_2_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v4_4_2_hw_init(ip_block);
>> }
>> -static bool sdma_v4_4_2_is_idle(void *handle)
>> +static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -1812,10 +1812,10 @@ static void
>> sdma_v4_4_2_inst_update_medium_grain_clock_gating(
>> }
>> }
>> -static int sdma_v4_4_2_set_clockgating_state(void *handle,
>> +static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> uint32_t inst_mask;
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> index 82a8bbd53d49..d4f2ece8c1f5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> @@ -1512,9 +1512,9 @@ static int sdma_v5_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v5_0_hw_init(ip_block);
>> }
>> -static bool sdma_v5_0_is_idle(void *handle)
>> +static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -1835,10 +1835,10 @@ static void
>> sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev
>> }
>> }
>> -static int sdma_v5_0_set_clockgating_state(void *handle,
>> +static int sdma_v5_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> index b84d5c27bb94..cc1eae69df68 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> @@ -1412,9 +1412,9 @@ static int sdma_v5_2_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v5_2_hw_init(ip_block);
>> }
>> -static bool sdma_v5_2_is_idle(void *handle)
>> +static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -1789,10 +1789,10 @@ static void
>> sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>> }
>> }
>> -static int sdma_v5_2_set_clockgating_state(void *handle,
>> +static int sdma_v5_2_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> index bc9fe03ab145..911151c3d41b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> @@ -1410,9 +1410,9 @@ static int sdma_v6_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v6_0_hw_init(ip_block);
>> }
>> -static bool sdma_v6_0_is_idle(void *handle)
>> +static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -1583,7 +1583,7 @@ static int
>> sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int sdma_v6_0_set_clockgating_state(void *handle,
>> +static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> index c224e7e7e103..d265696553df 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> @@ -1368,9 +1368,9 @@ static int sdma_v7_0_resume(struct
>> amdgpu_ip_block *ip_block)
>> return sdma_v7_0_hw_init(ip_block);
>> }
>> -static bool sdma_v7_0_is_idle(void *handle)
>> +static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 i;
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> @@ -1518,7 +1518,7 @@ static int
>> sdma_v7_0_process_illegal_inst_irq(struct amdgpu_device *adev,
>> return 0;
>> }
>> -static int sdma_v7_0_set_clockgating_state(void *handle,
>> +static int sdma_v7_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
>> b/drivers/gpu/drm/amd/amdgpu/si.c
>> index 6b0211c94836..8a1100bc4f17 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
>> @@ -2660,7 +2660,7 @@ static int si_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return si_common_hw_init(ip_block);
>> }
>> -static bool si_common_is_idle(void *handle)
>> +static bool si_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -2675,7 +2675,7 @@ static int si_common_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int si_common_set_clockgating_state(void *handle,
>> +static int si_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> index 26782dad9311..7527731322f4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> @@ -541,9 +541,9 @@ static int si_dma_resume(struct amdgpu_ip_block
>> *ip_block)
>> return si_dma_hw_init(ip_block);
>> }
>> -static bool si_dma_is_idle(void *handle)
>> +static bool si_dma_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(SRBM_STATUS2);
>> @@ -559,7 +559,7 @@ static int si_dma_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (si_dma_is_idle(adev))
>> + if (si_dma_is_idle(ip_block))
>> return 0;
>> udelay(1);
>> }
>> @@ -629,13 +629,13 @@ static int si_dma_process_trap_irq(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int si_dma_set_clockgating_state(void *handle,
>> +static int si_dma_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> u32 orig, data, offset;
>> int i;
>> bool enable;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> enable = (state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index 976d803bef8c..f18887145887 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -210,9 +210,9 @@ static int si_ih_resume(struct amdgpu_ip_block
>> *ip_block)
>> return si_ih_hw_init(ip_block);
>> }
>> -static bool si_ih_is_idle(void *handle)
>> +static bool si_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(SRBM_STATUS);
>> if (tmp & SRBM_STATUS__IH_BUSY_MASK)
>> @@ -227,7 +227,7 @@ static int si_ih_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (si_ih_is_idle(adev))
>> + if (si_ih_is_idle(ip_block))
>> return 0;
>> udelay(1);
>> }
>> @@ -263,7 +263,7 @@ static int si_ih_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int si_ih_set_clockgating_state(void *handle,
>> +static int si_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index 9fbada694cd7..c4c5f688ff26 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -1334,7 +1334,7 @@ static int soc15_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return soc15_common_hw_init(ip_block);
>> }
>> -static bool soc15_common_is_idle(void *handle)
>> +static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -1393,10 +1393,10 @@ static void
>> soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable
>> WREG32(SOC15_REG_OFFSET(MP0, 0,
>> mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
>> }
>> -static int soc15_common_set_clockgating_state(void *handle,
>> +static int soc15_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> index 6497a65f9738..1f5f7ab4a304 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> @@ -927,7 +927,7 @@ static int soc21_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return soc21_common_hw_init(ip_block);
>> }
>> -static bool soc21_common_is_idle(void *handle)
>> +static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -942,10 +942,10 @@ static int soc21_common_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int soc21_common_set_clockgating_state(void *handle,
>> +static int soc21_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
>> case IP_VERSION(4, 3, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> index 7b43d8908448..1392fc88b857 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> @@ -522,7 +522,7 @@ static int soc24_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return soc24_common_hw_init(ip_block);
>> }
>> -static bool soc24_common_is_idle(void *handle)
>> +static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -537,10 +537,10 @@ static int soc24_common_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int soc24_common_set_clockgating_state(void *handle,
>> +static int soc24_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
>> case IP_VERSION(6, 3, 1):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index 77fba40e1dbc..d987637b0394 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -353,9 +353,9 @@ static int tonga_ih_resume(struct amdgpu_ip_block
>> *ip_block)
>> return tonga_ih_hw_init(ip_block);
>> }
>> -static bool tonga_ih_is_idle(void *handle)
>> +static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 tmp = RREG32(mmSRBM_STATUS);
>> if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
>> @@ -448,7 +448,7 @@ static int tonga_ih_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int tonga_ih_set_clockgating_state(void *handle,
>> +static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> index 561fc15173b6..d5a5a5189ac6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> @@ -758,9 +758,9 @@ static int uvd_v3_1_resume(struct amdgpu_ip_block
>> *ip_block)
>> return uvd_v3_1_hw_init(ip_block);
>> }
>> -static bool uvd_v3_1_is_idle(void *handle)
>> +static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
>> }
>> @@ -790,7 +790,7 @@ static int uvd_v3_1_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return uvd_v3_1_start(adev);
>> }
>> -static int uvd_v3_1_set_clockgating_state(void *handle,
>> +static int uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> index 6bd728153b4c..9e3ac12d0127 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> @@ -44,7 +44,7 @@ static void uvd_v4_2_set_ring_funcs(struct
>> amdgpu_device *adev);
>> static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
>> static int uvd_v4_2_start(struct amdgpu_device *adev);
>> static void uvd_v4_2_stop(struct amdgpu_device *adev);
>> -static int uvd_v4_2_set_clockgating_state(void *handle,
>> +static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state);
>> static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
>> bool sw_mode);
>> @@ -658,9 +658,9 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device
>> *adev,
>> WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
>> }
>> -static bool uvd_v4_2_is_idle(void *handle)
>> +static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
>> }
>> @@ -708,7 +708,7 @@ static int uvd_v4_2_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int uvd_v4_2_set_clockgating_state(void *handle,
>> +static int uvd_v4_2_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> index 02e0e5c9e701..a16c99d0b85d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> @@ -42,7 +42,7 @@ static void uvd_v5_0_set_ring_funcs(struct
>> amdgpu_device *adev);
>> static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
>> static int uvd_v5_0_start(struct amdgpu_device *adev);
>> static void uvd_v5_0_stop(struct amdgpu_device *adev);
>> -static int uvd_v5_0_set_clockgating_state(void *handle,
>> +static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state);
>> static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
>> bool enable);
>> @@ -155,7 +155,7 @@ static int uvd_v5_0_hw_init(struct
>> amdgpu_ip_block *ip_block)
>> int r;
>> amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
>> - uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
>> + uvd_v5_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
>> uvd_v5_0_enable_mgcg(adev, true);
>> r = amdgpu_ring_test_helper(ring);
>> @@ -580,9 +580,9 @@ static void uvd_v5_0_ring_insert_nop(struct
>> amdgpu_ring *ring, uint32_t count)
>> }
>> }
>> -static bool uvd_v5_0_is_idle(void *handle)
>> +static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
>> }
>> @@ -790,16 +790,11 @@ static void uvd_v5_0_enable_mgcg(struct
>> amdgpu_device *adev,
>> }
>> }
>> -static int uvd_v5_0_set_clockgating_state(void *handle,
>> +static int uvd_v5_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> - struct amdgpu_ip_block *ip_block;
>> -
>> - ip_block = amdgpu_device_ip_get_ip_block(adev,
>> AMD_IP_BLOCK_TYPE_UVD);
>> - if (!ip_block)
>> - return -EINVAL;
>> if (enable) {
>> /* wait for STATUS to clear */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index fdf23d2b0e42..5da51118a184 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -48,7 +48,7 @@ static void uvd_v6_0_set_irq_funcs(struct
>> amdgpu_device *adev);
>> static int uvd_v6_0_start(struct amdgpu_device *adev);
>> static void uvd_v6_0_stop(struct amdgpu_device *adev);
>> static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
>> -static int uvd_v6_0_set_clockgating_state(void *handle,
>> +static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state);
>> static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
>> bool enable);
>> @@ -467,7 +467,7 @@ static int uvd_v6_0_hw_init(struct
>> amdgpu_ip_block *ip_block)
>> int i, r;
>> amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
>> - uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
>> + uvd_v6_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
>> uvd_v6_0_enable_mgcg(adev, true);
>> r = amdgpu_ring_test_helper(ring);
>> @@ -1143,9 +1143,9 @@ static void
>> uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>> amdgpu_ring_write(ring, vmid);
>> }
>> -static bool uvd_v6_0_is_idle(void *handle)
>> +static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
>> }
>> @@ -1156,7 +1156,7 @@ static int uvd_v6_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (uvd_v6_0_is_idle(adev))
>> + if (uvd_v6_0_is_idle(ip_block))
>> return 0;
>> }
>> return -ETIMEDOUT;
>> @@ -1450,17 +1450,12 @@ static void uvd_v6_0_enable_mgcg(struct
>> amdgpu_device *adev,
>> }
>> }
>> -static int uvd_v6_0_set_clockgating_state(void *handle,
>> +static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> - struct amdgpu_ip_block *ip_block;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> - ip_block = amdgpu_device_ip_get_ip_block(adev,
>> AMD_IP_BLOCK_TYPE_UVD);
>> - if (!ip_block)
>> - return -EINVAL;
>> -
>> if (enable) {
>> /* wait for STATUS to clear */
>> if (uvd_v6_0_wait_for_idle(ip_block))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index 55fa858328f6..591db2da8067 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -1779,7 +1779,7 @@ static int uvd_v7_0_set_powergating_state(void
>> *handle,
>> }
>> #endif
>> -static int uvd_v7_0_set_clockgating_state(void *handle,
>> +static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> /* needed for driver unload*/
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> index 836643c99572..f4bd28af41e1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> @@ -201,9 +201,9 @@ static void vce_v2_0_mc_resume(struct
>> amdgpu_device *adev)
>> WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
>> }
>> -static bool vce_v2_0_is_idle(void *handle)
>> +static bool vce_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
>> }
>> @@ -214,7 +214,7 @@ static int vce_v2_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> unsigned i;
>> for (i = 0; i < adev->usec_timeout; i++) {
>> - if (vce_v2_0_is_idle(adev))
>> + if (vce_v2_0_is_idle(ip_block))
>> return 0;
>> }
>> return -ETIMEDOUT;
>> @@ -578,13 +578,13 @@ static int vce_v2_0_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int vce_v2_0_set_clockgating_state(void *handle,
>> +static int vce_v2_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> bool gate = false;
>> bool sw_cg = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_CG_STATE_GATE) {
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> index e985cf1e63f1..679033481616 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> @@ -65,7 +65,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device
>> *adev, int idx);
>> static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
>> static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>> static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
>> -static int vce_v3_0_set_clockgating_state(void *handle,
>> +static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state);
>> /**
>> * vce_v3_0_ring_get_rptr - get read pointer
>> @@ -497,7 +497,7 @@ static int vce_v3_0_hw_fini(struct
>> amdgpu_ip_block *ip_block)
>> return r;
>> vce_v3_0_stop(adev);
>> - return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
>> + return vce_v3_0_set_clockgating_state(ip_block, AMD_CG_STATE_GATE);
>> }
>> static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block)
>> @@ -597,9 +597,9 @@ static void vce_v3_0_mc_resume(struct
>> amdgpu_device *adev, int idx)
>> WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
>> }
>> -static bool vce_v3_0_is_idle(void *handle)
>> +static bool vce_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> u32 mask = 0;
>> mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0)
>> ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
>> @@ -614,7 +614,7 @@ static int vce_v3_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> struct amdgpu_device *adev = ip_block->adev;
>> for (i = 0; i < adev->usec_timeout; i++)
>> - if (vce_v3_0_is_idle(adev))
>> + if (vce_v3_0_is_idle(ip_block))
>> return 0;
>> return -ETIMEDOUT;
>> @@ -760,10 +760,10 @@ static int vce_v3_0_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int vce_v3_0_set_clockgating_state(void *handle,
>> +static int vce_v3_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index 30d64672f3c5..adcbf61411b5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -684,7 +684,7 @@ static void vce_v4_0_mc_resume(struct
>> amdgpu_device *adev)
>> ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
>> }
>> -static int vce_v4_0_set_clockgating_state(void *handle,
>> +static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> /* needed for driver unload*/
>> @@ -911,10 +911,10 @@ static void vce_v4_0_set_bypass_mode(struct
>> amdgpu_device *adev, bool enable)
>> WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
>> }
>> -static int vce_v4_0_set_clockgating_state(void *handle,
>> +static int vce_v4_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> index 34b1e55a907a..37ff3c140e81 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> @@ -1377,9 +1377,9 @@ static int vcn_v1_0_pause_dpg_mode(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static bool vcn_v1_0_is_idle(void *handle)
>> +static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
>> }
>> @@ -1395,15 +1395,15 @@ static int vcn_v1_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int vcn_v1_0_set_clockgating_state(void *handle,
>> +static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> if (enable) {
>> /* wait for STATUS to clear */
>> - if (!vcn_v1_0_is_idle(handle))
>> + if (!vcn_v1_0_is_idle(ip_block))
>> return -EBUSY;
>> vcn_v1_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index 6c1f5d05f90a..bda39d2dd7be 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -1317,9 +1317,9 @@ static int vcn_v2_0_pause_dpg_mode(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static bool vcn_v2_0_is_idle(void *handle)
>> +static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
>> }
>> @@ -1335,10 +1335,10 @@ static int vcn_v2_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int vcn_v2_0_set_clockgating_state(void *handle,
>> +static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> @@ -1346,7 +1346,7 @@ static int vcn_v2_0_set_clockgating_state(void
>> *handle,
>> if (enable) {
>> /* wait for STATUS to clear */
>> - if (!vcn_v2_0_is_idle(handle))
>> + if (!vcn_v2_0_is_idle(ip_block))
>> return -EBUSY;
>> vcn_v2_0_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index 35ded346771d..aa6c01f5854e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -1775,14 +1775,15 @@ static void
>> vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
>> }
>> }
>> -static bool vcn_v2_5_is_idle(void *handle)
>> +static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> +
>> ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) ==
>> UVD_STATUS__IDLE);
>> }
>> @@ -1806,17 +1807,17 @@ static int vcn_v2_5_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int vcn_v2_5_set_clockgating_state(void *handle,
>> +static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> if (enable) {
>> - if (!vcn_v2_5_is_idle(handle))
>> + if (!vcn_v2_5_is_idle(ip_block))
>> return -EBUSY;
>> vcn_v2_5_enable_clock_gating(adev);
>> } else {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index c02c9ef8ddeb..dbe432e765c1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -2103,9 +2103,9 @@ static void vcn_v3_0_set_enc_ring_funcs(struct
>> amdgpu_device *adev)
>> }
>> }
>> -static bool vcn_v3_0_is_idle(void *handle)
>> +static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> @@ -2136,10 +2136,10 @@ static int vcn_v3_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> return ret;
>> }
>> -static int vcn_v3_0_set_clockgating_state(void *handle,
>> +static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> index 319eb5a3d061..37e60d6e11b5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> @@ -1959,9 +1959,9 @@ static void
>> vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
>> *
>> * Check whether VCN block is idle
>> */
>> -static bool vcn_v4_0_is_idle(void *handle)
>> +static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> @@ -2007,9 +2007,10 @@ static int vcn_v4_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> *
>> * Set VCN block clockgating state
>> */
>> -static int vcn_v4_0_set_clockgating_state(void *handle, enum
>> amd_clockgating_state state)
>> +static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index b6c1135d6fec..a7aab3102aca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -1553,14 +1553,14 @@ static void
>> vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
>> *
>> * Check whether VCN block is idle
>> */
>> -static bool vcn_v4_0_3_is_idle(void *handle)
>> +static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
>> - UVD_STATUS__IDLE);
>> + UVD_STATUS__IDLE);
>> }
>> return ret;
>> @@ -1595,10 +1595,10 @@ static int vcn_v4_0_3_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> *
>> * Set VCN block clockgating state
>> */
>> -static int vcn_v4_0_3_set_clockgating_state(void *handle,
>> +static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = state == AMD_CG_STATE_GATE;
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> index ebf6301b13be..895f82b9e81b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> @@ -1453,9 +1453,9 @@ static void
>> vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
>> *
>> * Check whether VCN block is idle
>> */
>> -static bool vcn_v4_0_5_is_idle(void *handle)
>> +static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> @@ -1501,9 +1501,10 @@ static int vcn_v4_0_5_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> *
>> * Set VCN block clockgating state
>> */
>> -static int vcn_v4_0_5_set_clockgating_state(void *handle, enum
>> amd_clockgating_state state)
>> +static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> index 50c102f1b5fe..dfc974ff4f6b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> @@ -1180,9 +1180,9 @@ static void
>> vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
>> *
>> * Check whether VCN block is idle
>> */
>> -static bool vcn_v5_0_0_is_idle(void *handle)
>> +static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int i, ret = 1;
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> @@ -1228,9 +1228,10 @@ static int vcn_v5_0_0_wait_for_idle(struct
>> amdgpu_ip_block *ip_block)
>> *
>> * Set VCN block clockgating state
>> */
>> -static int vcn_v5_0_0_set_clockgating_state(void *handle, enum
>> amd_clockgating_state state)
>> +static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>> int i;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> index 8df4f4352d65..217df1d08cc3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> @@ -556,7 +556,7 @@ static int vega10_ih_resume(struct
>> amdgpu_ip_block *ip_block)
>> return vega10_ih_hw_init(ip_block);
>> }
>> -static bool vega10_ih_is_idle(void *handle)
>> +static bool vega10_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -605,10 +605,10 @@ static void
>> vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
>> }
>> }
>> -static int vega10_ih_set_clockgating_state(void *handle,
>> +static int vega10_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> vega10_ih_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> index 4ac43aeb85c1..35f1e9fa6430 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> @@ -624,7 +624,7 @@ static int vega20_ih_resume(struct
>> amdgpu_ip_block *ip_block)
>> return vega20_ih_hw_init(ip_block);
>> }
>> -static bool vega20_ih_is_idle(void *handle)
>> +static bool vega20_ih_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* todo */
>> return true;
>> @@ -670,10 +670,10 @@ static void
>> vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
>> }
>> }
>> -static int vega20_ih_set_clockgating_state(void *handle,
>> +static int vega20_ih_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> vega20_ih_update_clockgating_state(adev,
>> state == AMD_CG_STATE_GATE);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
>> b/drivers/gpu/drm/amd/amdgpu/vi.c
>> index 6b58723f0b2e..614f049d88b9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -1741,7 +1741,7 @@ static int vi_common_resume(struct
>> amdgpu_ip_block *ip_block)
>> return vi_common_hw_init(ip_block);
>> }
>> -static bool vi_common_is_idle(void *handle)
>> +static bool vi_common_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -1960,10 +1960,10 @@ static int
>> vi_common_set_clockgating_state_by_smu(void *handle,
>> return 0;
>> }
>> -static int vi_common_set_clockgating_state(void *handle,
>> +static int vi_common_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index d5a0417f95df..3297f2ed51af 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -314,7 +314,7 @@ static int dm_crtc_get_scanoutpos(struct
>> amdgpu_device *adev, int crtc,
>> return 0;
>> }
>> -static bool dm_is_idle(void *handle)
>> +static bool dm_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* XXX todo */
>> return true;
>> @@ -955,7 +955,7 @@ static void dm_dmub_outbox1_low_irq(void
>> *interrupt_params)
>> }
>> }
>> -static int dm_set_clockgating_state(void *handle,
>> +static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
>> b/drivers/gpu/drm/amd/include/amd_shared.h
>> index 03c77bbc2e6d..42445413b27b 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -390,13 +390,13 @@ struct amd_ip_funcs {
>> int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
>> int (*suspend)(struct amdgpu_ip_block *ip_block);
>> int (*resume)(struct amdgpu_ip_block *ip_block);
>> - bool (*is_idle)(void *handle);
>> + bool (*is_idle)(struct amdgpu_ip_block *ip_block);
>> let it be same as original code.
>> int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
>> bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
>> int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
>> int (*soft_reset)(struct amdgpu_ip_block *ip_block);
>> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
>> - int (*set_clockgating_state)(void *handle,
>> + int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state);
>> int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state);
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> index d5130da88162..3cafc9493e88 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> @@ -3094,7 +3094,7 @@ static int kv_dpm_resume(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static bool kv_dpm_is_idle(void *handle)
>> +static bool kv_dpm_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return true;
>> }
>> @@ -3188,7 +3188,7 @@ static int kv_dpm_process_interrupt(struct
>> amdgpu_device *adev,
>> return 0;
>> }
>> -static int kv_dpm_set_clockgating_state(void *handle,
>> +static int kv_dpm_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> index 18c47fa89bc1..b61f44844d25 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> @@ -7837,7 +7837,7 @@ static int si_dpm_resume(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static bool si_dpm_is_idle(void *handle)
>> +static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> /* XXX */
>> return true;
>> @@ -7854,7 +7854,7 @@ static int si_dpm_soft_reset(struct
>> amdgpu_ip_block *ip_block)
>> return 0;
>> }
>> -static int si_dpm_set_clockgating_state(void *handle,
>> +static int si_dpm_set_clockgating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> index 069b604d6e7a..8b678be90089 100644
>> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> @@ -239,7 +239,7 @@ static void pp_late_fini(struct amdgpu_ip_block
>> *ip_block)
>> }
>> -static bool pp_is_idle(void *handle)
>> +static bool pp_is_idle(struct amdgpu_ip_block *ip_block)
>> {
>> return false;
>> }
>> @@ -277,7 +277,7 @@ static int pp_resume(struct amdgpu_ip_block
>> *ip_block)
>> return hwmgr_resume(hwmgr);
>> }
>> -static int pp_set_clockgating_state(void *handle,
>> +static int pp_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 4aaaf0e0b851..15310f74c483 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -2178,7 +2178,7 @@ static int
>> smu_display_configuration_change(void *handle,
>> return 0;
>> }
>> -static int smu_set_clockgating_state(void *handle,
>> +static int smu_set_clockgating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_clockgating_state state)
>> {
>> return 0;
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 09/32] drm/amdgpu: track instances of the same IP block
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (7 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 10/32] drm/amdgpu: move per inst variables to amdgpu_vcn_inst boyuan.zhang
` (23 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add a new function to count the number of instance of the same IP block
in the current ip_block list, then use the returned count value to set
the newly defined instance variable in ip_block, to track the instance
number of each ip_block.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 +++++++++++++++++++++-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 48c9b9b06905..3442564fe174 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -387,6 +387,7 @@ struct amdgpu_ip_block {
struct amdgpu_ip_block_status status;
const struct amdgpu_ip_block_version *version;
struct amdgpu_device *adev;
+ unsigned int instance;
};
int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index af159ebe9cbc..426beab725b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2283,6 +2283,28 @@ int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
return 1;
}
+/**
+ * amdgpu_device_ip_get_num_instances - get number of instances of an IP block
+ *
+ * @adev: amdgpu_device pointer
+ * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
+ *
+ * Returns the count of the hardware IP blocks structure for that type.
+ */
+static unsigned int
+amdgpu_device_ip_get_num_instances(struct amdgpu_device *adev,
+ enum amd_ip_block_type type)
+{
+ unsigned int i, count = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->type == type)
+ count++;
+ }
+
+ return count;
+}
+
/**
* amdgpu_device_ip_block_add
*
@@ -2315,7 +2337,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
ip_block_version->funcs->name);
adev->ip_blocks[adev->num_ip_blocks].adev = adev;
-
+ adev->ip_blocks[adev->num_ip_blocks].instance =
+ amdgpu_device_ip_get_num_instances(adev, ip_block_version->type);
adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 10/32] drm/amdgpu: move per inst variables to amdgpu_vcn_inst
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (8 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 09/32] drm/amdgpu: track instances of the same IP block boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 11/32] drm/amdgpu/vcn: separate gating state by instance boyuan.zhang
` (22 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Move all per instance variables from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.fw[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_config[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_codec_disable_mask[i] from amdgpu_vcn to amdgpu_vcn_inst.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +++++++++----------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++--
11 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 9f9a1867da72..71f5ee9f6031 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1340,7 +1340,7 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
*/
if (adev->vcn.num_vcn_inst <
AMDGPU_MAX_VCN_INSTANCES) {
- adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
+ adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
ip->revision & 0xc0;
adev->vcn.num_vcn_inst++;
adev->vcn.inst_mask |=
@@ -1705,7 +1705,7 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
* so this won't overflow.
*/
for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
- adev->vcn.vcn_codec_disable_mask[v] =
+ adev->vcn.inst[v].vcn_codec_disable_mask =
le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
}
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 43f44cc201cb..7ebcab8d1bd2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -99,11 +99,11 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev)
amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
- r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s_%d.bin", ucode_prefix, i);
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s_%d.bin", ucode_prefix, i);
else
- r = amdgpu_ucode_request(adev, &adev->vcn.fw[i], "amdgpu/%s.bin", ucode_prefix);
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s.bin", ucode_prefix);
if (r) {
- amdgpu_ucode_release(&adev->vcn.fw[i]);
+ amdgpu_ucode_release(&adev->vcn.inst[i].fw);
return r;
}
}
@@ -151,7 +151,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
adev->vcn.using_unified_queue =
amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);
- hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[0].fw->data;
adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
/* Bit 20-23, it is encode major and non-zero for new naming convention.
@@ -270,7 +270,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
- amdgpu_ucode_release(&adev->vcn.fw[j]);
+ amdgpu_ucode_release(&adev->vcn.inst[j].fw);
}
mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
@@ -282,7 +282,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
{
bool ret = false;
- int vcn_config = adev->vcn.vcn_config[vcn_instance];
+ int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK))
ret = true;
@@ -356,12 +356,12 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
const struct common_firmware_header *hdr;
unsigned int offset;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
memcpy_toio(adev->vcn.inst[i].cpu_addr,
- adev->vcn.fw[i]->data + offset,
+ adev->vcn.inst[i].fw->data + offset,
le32_to_cpu(hdr->ucode_size_bytes));
drm_dev_exit(idx);
}
@@ -1057,7 +1057,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << i))
continue;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[i]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
/* currently only support 2 FW instances */
if (i >= 2) {
dev_info(adev->dev, "More then 2 VCN FW instances!\n");
@@ -1065,7 +1065,7 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
}
idx = AMDGPU_UCODE_ID_VCN + i;
adev->firmware.ucode[idx].ucode_id = idx;
- adev->firmware.ucode[idx].fw = adev->vcn.fw[i];
+ adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
adev->firmware.fw_size +=
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2a1f3dbb14d3..fc2efa53f3f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -297,6 +297,9 @@ struct amdgpu_vcn_inst {
atomic_t dpg_enc_submission_cnt;
struct amdgpu_vcn_fw_shared fw_shared;
uint8_t aid_id;
+ const struct firmware *fw; /* VCN firmware */
+ uint8_t vcn_config;
+ uint32_t vcn_codec_disable_mask;
};
struct amdgpu_vcn_ras {
@@ -306,15 +309,12 @@ struct amdgpu_vcn_ras {
struct amdgpu_vcn {
unsigned fw_version;
struct delayed_work idle_work;
- const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */
unsigned num_enc_rings;
enum amd_powergating_state cur_state;
bool indirect_sram;
uint8_t num_vcn_inst;
struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
- uint8_t vcn_config[AMDGPU_MAX_VCN_INSTANCES];
- uint32_t vcn_codec_disable_mask[AMDGPU_MAX_VCN_INSTANCES];
struct amdgpu_vcn_reg internal;
struct mutex vcn_pg_lock;
struct mutex vcn1_jpeg1_workaround;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 37ff3c140e81..553ad1efef03 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -345,7 +345,7 @@ static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
*/
static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
@@ -412,7 +412,7 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index bda39d2dd7be..670b8b4c89f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -372,7 +372,7 @@ static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
*/
static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
uint32_t offset;
if (amdgpu_sriov_vf(adev))
@@ -428,7 +428,7 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
@@ -1920,7 +1920,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
init_table += header->vcn_table_offset;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4);
+ size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index aa6c01f5854e..f9d34b8de874 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -466,7 +466,7 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
if (adev->vcn.harvest_config & (1 << i))
continue;
- size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
+ size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
@@ -515,7 +515,7 @@ static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
@@ -1288,7 +1288,7 @@ static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
- size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
+ size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
/* mc resume*/
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
MMSCH_V1_0_INSERT_DIRECT_WT(
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index dbe432e765c1..79e5adddd97c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -490,7 +490,7 @@ static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block)
*/
static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
@@ -540,7 +540,7 @@ static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
{
- uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4);
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4);
uint32_t offset;
/* cache window 0: fw */
@@ -1375,7 +1375,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
mmUVD_STATUS),
~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
- cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
+ cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 37e60d6e11b5..8ab02e5bcdd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -422,7 +422,7 @@ static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
@@ -482,7 +482,7 @@ static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
{
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
@@ -1334,7 +1334,7 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
regUVD_STATUS),
~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
- cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
+ cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index a7aab3102aca..323ad6e34a15 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -377,7 +377,7 @@ static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)
uint32_t offset, size, vcn_inst;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
vcn_inst = GET_INST(VCN, inst_idx);
@@ -452,7 +452,7 @@ static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
@@ -939,7 +939,7 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
- cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
+ cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 895f82b9e81b..eceed8cdb3bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -370,7 +370,7 @@ static void vcn_v4_0_5_mc_resume(struct amdgpu_device *adev, int inst)
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
@@ -431,7 +431,7 @@ static void vcn_v4_0_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index dfc974ff4f6b..234f245e2792 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -334,7 +334,7 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
@@ -395,7 +395,7 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
uint32_t offset, size;
const struct common_firmware_header *hdr;
- hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data;
size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
/* cache window 0: fw */
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 11/32] drm/amdgpu/vcn: separate gating state by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (9 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 10/32] drm/amdgpu: move per inst variables to amdgpu_vcn_inst boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 12/32] drm/amdgpu: power vcn 2_5 " boyuan.zhang
` (21 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
vcn gating state should now be based on instance. For example, instance 0
can be gated while instance 1 is ungated, or vice versa.
Therefore, change the cur_state to be an array, so that it can track the
gating status for each vcn instance now.
v2: remove redundant codes in v1.
v3: move cur_state from amdgpu_vcn to amdgou_vcn_inst since it's a per
instance variable.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 ++++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 29 ++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 25 +++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 ++++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +++++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 24 +++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 24 +++++++++---------
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
10 files changed, 84 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index fc2efa53f3f4..0d882ba59b22 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -298,6 +298,7 @@ struct amdgpu_vcn_inst {
struct amdgpu_vcn_fw_shared fw_shared;
uint8_t aid_id;
const struct firmware *fw; /* VCN firmware */
+ enum amd_powergating_state cur_state;
uint8_t vcn_config;
uint32_t vcn_codec_disable_mask;
};
@@ -310,7 +311,6 @@ struct amdgpu_vcn {
unsigned fw_version;
struct delayed_work idle_work;
unsigned num_enc_rings;
- enum amd_powergating_state cur_state;
bool indirect_sram;
uint8_t num_vcn_inst;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 553ad1efef03..407b0b5146cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -280,7 +280,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
@@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
int ret;
struct amdgpu_device *adev = ip_block->adev;
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1822,7 +1822,8 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v1_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[0].cur_state = state;
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 670b8b4c89f9..03eaae64c356 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -316,7 +316,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
@@ -1810,11 +1810,11 @@ static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.inst[0].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1823,7 +1823,8 @@ static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v2_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[0].cur_state = state;
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index f9d34b8de874..8f9e5535429f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -388,24 +388,22 @@ static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
- vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
- amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, inst, mmUVD_STATUS))) {
+ vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
+ amdgpu_irq_put(adev, &adev->vcn.inst[inst].ras_poison_irq, 0);
+
return 0;
}
@@ -1831,12 +1829,13 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
if (amdgpu_sriov_vf(adev))
return 0;
- if(state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1844,8 +1843,8 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
else
ret = vcn_v2_5_start(adev);
- if(!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 79e5adddd97c..a5648089ba05 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -420,20 +420,18 @@ static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (!amdgpu_sriov_vf(adev)) {
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
- vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
- }
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, inst, mmUVD_STATUS))) {
+ vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
@@ -2163,6 +2161,7 @@ static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
@@ -2170,11 +2169,11 @@ static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.inst[inst].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -2183,7 +2182,7 @@ static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v3_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 8ab02e5bcdd0..14640d9352a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -348,24 +348,24 @@ static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (!amdgpu_sriov_vf(adev)) {
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, inst, regUVD_STATUS))) {
+ vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
- if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
- amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
}
+ if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
+ amdgpu_irq_put(adev, &adev->vcn.inst[inst].ras_poison_irq, 0);
+
return 0;
}
@@ -2042,6 +2042,7 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
@@ -2049,11 +2050,11 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.inst[inst].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -2062,7 +2063,7 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v4_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 323ad6e34a15..ef246bf9d15c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -315,10 +315,11 @@ static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
+ if (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE)
vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
@@ -1627,6 +1628,7 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
/* for SRIOV, guest should not control VCN Power-gating
@@ -1634,11 +1636,11 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
* guest should avoid touching CGC and PG
*/
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.inst[inst].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1647,7 +1649,7 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v4_0_3_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index eceed8cdb3bb..f0e48e9bd839 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -298,19 +298,18 @@ static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (!amdgpu_sriov_vf(adev)) {
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, inst, regUVD_STATUS))) {
+ vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
@@ -1536,9 +1535,10 @@ static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1547,7 +1547,7 @@ static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v4_0_5_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 234f245e2792..8e716165cc03 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -262,19 +262,18 @@ static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
cancel_delayed_work_sync(&adev->vcn.idle_work);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (!amdgpu_sriov_vf(adev)) {
- if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ if (!amdgpu_sriov_vf(adev)) {
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, inst, regUVD_STATUS))) {
+ vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
@@ -1263,9 +1262,10 @@ static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[inst].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1274,7 +1274,7 @@ static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
ret = vcn_v5_0_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[inst].cur_state = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 15310f74c483..61c700e2c47f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2034,7 +2034,8 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block)
smu_dpm_set_vpe_enable(smu, false);
smu_dpm_set_umsch_mm_enable(smu, false);
- adev->vcn.cur_state = AMD_PG_STATE_GATE;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ adev->vcn.inst[i].cur_state = AMD_PG_STATE_GATE;
adev->jpeg.cur_state = AMD_PG_STATE_GATE;
if (!smu->pm_enabled)
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 12/32] drm/amdgpu: power vcn 2_5 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (10 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 11/32] drm/amdgpu/vcn: separate gating state by instance boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 13/32] drm/amdgpu: power vcn 3_0 " boyuan.zhang
` (20 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 2_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 565 +++++++++---------
2 files changed, 281 insertions(+), 289 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 71f5ee9f6031..eb77eef60368 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2278,6 +2278,8 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
{
+ int i;
+
if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
case IP_VERSION(7, 0, 0):
@@ -2321,7 +2323,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(2, 0, 3):
break;
case IP_VERSION(2, 5, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
break;
case IP_VERSION(2, 6, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 8f9e5535429f..9162c7fcefc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -158,35 +158,34 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
uint32_t *ptr;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- /* VCN DEC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
- if (r)
- return r;
-
- /* VCN ENC TRAP */
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
- if (r)
- return r;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto sw_init;
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
+ /* VCN ENC TRAP */
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
if (r)
return r;
}
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
+sw_init:
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -197,76 +196,74 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
- adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
- adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
-
- adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
- adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
- adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
- adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
- adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
-
- ring = &adev->vcn.inst[j].ring_dec;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.scratch9 = SOC15_REG_OFFSET(VCN, inst, mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data0 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data1 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.cmd = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.nop = SOC15_REG_OFFSET(VCN, inst, mmUVD_NO_OP);
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ ring->use_doorbell = true;
+
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ (amdgpu_sriov_vf(adev) ? 2*inst : 8*inst);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
+ ring->vm_hub = AMDGPU_MMHUB1(0);
+ else
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+
+ sprintf(ring->name, "vcn_dec_%d", inst);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq,
+ 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
+ if (r)
+ return r;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
+
+ ring = &adev->vcn.inst[inst].ring_enc[i];
ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
+ (amdgpu_sriov_vf(adev) ? (1 + i + 2*inst) : (2 + i + 8*inst));
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(2, 5, 0))
ring->vm_hub = AMDGPU_MMHUB1(0);
else
ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_dec_%d", j);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
- 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
+ sprintf(ring->name, "vcn_enc_%d.%d", inst, i);
+ r = amdgpu_ring_init(adev, ring, 512,
+ &adev->vcn.inst[inst].irq, 0,
+ hw_prio, NULL);
if (r)
return r;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
-
- ring = &adev->vcn.inst[j].ring_enc[i];
- ring->use_doorbell = true;
-
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(2, 5, 0))
- ring->vm_hub = AMDGPU_MMHUB1(0);
- else
- ring->vm_hub = AMDGPU_MMHUB0(0);
-
- sprintf(ring->name, "vcn_enc_%d.%d", j, i);
- r = amdgpu_ring_init(adev, ring, 512,
- &adev->vcn.inst[j].irq, 0,
- hw_prio, NULL);
- if (r)
- return r;
- }
-
- fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
-
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
}
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1005,197 +1002,192 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
return 0;
}
-static int vcn_v2_5_start(struct amdgpu_device *adev)
+static int vcn_v2_5_start(struct amdgpu_device *adev, unsigned int inst)
{
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
- int i, j, k, r;
+ int j, k, r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
- }
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
- /* disable register anti-hang mechanism */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
- ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- /* set uvd status busy */
- tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_5_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
+ /* disable register anti-hang mechanism */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS), 0,
+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+
+ /* set uvd status busy */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, tmp);
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return 0;
/*SW clock gating */
vcn_v2_5_disable_clock_gating(adev);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* setup mmUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
- tmp &= ~0xff;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup mmUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup mmUVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* setup mmUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL);
+ tmp &= ~0xff;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL, tmp | 0x8|
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup mmUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup mmUVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
vcn_v2_5_mc_resume(adev);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
- WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
+ volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, mmUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ WREG32_SOC15(VCN, inst, mmUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- for (k = 0; k < 10; ++k) {
- uint32_t status;
-
- for (j = 0; j < 100; ++j) {
- status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
- if (status & 2)
- break;
- if (amdgpu_emu_mode == 1)
- msleep(500);
- else
- mdelay(10);
- }
- r = 0;
+ for (k = 0; k < 10; ++k) {
+ uint32_t status;
+
+ for (j = 0; j < 100; ++j) {
+ status = RREG32_SOC15(VCN, inst, mmUVD_STATUS);
if (status & 2)
break;
+ if (amdgpu_emu_mode == 1)
+ msleep(500);
+ else
+ mdelay(10);
+ }
+ r = 0;
+ if (status & 2)
+ break;
- DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
+ mdelay(10);
+ r = -1;
+ }
- if (r) {
- DRM_ERROR("VCN decode not responding, giving up!!!\n");
- return r;
- }
+ if (r) {
+ DRM_ERROR("VCN decode not responding, giving up!!!\n");
+ return r;
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_VMID, 0);
- ring = &adev->vcn.inst[i].ring_dec;
- /* force RBC into idle state */
- rb_bufsz = order_base_2(ring->ring_size);
- tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
+ ring = &adev->vcn.inst[inst].ring_dec;
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_CNTL, tmp);
- fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
- /* program the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
- upper_32_bits(ring->gpu_addr));
+ fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
+ /* program the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR, 0);
- ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
- lower_32_bits(ring->wptr));
- fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
+ ring->wptr = RREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
- fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
- fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
-
- fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
- ring = &adev->vcn.inst[i].ring_enc[1];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
- fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
- }
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
+
+ fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
+ ring = &adev->vcn.inst[inst].ring_enc[1];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
return 0;
}
@@ -1424,72 +1416,69 @@ static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
return 0;
}
-static int vcn_v2_5_stop(struct amdgpu_device *adev)
+static int vcn_v2_5_stop(struct amdgpu_device *adev, unsigned int inst)
{
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v2_5_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_5_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* block LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* block LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2, tmp);
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* clear status */
- WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- vcn_v2_5_enable_clock_gating(adev);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
- /* enable register anti-hang mechanism */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
- ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
- }
+ vcn_v2_5_enable_clock_gating(adev);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+ /* enable register anti-hang mechanism */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS),
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+done:
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1839,9 +1828,9 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v2_5_stop(adev);
+ ret = vcn_v2_5_stop(adev, inst);
else
- ret = vcn_v2_5_start(adev);
+ ret = vcn_v2_5_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 13/32] drm/amdgpu: power vcn 3_0 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (11 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 12/32] drm/amdgpu: power vcn 2_5 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 14/32] drm/amdgpu: power vcn 4_0 " boyuan.zhang
` (19 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 3_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 583 +++++++++---------
2 files changed, 289 insertions(+), 297 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index eb77eef60368..4ab5f11f0659 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2336,7 +2336,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index a5648089ba05..e68904659059 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -160,7 +160,7 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int inst = ip_block->instance, j, r;
int vcn_doorbell_index = 0;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
uint32_t *ptr;
@@ -189,93 +189,91 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
vcn_doorbell_index = vcn_doorbell_index << 1;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.scratch9 = SOC15_REG_OFFSET(VCN, inst, mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data0 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data1 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.cmd = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.nop = SOC15_REG_OFFSET(VCN, inst, mmUVD_NO_OP);
+
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
+
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
- adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
- adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
-
- adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
- adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
- adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
- adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
- adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
-
- /* VCN DEC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
+ ring = &adev->vcn.inst[inst].ring_dec;
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev)) {
+ ring->doorbell_index = vcn_doorbell_index + inst * (adev->vcn.num_enc_rings + 1);
+ } else {
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * inst;
+ }
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_dec_%d", inst);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT,
+ &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
+
+ /* VCN ENC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
if (r)
return r;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
-
- ring = &adev->vcn.inst[i].ring_dec;
+ ring = &adev->vcn.inst[inst].ring_enc[j];
ring->use_doorbell = true;
if (amdgpu_sriov_vf(adev)) {
- ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
+ ring->doorbell_index = vcn_doorbell_index + inst * (adev->vcn.num_enc_rings + 1) + 1 + j;
} else {
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * inst;
}
ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_dec_%d", i);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_DEFAULT,
- &adev->vcn.inst[i].sched_score);
+ sprintf(ring->name, "vcn_enc_%d.%d", inst, j);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ hw_prio, &adev->vcn.inst[inst].sched_score);
if (r)
return r;
-
- for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
- enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
-
- /* VCN ENC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
-
- ring = &adev->vcn.inst[i].ring_enc[j];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev)) {
- ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
- } else {
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
- }
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_enc_%d.%d", i, j);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- hw_prio, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
- }
-
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
- cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
- cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
- fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
- fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
- fw_shared->smu_interface_info.smu_interface_type = 2;
- else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(3, 1, 1))
- fw_shared->smu_interface_info.smu_interface_type = 1;
-
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
}
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
+ cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
+ cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
+ fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
+ fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
+ fw_shared->smu_interface_info.smu_interface_type = 2;
+ else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(3, 1, 1))
+ fw_shared->smu_interface_info.smu_interface_type = 1;
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1132,192 +1130,188 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
return 0;
}
-static int vcn_v3_0_start(struct amdgpu_device *adev)
+static int vcn_v3_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
- int i, j, k, r;
+ int j, k, r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v3_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ /* disable VCN power gating */
+ vcn_v3_0_disable_static_power_gating(adev, inst);
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, tmp);
- /* disable VCN power gating */
- vcn_v3_0_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v3_0_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
-
- /* setup mmUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup mmUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup mmUVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v3_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /*SW clock gating */
+ vcn_v3_0_disable_clock_gating(adev, inst);
- for (j = 0; j < 10; ++j) {
- uint32_t status;
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- }
- r = 0;
- if (status & 2)
- break;
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
+
+ /* setup mmUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup mmUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup mmUVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v3_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, mmUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, mmUVD_STATUS);
+ if (status & 2)
+ break;
mdelay(10);
- r = -1;
}
+ r = 0;
+ if (status & 2)
+ break;
- if (r) {
- DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
- return r;
- }
+ DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ mdelay(10);
+ r = -1;
+ }
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ if (r) {
+ DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", inst);
+ return r;
+ }
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- ring = &adev->vcn.inst[i].ring_dec;
- /* force RBC into idle state */
- rb_bufsz = order_base_2(ring->ring_size);
- tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_VMID, 0);
- /* programm the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
- upper_32_bits(ring->gpu_addr));
+ ring = &adev->vcn.inst[inst].ring_dec;
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_CNTL, tmp);
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
- ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
- lower_32_bits(ring->wptr));
- fw_shared->rb.wptr = lower_32_bits(ring->wptr);
- fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
- IP_VERSION(3, 0, 33)) {
- fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
- fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
- fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- ring = &adev->vcn.inst[i].ring_enc[1];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
- fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
- }
+ /* programm the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
+
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR, 0);
+
+ WREG32_SOC15(VCN, inst, mmUVD_SCRATCH2, 0);
+ ring->wptr = RREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ fw_shared->rb.wptr = lower_32_bits(ring->wptr);
+ fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
+ IP_VERSION(3, 0, 33)) {
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+ fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ ring = &adev->vcn.inst[inst].ring_enc[1];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
}
return 0;
@@ -1563,79 +1557,76 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
return 0;
}
-static int vcn_v3_0_stop(struct amdgpu_device *adev)
+static int vcn_v3_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v3_0_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v3_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
- /* clear status */
- WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
- /* apply HW clock gating */
- vcn_v3_0_enable_clock_gating(adev, i);
+ /* apply HW clock gating */
+ vcn_v3_0_enable_clock_gating(adev, inst);
- /* enable VCN power gating */
- vcn_v3_0_enable_static_power_gating(adev, i);
- }
+ /* enable VCN power gating */
+ vcn_v3_0_enable_static_power_gating(adev, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+done:
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -2177,9 +2168,9 @@ static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v3_0_stop(adev);
+ ret = vcn_v3_0_stop(adev, inst);
else
- ret = vcn_v3_0_start(adev);
+ ret = vcn_v3_0_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 14/32] drm/amdgpu: power vcn 4_0 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (12 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 13/32] drm/amdgpu: power vcn 3_0 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 15/32] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
` (18 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 495 +++++++++---------
2 files changed, 245 insertions(+), 253 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 4ab5f11f0659..85fe628dc4d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2347,7 +2347,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2):
case IP_VERSION(4, 0, 4):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 14640d9352a0..8c32a57093fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -172,7 +172,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
+
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
uint32_t *ptr;
@@ -186,45 +187,43 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
- if (i == 0)
- atomic_set(&adev->vcn.inst[i].sched_score, 1);
- else
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
+ if (inst == 0)
+ atomic_set(&adev->vcn.inst[inst].sched_score, 1);
+ else
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
- else
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + inst * (adev->vcn.num_enc_rings + 1) + 1;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * inst;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- vcn_v4_0_fw_shared_init(adev, i);
- }
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
+ vcn_v4_0_fw_shared_init(adev, inst);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1081,180 +1080,176 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
*
* Start VCN block
*/
-static int vcn_v4_0_start(struct amdgpu_device *adev)
+static int vcn_v4_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ /* disable VCN power gating */
+ vcn_v4_0_disable_static_power_gating(adev, inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
+ /*SW clock gating */
+ vcn_v4_0_disable_clock_gating(adev, inst);
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
}
- /* disable VCN power gating */
- vcn_v4_0_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
+ r = 0;
+ break;
}
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
- r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
+ dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
- }
-
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
+ mdelay(10);
+ r = -1;
}
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
-
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
}
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
+
return 0;
}
@@ -1543,83 +1538,79 @@ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ int r = 0;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_stop_dpg_mode(adev, i);
- continue;
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
- /* apply HW clock gating */
- vcn_v4_0_enable_clock_gating(adev, i);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
- /* enable VCN power gating */
- vcn_v4_0_enable_static_power_gating(adev, i);
- }
+ /* apply HW clock gating */
+ vcn_v4_0_enable_clock_gating(adev, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+ /* enable VCN power gating */
+ vcn_v4_0_enable_static_power_gating(adev, inst);
+done:
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -2058,9 +2049,9 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_stop(adev);
+ ret = vcn_v4_0_stop(adev, inst);
else
- ret = vcn_v4_0_start(adev);
+ ret = vcn_v4_0_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 15/32] drm/amdgpu: power vcn 4_0_3 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (13 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 14/32] drm/amdgpu: power vcn 4_0 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 16/32] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
` (17 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0_3, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 462 +++++++++---------
2 files changed, 228 insertions(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 85fe628dc4d4..3f67a9cf45a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2352,7 +2352,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
break;
case IP_VERSION(4, 0, 5):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index ef246bf9d15c..4a6a4719a933 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -127,7 +127,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r, vcn_inst;
+ int inst = ip_block->instance, r, vcn_inst;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
uint32_t *ptr;
@@ -147,38 +147,36 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- vcn_inst = GET_INST(VCN, i);
+ vcn_inst = GET_INST(VCN, inst);
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
-
- if (!amdgpu_sriov_vf(adev))
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst;
- else
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 32 * vcn_inst;
-
- ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
- sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
- AMDGPU_RING_PRIO_DEFAULT,
- &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = true;
+ if (!amdgpu_sriov_vf(adev))
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 9 * vcn_inst;
+ else
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 32 * vcn_inst;
+
+ ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[inst].aid_id);
+ sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[inst].aid_id);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT,
+ &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = true;
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
@@ -1085,174 +1083,170 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
*
* Start VCN block
*/
-static int vcn_v4_0_3_start(struct amdgpu_device *adev)
+static int vcn_v4_0_3_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
- int i, j, k, r, vcn_inst;
+ int j, k, r, vcn_inst;
uint32_t tmp;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_3_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ vcn_inst = GET_INST(VCN, inst);
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
+ UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
- vcn_inst = GET_INST(VCN, i);
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
- UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_3_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK,
- ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
- tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_3_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
- WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /*SW clock gating */
+ vcn_v4_0_3_disable_clock_gating(adev, inst);
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK,
+ ~UVD_VCPU_CNTL__CLK_EN_MASK);
- for (j = 0; j < 10; ++j) {
- uint32_t status;
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, vcn_inst,
- regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- }
- r = 0;
- if (status & 2)
- break;
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- DRM_DEV_ERROR(adev->dev,
- "VCN decode not responding, trying to reset the VCPU!!!\n");
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
- regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
- regUVD_VCPU_CNTL),
- 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
+ tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_3_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, vcn_inst,
+ regUVD_STATUS);
+ if (status & 2)
+ break;
mdelay(10);
- r = -1;
}
+ r = 0;
+ if (status & 2)
+ break;
- if (r) {
- DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
- return r;
- }
+ DRM_DEV_ERROR(adev->dev,
+ "VCN decode not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
+ regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
+ regUVD_VCPU_CNTL),
+ 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ mdelay(10);
+ r = -1;
+ }
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ if (r) {
+ DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
+ return r;
+ }
- ring = &adev->vcn.inst[i].ring_enc[0];
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* program the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
- upper_32_bits(ring->gpu_addr));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
- ring->ring_size / sizeof(uint32_t));
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
- /* resetting ring, fw should not check RB ring */
- tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
- WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+ /* program the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
+ upper_32_bits(ring->gpu_addr));
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
+ ring->ring_size / sizeof(uint32_t));
- tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB_EN_MASK;
- WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+ /* resetting ring, fw should not check RB ring */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
+ WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
- ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
- fw_shared->sq.queue_mode &=
- cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB_EN_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+
+ ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
+ fw_shared->sq.queue_mode &=
+ cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
- }
return 0;
}
@@ -1295,83 +1289,79 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_3_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- int i, r = 0, vcn_inst;
+ int r = 0, vcn_inst;
uint32_t tmp;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
+ vcn_inst = GET_INST(VCN, inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_3_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_3_stop_dpg_mode(adev, inst);
+ goto Done;
+ }
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
- UVD_STATUS__IDLE, 0x7);
- if (r)
- goto Done;
-
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
- tmp);
- if (r)
- goto Done;
-
- /* stall UMC channel */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
- tmp);
- if (r)
- goto Done;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
+ UVD_STATUS__IDLE, 0x7);
+ if (r)
+ goto Done;
+
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
+ tmp);
+ if (r)
+ goto Done;
+
+ /* stall UMC channel */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
+ tmp);
+ if (r)
+ goto Done;
- /* Unblock VCPU Register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* Unblock VCPU Register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* reset LMI UMC/LMI/VCPU */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+ /* reset LMI UMC/LMI/VCPU */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
- /* clear VCN status */
- WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
+ /* clear VCN status */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
- /* apply HW clock gating */
- vcn_v4_0_3_enable_clock_gating(adev, i);
- }
+ /* apply HW clock gating */
+ vcn_v4_0_3_enable_clock_gating(adev, inst);
Done:
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1644,9 +1634,9 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_3_stop(adev);
+ ret = vcn_v4_0_3_stop(adev, inst);
else
- ret = vcn_v4_0_3_start(adev);
+ ret = vcn_v4_0_3_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 16/32] drm/amdgpu: power vcn 4_0_5 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (14 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 15/32] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 17/32] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
` (16 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 510 +++++++++---------
2 files changed, 252 insertions(+), 261 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 3f67a9cf45a5..7784e78ba808 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2358,7 +2358,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
break;
case IP_VERSION(4, 0, 5):
case IP_VERSION(4, 0, 6):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index f0e48e9bd839..1e3cc5fb3749 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -132,7 +132,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
uint32_t *ptr;
@@ -146,57 +146,55 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- i * (adev->vcn.num_enc_rings + 1) + 1;
- else
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ inst * (adev->vcn.num_enc_rings + 1) + 1;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 2 + 8 * inst;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = 1;
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
- fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
- AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = 1;
- if (amdgpu_sriov_vf(adev))
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
+ fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
+ AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ if (amdgpu_sriov_vf(adev))
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -992,180 +990,176 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
*
* Start VCN block
*/
-static int vcn_v4_0_5_start(struct amdgpu_device *adev)
+static int vcn_v4_0_5_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_5_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ /* disable VCN power gating */
+ vcn_v4_0_5_disable_static_power_gating(adev, inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ /*SW clock gating */
+ vcn_v4_0_5_disable_clock_gating(adev, inst);
- /* disable VCN power gating */
- vcn_v4_0_5_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_5_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_5_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
- }
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_5_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
+ }
+
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev,
- "VCN[%d] is not responding, trying to reset VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
+ break;
+ }
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
+
+ dev_err(adev->dev,
+ "VCN[%d] is not responding, trying to reset VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
+ mdelay(10);
+ r = -1;
}
+ }
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
- }
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
- }
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
return 0;
}
@@ -1205,83 +1199,79 @@ static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_5_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_5_stop_dpg_mode(adev, i);
- continue;
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_5_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
- /* apply HW clock gating */
- vcn_v4_0_5_enable_clock_gating(adev, i);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
- /* enable VCN power gating */
- vcn_v4_0_5_enable_static_power_gating(adev, i);
- }
+ /* apply HW clock gating */
+ vcn_v4_0_5_enable_clock_gating(adev, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+ /* enable VCN power gating */
+ vcn_v4_0_5_enable_static_power_gating(adev, inst);
+done:
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1542,9 +1532,9 @@ static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_5_stop(adev);
+ ret = vcn_v4_0_5_stop(adev, inst);
else
- ret = vcn_v4_0_5_start(adev);
+ ret = vcn_v4_0_5_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 17/32] drm/amdgpu: power vcn 5_0_0 by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (15 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 16/32] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 18/32] drm/amdgpu/vcn: separate idle work " boyuan.zhang
` (15 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 5_0_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 432 +++++++++---------
2 files changed, 213 insertions(+), 222 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 7784e78ba808..4bf039796d37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2363,7 +2363,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 8e716165cc03..a7723b5c5db7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -116,7 +116,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
uint32_t *ptr;
@@ -130,46 +130,44 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn5_fw_shared *fw_shared;
-
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ volatile struct amdgpu_vcn5_fw_shared *fw_shared;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * inst;
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = 1;
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = 1;
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
@@ -753,151 +751,147 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
*
* Start VCN block
*/
-static int vcn_v5_0_0_start(struct amdgpu_device *adev)
+static int vcn_v5_0_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true, i);
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, inst);
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v5_0_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ /* disable VCN power gating */
+ vcn_v5_0_0_disable_static_power_gating(adev, inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
- /* disable VCN power gating */
- vcn_v5_0_0_disable_static_power_gating(adev, i);
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- vcn_v5_0_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
- }
+ vcn_v5_0_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
+ }
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev,
- "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- mdelay(10);
- r = -1;
+ break;
}
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
+
+ dev_err(adev->dev,
+ "VCN[%d] is not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ mdelay(10);
+ r = -1;
}
+ }
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
- }
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
- }
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
return 0;
}
@@ -939,80 +933,76 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v5_0_0_stop(struct amdgpu_device *adev)
+static int vcn_v5_0_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v5_0_0_stop_dpg_mode(adev, i);
- continue;
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v5_0_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
-
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
-
- /* enable VCN power gating */
- vcn_v5_0_0_enable_static_power_gating(adev, i);
- }
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false, i);
- }
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
+
+ /* enable VCN power gating */
+ vcn_v5_0_0_enable_static_power_gating(adev, inst);
+done:
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1269,9 +1259,9 @@ static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
return 0;
if (state == AMD_PG_STATE_GATE)
- ret = vcn_v5_0_0_stop(adev);
+ ret = vcn_v5_0_0_stop(adev, inst);
else
- ret = vcn_v5_0_0_start(adev);
+ ret = vcn_v5_0_0_start(adev, inst);
if (!ret)
adev->vcn.inst[inst].cur_state = state;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 18/32] drm/amdgpu/vcn: separate idle work by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (16 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 17/32] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 19/32] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
` (14 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Previously idle working handling is for all VCN instances. As a result, when one
of the instance finishes its job, the idle work can't be triggered if the other
instance is still busy.
Now, move the idle_work from amdgpu_vcn to amdgpu_vcn_inst, in order to
track work by vcn instance. Add work_inst to track the instance number
that the work belongs to. As a result, the idle work can now be triggered
once the job is done on one of the vcn instance, and no need to consider
the work on the other vcn instance.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 66 ++++++++++++------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +-
17 files changed, 58 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 7ebcab8d1bd2..4838a4ca44f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -118,7 +118,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
unsigned int fw_shared_size, log_offset;
int i, r;
- INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ adev->vcn.inst[i].adev = adev;
+ adev->vcn.inst[i].work_inst = i;
+ INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
+ }
mutex_init(&adev->vcn.vcn_pg_lock);
mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
atomic_set(&adev->vcn.total_submission_cnt, 0);
@@ -302,7 +306,8 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
bool in_ras_intr = amdgpu_ras_intr_triggered();
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
/* err_event_athub will corrupt VCPU buffer, so we need to
* restore fw data and clear buffer in amdgpu_vcn_resume() */
@@ -376,46 +381,43 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
{
- struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
- unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
- unsigned int i, j;
+ struct amdgpu_vcn_inst *vcn_inst =
+ container_of(work, struct amdgpu_vcn_inst, idle_work.work);
+ struct amdgpu_device *adev = vcn_inst->adev;
+ unsigned int inst = vcn_inst->work_inst;
+ unsigned int fence = 0;
+ unsigned int i;
int r = 0;
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i)
- fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
-
- /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
- !adev->vcn.using_unified_queue) {
- struct dpg_pause_state new_state;
-
- if (fence[j] ||
- unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
- new_state.fw_based = VCN_DPG_STATE__PAUSE;
- else
- new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.pause_dpg_mode(adev, j, &new_state);
- }
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_enc[i]);
- fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
- fences += fence[j];
+ /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
+ !adev->vcn.using_unified_queue) {
+ struct dpg_pause_state new_state;
+ if (fence ||
+ unlikely(atomic_read(&adev->vcn.inst[inst].dpg_enc_submission_cnt)))
+ new_state.fw_based = VCN_DPG_STATE__PAUSE;
+ else
+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ adev->vcn.pause_dpg_mode(adev, inst, &new_state);
}
- if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
+ fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_dec);
+
+ if (!fence && !atomic_read(&adev->vcn.total_submission_cnt)) {
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
- false);
+ false);
if (r)
dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
} else {
- schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&adev->vcn.inst[inst].idle_work, VCN_IDLE_TIMEOUT);
}
}
@@ -426,7 +428,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
atomic_inc(&adev->vcn.total_submission_cnt);
- if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
+ if (!cancel_delayed_work_sync(&adev->vcn.inst[ring->me].idle_work)) {
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
true);
if (r)
@@ -475,7 +477,7 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
atomic_dec(&ring->adev->vcn.total_submission_cnt);
- schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, VCN_IDLE_TIMEOUT);
}
int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 0d882ba59b22..38488194a1e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -279,6 +279,7 @@ struct amdgpu_vcn_fw_shared {
};
struct amdgpu_vcn_inst {
+ struct amdgpu_device *adev;
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
uint64_t gpu_addr;
@@ -301,6 +302,8 @@ struct amdgpu_vcn_inst {
enum amd_powergating_state cur_state;
uint8_t vcn_config;
uint32_t vcn_codec_disable_mask;
+ struct delayed_work idle_work;
+ uint8_t work_inst;
};
struct amdgpu_vcn_ras {
@@ -309,7 +312,6 @@ struct amdgpu_vcn_ras {
struct amdgpu_vcn {
unsigned fw_version;
- struct delayed_work idle_work;
unsigned num_enc_rings;
bool indirect_sram;
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
index 03b8b7cd5229..8031406e20ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
@@ -604,7 +604,7 @@ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
int cnt = 0;
mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index e13d1c2a9378..2c89b63540b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -150,7 +150,7 @@ static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 091baf408a86..1ca20847dfc6 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -211,7 +211,7 @@ static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (adev->jpeg.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 1f284f1f29d2..f9e62c45ec4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -164,7 +164,7 @@ static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index e78135cdddd8..7d1c525c9f17 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -195,7 +195,7 @@ static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index 8f53f3a40084..4bd211421c76 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -219,7 +219,7 @@ static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (adev->jpeg.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 8329692dff07..978666b5e7ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -161,7 +161,7 @@ static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 407b0b5146cd..f6886cf2a686 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -150,7 +150,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
return r;
/* Override the work func */
- adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
+ adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
amdgpu_vcn_setup_ucode(adev);
@@ -277,7 +277,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
@@ -301,7 +301,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
bool idle_work_unexecuted;
- idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
+ idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (idle_work_unexecuted) {
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_vcn(adev, false, 0);
@@ -1830,7 +1830,7 @@ static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
static void vcn_v1_0_idle_work_handler(struct work_struct *work)
{
struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
+ container_of(work, struct amdgpu_device, vcn.inst[0].idle_work.work);
unsigned int fences = 0, i;
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
@@ -1863,14 +1863,14 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
} else {
- schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
}
}
static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
@@ -1922,7 +1922,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
{
- schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&ring->adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 03eaae64c356..15c498b2b0de 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -313,7 +313,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 9162c7fcefc7..880dc4790a96 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -387,7 +387,7 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e68904659059..464394989dd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -420,7 +420,7 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 8c32a57093fd..2994328982ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -349,7 +349,7 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 4a6a4719a933..166e86fa7daf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -315,7 +315,7 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.inst[inst].cur_state != AMD_PG_STATE_GATE)
vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 1e3cc5fb3749..26de66ac0af3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -298,7 +298,7 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index a7723b5c5db7..5987a8af22cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -262,7 +262,7 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
struct amdgpu_device *adev = ip_block->adev;
int inst = ip_block->instance;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 19/32] drm/amdgpu: set powergating state by vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (17 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 18/32] drm/amdgpu/vcn: separate idle work " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 20/32] drm/amdgpu: early_init for each " boyuan.zhang
` (13 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Set powergating state by vcn instance in idle_work_handler() and
ring_begin_use() functions for vcn with multiple instances.
v2: Add instance parameter to amdgpu_device_ip_set_powergating_state(),
instead of creating new function.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 ++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 6 ++++--
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 8 ++++----
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 6 ++++--
.../amd/pm/powerplay/hwmgr/smu7_clockpowergating.c | 12 ++++++++----
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 12 ++++++++----
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 6 ++++--
22 files changed, 65 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3442564fe174..53b7b7c0291c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -357,7 +357,8 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_clockgating_state state);
int amdgpu_device_ip_set_powergating_state(void *dev,
enum amd_ip_block_type block_type,
- enum amd_powergating_state state);
+ enum amd_powergating_state state,
+ int inst);
void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
u64 *flags);
int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 426beab725b2..5ccfe7394e15 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2141,7 +2141,8 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
*/
int amdgpu_device_ip_set_powergating_state(void *dev,
enum amd_ip_block_type block_type,
- enum amd_powergating_state state)
+ enum amd_powergating_state state,
+ int inst)
{
struct amdgpu_device *adev = dev;
int i, r = 0;
@@ -2151,6 +2152,9 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
continue;
if (adev->ip_blocks[i].version->type != block_type)
continue;
+ if (block_type == AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].instance != inst)
+ continue;
if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
continue;
r = adev->ip_blocks[i].version->funcs->set_powergating_state(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index 95e2796919fc..78fd1ff28a57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -119,7 +119,7 @@ static void amdgpu_jpeg_idle_work_handler(struct work_struct *work)
if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
else
schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
}
@@ -133,7 +133,7 @@ void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
mutex_lock(&adev->jpeg.jpeg_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
mutex_unlock(&adev->jpeg.jpeg_pg_lock);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 31fd30dcd593..09844953a1fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1277,7 +1277,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
@@ -1303,7 +1303,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
}
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 74fdbf71d95b..a061fb8a2fcf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -344,7 +344,7 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
} else {
amdgpu_asic_set_vce_clocks(adev, 0, 0);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
}
@@ -378,7 +378,7 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 4838a4ca44f8..e93d3ef2fdd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -410,8 +410,9 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_dec);
if (!fence && !atomic_read(&adev->vcn.total_submission_cnt)) {
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_GATE, inst);
+
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
false);
if (r)
@@ -436,8 +437,9 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
}
mutex_lock(&adev->vcn.vcn_pg_lock);
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_UNGATE);
+
+ amdgpu_device_ip_set_powergating_state(adev,
+ AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_UNGATE, ring->me);
/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index 416d1a073173..6b2afcc3fb21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -330,7 +330,7 @@ static void vpe_idle_work_handler(struct work_struct *work)
fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
if (fences == 0)
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE, 0);
else
schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
}
@@ -406,7 +406,7 @@ static int vpe_hw_init(struct amdgpu_ip_block *ip_block)
/* Power on VPE */
ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
if (ret)
return ret;
@@ -429,7 +429,7 @@ static int vpe_hw_fini(struct amdgpu_ip_block *ip_block)
vpe_ring_stop(vpe);
/* Power off VPE */
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE, 0);
return 0;
}
@@ -845,7 +845,7 @@ static void vpe_ring_begin_use(struct amdgpu_ring *ring)
uint32_t context_notify;
/* Power on VPE */
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE, 0);
/* Indicates that a job from a new context has been submitted. */
context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index d5a5a5189ac6..a3b8bccf3c9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -735,7 +735,7 @@ static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 9e3ac12d0127..7dced60403ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -249,7 +249,7 @@ static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index a16c99d0b85d..f883cf8d2d2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -247,7 +247,7 @@ static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 5da51118a184..9cb78358e355 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -571,7 +571,7 @@ static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 591db2da8067..92f369d08fec 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -639,7 +639,7 @@ static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block)
amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index f4bd28af41e1..72e01a0352ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -512,7 +512,7 @@ static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block)
} else {
amdgpu_asic_set_vce_clocks(adev, 0, 0);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 679033481616..4ee0d479b0fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -523,7 +523,7 @@ static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block)
} else {
amdgpu_asic_set_vce_clocks(adev, 0, 0);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index adcbf61411b5..d9c36d7213de 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -589,7 +589,7 @@ static int vce_v4_0_suspend(struct amdgpu_ip_block *ip_block)
} else {
amdgpu_asic_set_vce_clocks(adev, 0, 0);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index f6886cf2a686..f093d66df1a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1861,7 +1861,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
amdgpu_dpm_enable_vcn(adev, false, 0);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
} else {
schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
}
@@ -1891,7 +1891,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
amdgpu_dpm_enable_vcn(adev, true, 0);
else
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
}
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 5a9006bfc3cd..d4c264814b61 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -1026,7 +1026,8 @@ int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
/* enter UMD Pstate */
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
amdgpu_device_ip_set_clockgating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_CG_STATE_UNGATE);
@@ -1038,7 +1039,8 @@ int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
AMD_CG_STATE_GATE);
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
}
mutex_lock(&adev->pm.mutex);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 3cafc9493e88..b0443f20fe2a 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -1675,7 +1675,7 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
if (gate) {
/* stop the UVD block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
kv_update_uvd_dpm(adev, gate);
if (pi->caps_uvd_pg)
/* power off the UVD block */
@@ -1688,7 +1688,7 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
kv_update_uvd_dpm(adev, gate);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
}
}
@@ -1702,7 +1702,7 @@ static void kv_dpm_powergate_vce(void *handle, bool gate)
if (gate) {
/* stop the VCE block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
kv_enable_vce_dpm(adev, false);
if (pi->caps_vce_pg) /* power off the VCE block */
amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
@@ -1712,7 +1712,7 @@ static void kv_dpm_powergate_vce(void *handle, bool gate)
kv_enable_vce_dpm(adev, true);
/* re-init the VCE block */
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE, 0);
}
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index a8c732e07006..41dbf043f59b 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -1407,7 +1407,8 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0, NULL);
smu10_data->vcn_power_gated = true;
@@ -1416,7 +1417,8 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
PPSMC_MSG_PowerUpVcn, 0, NULL);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
smu10_data->vcn_power_gated = false;
}
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
index f2bda3bcbbde..b496b77153e9 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_clockpowergating.c
@@ -120,7 +120,8 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
@@ -133,7 +134,8 @@ void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
smu7_update_uvd_dpm(hwmgr, false);
}
@@ -148,7 +150,8 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
@@ -161,7 +164,8 @@ void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
smu7_update_vce_dpm(hwmgr, false);
}
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
index 7e1197420873..2ccce2bc3b4a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c
@@ -1985,7 +1985,8 @@ static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE);
@@ -1998,7 +1999,8 @@ static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_UVD,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
smu8_dpm_update_uvd_dpm(hwmgr, false);
}
@@ -2017,7 +2019,8 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE);
@@ -2032,7 +2035,8 @@ static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
AMD_CG_STATE_UNGATE);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
smu8_dpm_update_vce_dpm(hwmgr);
smu8_enable_disable_vce_dpm(hwmgr, true);
}
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index baf251fe5d82..64ef8c8398ff 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -3715,11 +3715,13 @@ static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
vega20_enable_disable_vce_dpm(hwmgr, !bgate);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE,
+ 0);
} else {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCE,
- AMD_PG_STATE_UNGATE);
+ AMD_PG_STATE_UNGATE,
+ 0);
vega20_enable_disable_vce_dpm(hwmgr, !bgate);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 20/32] drm/amdgpu: early_init for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (18 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 19/32] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 21/32] drm/amdgpu: sw_init " boyuan.zhang
` (12 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_early_init(), and perform
early init ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 23 ++++++++++++-----------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 13 ++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 +++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 3 ++-
10 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e93d3ef2fdd1..e2986871f3a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -91,22 +91,23 @@ MODULE_FIRMWARE(FIRMWARE_VCN5_0_0);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
-int amdgpu_vcn_early_init(struct amdgpu_device *adev)
+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst)
{
char ucode_prefix[25];
- int r, i;
+ int r;
amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
- r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s_%d.bin", ucode_prefix, i);
- else
- r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw, "amdgpu/%s.bin", ucode_prefix);
- if (r) {
- amdgpu_ucode_release(&adev->vcn.inst[i].fw);
- return r;
- }
+
+ if (inst == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[inst].fw, "amdgpu/%s_%d.bin", ucode_prefix, inst);
+ else
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[inst].fw, "amdgpu/%s.bin", ucode_prefix);
+
+ if (r) {
+ amdgpu_ucode_release(&adev->vcn.inst[inst].fw);
+ return r;
}
+
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 38488194a1e7..acf4b88e2797 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -483,7 +483,7 @@ enum vcn_ring_type {
VCN_UNIFIED_RING,
};
-int amdgpu_vcn_early_init(struct amdgpu_device *adev);
+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index f093d66df1a0..1a3907295e36 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -104,6 +104,7 @@ static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
adev->vcn.num_enc_rings = 2;
@@ -113,7 +114,7 @@ static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
jpeg_v1_0_early_init(ip_block);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 15c498b2b0de..d14062e1dd31 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -108,6 +108,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev))
adev->vcn.num_enc_rings = 1;
@@ -118,7 +119,7 @@ static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
vcn_v2_0_set_enc_ring_funcs(adev);
vcn_v2_0_set_irq_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 880dc4790a96..5d145adbe932 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -118,6 +118,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.num_vcn_inst = 2;
@@ -125,13 +126,11 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
adev->vcn.num_enc_rings = 1;
} else {
u32 harvest;
- int i;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
- if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
- adev->vcn.harvest_config |= 1 << i;
- }
+ harvest = RREG32_SOC15(VCN, inst, mmCC_UVD_HARVESTING);
+ if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
+ adev->vcn.harvest_config |= 1 << inst;
+
if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
AMDGPU_VCN_HARVEST_VCN1))
/* both instances are harvested, disable the block */
@@ -145,7 +144,7 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
vcn_v2_5_set_irq_funcs(adev);
vcn_v2_5_set_ras_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 464394989dd6..464a502a7cd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -124,6 +124,7 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
@@ -147,7 +148,7 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
vcn_v3_0_set_enc_ring_funcs(adev);
vcn_v3_0_set_irq_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 2994328982ce..58fdc07d9641 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -114,15 +114,13 @@ static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i;
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
- adev->vcn.harvest_config |= 1 << i;
- dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
- }
+ if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, inst)) {
+ adev->vcn.harvest_config |= 1 << inst;
+ dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", inst);
}
}
@@ -133,7 +131,7 @@ static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)
vcn_v4_0_set_irq_funcs(adev);
vcn_v4_0_set_ras_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 166e86fa7daf..4641534bb768 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -105,6 +105,7 @@ static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
@@ -113,7 +114,7 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)
vcn_v4_0_3_set_irq_funcs(adev);
vcn_v4_0_3_set_ras_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 26de66ac0af3..d5ef1b0bcf54 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -112,13 +112,14 @@ static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);
static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
vcn_v4_0_5_set_unified_ring_funcs(adev);
vcn_v4_0_5_set_irq_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 5987a8af22cc..88248fcfa138 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -95,6 +95,7 @@ static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
@@ -102,7 +103,7 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
vcn_v5_0_0_set_unified_ring_funcs(adev);
vcn_v5_0_0_set_irq_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 21/32] drm/amdgpu: sw_init for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (19 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 20/32] drm/amdgpu: early_init for each " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 22/32] drm/amdgpu: sw_fini " boyuan.zhang
` (11 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_sw_init(), and perform
sw init ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 83 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 7 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 7 ++-
10 files changed, 69 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e2986871f3a8..791b95867ac2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -111,24 +111,23 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst)
return r;
}
-int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
+int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst)
{
unsigned long bo_size;
const struct common_firmware_header *hdr;
unsigned char fw_check;
unsigned int fw_shared_size, log_offset;
- int i, r;
+ int r;
+
+ adev->vcn.inst[inst].adev = adev;
+ adev->vcn.inst[inst].work_inst = inst;
+ INIT_DELAYED_WORK(&adev->vcn.inst[inst].idle_work, amdgpu_vcn_idle_work_handler);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- adev->vcn.inst[i].adev = adev;
- adev->vcn.inst[i].work_inst = i;
- INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
- }
mutex_init(&adev->vcn.vcn_pg_lock);
mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
atomic_set(&adev->vcn.total_submission_cnt, 0);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++)
- atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
+
+ atomic_set(&adev->vcn.inst[inst].dpg_enc_submission_cnt, 0);
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
@@ -206,45 +205,43 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
if (amdgpu_vcnfw_log)
bo_size += AMDGPU_VCNFW_LOG_SIZE;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM |
- AMDGPU_GEM_DOMAIN_GTT,
- &adev->vcn.inst[i].vcpu_bo,
- &adev->vcn.inst[i].gpu_addr,
- &adev->vcn.inst[i].cpu_addr);
- if (r) {
- dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
- return r;
- }
+ r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM |
+ AMDGPU_GEM_DOMAIN_GTT,
+ &adev->vcn.inst[inst].vcpu_bo,
+ &adev->vcn.inst[inst].gpu_addr,
+ &adev->vcn.inst[inst].cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
+ return r;
+ }
- adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
- bo_size - fw_shared_size;
- adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
- bo_size - fw_shared_size;
+ adev->vcn.inst[inst].fw_shared.cpu_addr = adev->vcn.inst[inst].cpu_addr +
+ bo_size - fw_shared_size;
+ adev->vcn.inst[inst].fw_shared.gpu_addr = adev->vcn.inst[inst].gpu_addr +
+ bo_size - fw_shared_size;
- adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
+ adev->vcn.inst[inst].fw_shared.mem_size = fw_shared_size;
- if (amdgpu_vcnfw_log) {
- adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
- adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
- adev->vcn.inst[i].fw_shared.log_offset = log_offset;
- }
+ if (amdgpu_vcnfw_log) {
+ adev->vcn.inst[inst].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
+ adev->vcn.inst[inst].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
+ adev->vcn.inst[inst].fw_shared.log_offset = log_offset;
+ }
- if (adev->vcn.indirect_sram) {
- r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM |
- AMDGPU_GEM_DOMAIN_GTT,
- &adev->vcn.inst[i].dpg_sram_bo,
- &adev->vcn.inst[i].dpg_sram_gpu_addr,
- &adev->vcn.inst[i].dpg_sram_cpu_addr);
- if (r) {
- dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
- return r;
- }
+ if (adev->vcn.indirect_sram) {
+ r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM |
+ AMDGPU_GEM_DOMAIN_GTT,
+ &adev->vcn.inst[inst].dpg_sram_bo,
+ &adev->vcn.inst[inst].dpg_sram_gpu_addr,
+ &adev->vcn.inst[inst].dpg_sram_cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", inst, r);
+ return r;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index acf4b88e2797..825b70a396cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -484,7 +484,7 @@ enum vcn_ring_type {
};
int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
+int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1a3907295e36..70d865724463 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -126,11 +126,12 @@ static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
uint32_t *ptr;
- struct amdgpu_device *adev = ip_block->adev;
/* VCN DEC TRAP */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
@@ -146,7 +147,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
return r;
}
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index d14062e1dd31..834311e13a4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -131,11 +131,12 @@ static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
uint32_t *ptr;
- struct amdgpu_device *adev = ip_block->adev;
volatile struct amdgpu_fw_shared *fw_shared;
/* VCN DEC TRAP */
@@ -154,7 +155,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
return r;
}
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 5d145adbe932..f6d2e3e3bf32 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -156,12 +156,12 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
uint32_t *ptr;
- struct amdgpu_device *adev = ip_block->adev;
- int inst = ip_block->instance;
if (adev->vcn.harvest_config & (1 << inst))
goto sw_init;
@@ -185,7 +185,7 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
sw_init:
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 464a502a7cd7..9b62296cc233 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -160,14 +160,15 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
- int inst = ip_block->instance, j, r;
int vcn_doorbell_index = 0;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
uint32_t *ptr;
- struct amdgpu_device *adev = ip_block->adev;
+ int j, r;
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 58fdc07d9641..79d5ef8f857c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -168,14 +168,15 @@ static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx)
*/
static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int inst = ip_block->instance, r;
+ int inst = ip_block->instance;
+ struct amdgpu_ring *ring;
+ int r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
uint32_t *ptr;
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 4641534bb768..0932e992d088 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -127,12 +127,13 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
- int inst = ip_block->instance, r, vcn_inst;
+ int r, vcn_inst;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
uint32_t *ptr;
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index d5ef1b0bcf54..e551ba1d1e12 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -131,13 +131,14 @@ static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int inst = ip_block->instance, r;
+ int inst = ip_block->instance;
+ struct amdgpu_ring *ring;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
uint32_t *ptr;
+ int r;
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 88248fcfa138..dc15a74bb3d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -115,13 +115,14 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
{
- struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int inst = ip_block->instance, r;
+ int inst = ip_block->instance;
+ struct amdgpu_ring *ring;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
uint32_t *ptr;
+ int r;
- r = amdgpu_vcn_sw_init(adev);
+ r = amdgpu_vcn_sw_init(adev, inst);
if (r)
return r;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 22/32] drm/amdgpu: sw_fini for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (20 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 21/32] drm/amdgpu: sw_init " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-28 19:40 ` Alex Deucher
2024-10-17 13:20 ` [PATCH 23/32] drm/amdgpu: hw_init " boyuan.zhang
` (10 subsequent siblings)
32 siblings, 1 reply; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_sw_fini(), and perform
sw fini ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 36 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 17 ++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 21 +++++++--------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 16 +++++------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 21 +++++++--------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 21 +++++++--------
10 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 791b95867ac2..307615ffeb79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -248,33 +248,31 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst)
return 0;
}
-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst)
{
- int i, j;
-
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
+ int i;
- amdgpu_bo_free_kernel(
- &adev->vcn.inst[j].dpg_sram_bo,
- &adev->vcn.inst[j].dpg_sram_gpu_addr,
- (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- kvfree(adev->vcn.inst[j].saved_bo);
+ amdgpu_bo_free_kernel(
+ &adev->vcn.inst[inst].dpg_sram_bo,
+ &adev->vcn.inst[inst].dpg_sram_gpu_addr,
+ (void **)&adev->vcn.inst[inst].dpg_sram_cpu_addr);
- amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
- &adev->vcn.inst[j].gpu_addr,
- (void **)&adev->vcn.inst[j].cpu_addr);
+ kvfree(adev->vcn.inst[inst].saved_bo);
- amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
+ amdgpu_bo_free_kernel(&adev->vcn.inst[inst].vcpu_bo,
+ &adev->vcn.inst[inst].gpu_addr,
+ (void **)&adev->vcn.inst[inst].cpu_addr);
- for (i = 0; i < adev->vcn.num_enc_rings; ++i)
- amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
+ amdgpu_ring_fini(&adev->vcn.inst[inst].ring_dec);
- amdgpu_ucode_release(&adev->vcn.inst[j].fw);
- }
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ amdgpu_ring_fini(&adev->vcn.inst[inst].ring_enc[i]);
+ amdgpu_ucode_release(&adev->vcn.inst[inst].fw);
+done:
mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
mutex_destroy(&adev->vcn.vcn_pg_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 825b70a396cd..883b9f9776a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -485,7 +485,7 @@ enum vcn_ring_type {
int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 70d865724463..8203f80be316 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -222,8 +222,9 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
- int r;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
+ int r;
r = amdgpu_vcn_suspend(adev);
if (r)
@@ -231,7 +232,7 @@ static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
jpeg_v1_0_sw_fini(ip_block);
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 834311e13a4c..0481a07054eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -245,9 +245,10 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
- int r, idx;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
fw_shared->present_flag_0 = 0;
@@ -260,7 +261,7 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index f6d2e3e3bf32..ed972d843f93 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -297,17 +297,18 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
{
- int i, r, idx;
struct amdgpu_device *adev = ip_block->adev;
volatile struct amdgpu_fw_shared *fw_shared;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ done:
drm_dev_exit(idx);
}
@@ -319,7 +320,7 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9b62296cc233..c45bebeb0aaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -306,19 +306,19 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, r, idx;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- fw_shared->sw_ring.is_enabled = false;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sw_ring.is_enabled = false;
+ done:
drm_dev_exit(idx);
}
@@ -329,7 +329,7 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 79d5ef8f857c..c87b4e46f2b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -258,20 +258,19 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, r, idx;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- fw_shared->sq.is_enabled = 0;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sq.is_enabled = 0;
+ done:
drm_dev_exit(idx);
}
@@ -282,7 +281,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 0932e992d088..0b55d801ae88 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -219,16 +219,16 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, r, idx;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(&adev->ddev, &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sq.is_enabled = cpu_to_le32(false);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- fw_shared->sq.is_enabled = cpu_to_le32(false);
- }
drm_dev_exit(idx);
}
@@ -239,7 +239,7 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index e551ba1d1e12..b88fdb00cc5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -227,20 +227,19 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, r, idx;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
-
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- fw_shared->sq.is_enabled = 0;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sq.is_enabled = 0;
+ done:
drm_dev_exit(idx);
}
@@ -251,7 +250,7 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index dc15a74bb3d8..15cdc7be9062 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -194,20 +194,19 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, r, idx;
+ int inst = ip_block->instance;
+ int r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn5_fw_shared *fw_shared;
-
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ volatile struct amdgpu_vcn5_fw_shared *fw_shared;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = 0;
- fw_shared->sq.is_enabled = 0;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = 0;
+ fw_shared->sq.is_enabled = 0;
+ done:
drm_dev_exit(idx);
}
@@ -215,7 +214,7 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 22/32] drm/amdgpu: sw_fini for each vcn instance
2024-10-17 13:20 ` [PATCH 22/32] drm/amdgpu: sw_fini " boyuan.zhang
@ 2024-10-28 19:40 ` Alex Deucher
0 siblings, 0 replies; 45+ messages in thread
From: Alex Deucher @ 2024-10-28 19:40 UTC (permalink / raw)
To: boyuan.zhang; +Cc: amd-gfx, leo.liu, christian.koenig, alexander.deucher
On Thu, Oct 17, 2024 at 11:43 AM <boyuan.zhang@amd.com> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Pass instance parameter to amdgpu_vcn_sw_fini(), and perform
> sw fini ONLY for the given vcn instance, instead of for all
> vcn instances. Modify each vcn generation accordingly.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Thinking about these patches that modify amdgpu_vcn.c to add the
instance to them, will this break anything due to changes in ordering?
If so, we may want to squash all of these together into one patch.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 36 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 17 ++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +++++++-------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 21 +++++++--------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 16 +++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 21 +++++++--------
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 21 +++++++--------
> 10 files changed, 81 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 791b95867ac2..307615ffeb79 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -248,33 +248,31 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst)
> return 0;
> }
>
> -int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
> +int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst)
> {
> - int i, j;
> -
> - for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
> - if (adev->vcn.harvest_config & (1 << j))
> - continue;
> + int i;
>
> - amdgpu_bo_free_kernel(
> - &adev->vcn.inst[j].dpg_sram_bo,
> - &adev->vcn.inst[j].dpg_sram_gpu_addr,
> - (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> - kvfree(adev->vcn.inst[j].saved_bo);
> + amdgpu_bo_free_kernel(
> + &adev->vcn.inst[inst].dpg_sram_bo,
> + &adev->vcn.inst[inst].dpg_sram_gpu_addr,
> + (void **)&adev->vcn.inst[inst].dpg_sram_cpu_addr);
>
> - amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
> - &adev->vcn.inst[j].gpu_addr,
> - (void **)&adev->vcn.inst[j].cpu_addr);
> + kvfree(adev->vcn.inst[inst].saved_bo);
>
> - amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
> + amdgpu_bo_free_kernel(&adev->vcn.inst[inst].vcpu_bo,
> + &adev->vcn.inst[inst].gpu_addr,
> + (void **)&adev->vcn.inst[inst].cpu_addr);
>
> - for (i = 0; i < adev->vcn.num_enc_rings; ++i)
> - amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
> + amdgpu_ring_fini(&adev->vcn.inst[inst].ring_dec);
>
> - amdgpu_ucode_release(&adev->vcn.inst[j].fw);
> - }
> + for (i = 0; i < adev->vcn.num_enc_rings; ++i)
> + amdgpu_ring_fini(&adev->vcn.inst[inst].ring_enc[i]);
>
> + amdgpu_ucode_release(&adev->vcn.inst[inst].fw);
> +done:
> mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
> mutex_destroy(&adev->vcn.vcn_pg_lock);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 825b70a396cd..883b9f9776a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -485,7 +485,7 @@ enum vcn_ring_type {
>
> int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
> int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
> -int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
> +int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst);
> int amdgpu_vcn_suspend(struct amdgpu_device *adev);
> int amdgpu_vcn_resume(struct amdgpu_device *adev);
> void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 70d865724463..8203f80be316 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -222,8 +222,9 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
> */
> static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> - int r;
> struct amdgpu_device *adev = ip_block->adev;
> + int inst = ip_block->instance;
> + int r;
>
> r = amdgpu_vcn_suspend(adev);
> if (r)
> @@ -231,7 +232,7 @@ static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
>
> jpeg_v1_0_sw_fini(ip_block);
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 834311e13a4c..0481a07054eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -245,9 +245,10 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
> */
> static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> - int r, idx;
> struct amdgpu_device *adev = ip_block->adev;
> + int inst = ip_block->instance;
> volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> fw_shared->present_flag_0 = 0;
> @@ -260,7 +261,7 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index f6d2e3e3bf32..ed972d843f93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -297,17 +297,18 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
> */
> static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> - int i, r, idx;
> struct amdgpu_device *adev = ip_block->adev;
> volatile struct amdgpu_fw_shared *fw_shared;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
> +
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + done:
> drm_dev_exit(idx);
> }
>
> @@ -319,7 +320,7 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 9b62296cc233..c45bebeb0aaa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -306,19 +306,19 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
> static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r, idx;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_fw_shared *fw_shared;
> + volatile struct amdgpu_fw_shared *fw_shared;
>
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - fw_shared->sw_ring.is_enabled = false;
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + fw_shared->sw_ring.is_enabled = false;
> + done:
> drm_dev_exit(idx);
> }
>
> @@ -329,7 +329,7 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 79d5ef8f857c..c87b4e46f2b0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -258,20 +258,19 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
> static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r, idx;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> + volatile struct amdgpu_vcn4_fw_shared *fw_shared;
>
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> -
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - fw_shared->sq.is_enabled = 0;
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + fw_shared->sq.is_enabled = 0;
> + done:
> drm_dev_exit(idx);
> }
>
> @@ -282,7 +281,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 0932e992d088..0b55d801ae88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -219,16 +219,16 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
> static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r, idx;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(&adev->ddev, &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> + volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> +
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + fw_shared->sq.is_enabled = cpu_to_le32(false);
>
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - fw_shared->sq.is_enabled = cpu_to_le32(false);
> - }
> drm_dev_exit(idx);
> }
>
> @@ -239,7 +239,7 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index e551ba1d1e12..b88fdb00cc5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -227,20 +227,19 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
> static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r, idx;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_vcn4_fw_shared *fw_shared;
> -
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + volatile struct amdgpu_vcn4_fw_shared *fw_shared;
>
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - fw_shared->sq.is_enabled = 0;
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + fw_shared->sq.is_enabled = 0;
> + done:
> drm_dev_exit(idx);
> }
>
> @@ -251,7 +250,7 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index dc15a74bb3d8..15cdc7be9062 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -194,20 +194,19 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
> static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, r, idx;
> + int inst = ip_block->instance;
> + int r, idx;
>
> if (drm_dev_enter(adev_to_drm(adev), &idx)) {
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - volatile struct amdgpu_vcn5_fw_shared *fw_shared;
> -
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + volatile struct amdgpu_vcn5_fw_shared *fw_shared;
>
> - fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
> - fw_shared->present_flag_0 = 0;
> - fw_shared->sq.is_enabled = 0;
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + goto done;
>
> + fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
> + fw_shared->present_flag_0 = 0;
> + fw_shared->sq.is_enabled = 0;
> + done:
> drm_dev_exit(idx);
> }
>
> @@ -215,7 +214,7 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
> if (r)
> return r;
>
> - r = amdgpu_vcn_sw_fini(adev);
> + r = amdgpu_vcn_sw_fini(adev, inst);
>
> kfree(adev->vcn.ip_dump);
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 23/32] drm/amdgpu: hw_init for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (21 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 22/32] drm/amdgpu: sw_fini " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 24/32] drm/amdgpu: suspend " boyuan.zhang
` (9 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_hw_init(), and perform
hw init ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 39 +++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 73 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 37 ++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 67 +++++++++++------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 21 ++++---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 21 ++++---
6 files changed, 123 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index ed972d843f93..f225a0b214d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -338,37 +338,36 @@ static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, j, r = 0;
+ int inst = ip_block->instance;
+ int i, r = 0;
if (amdgpu_sriov_vf(adev))
r = vcn_v2_5_sriov_start(adev);
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return r;
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.inst[j].ring_enc[0].sched.ready = true;
- adev->vcn.inst[j].ring_enc[1].sched.ready = false;
- adev->vcn.inst[j].ring_enc[2].sched.ready = false;
- adev->vcn.inst[j].ring_dec.sched.ready = true;
- } else {
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.inst[inst].ring_enc[0].sched.ready = true;
+ adev->vcn.inst[inst].ring_enc[1].sched.ready = false;
+ adev->vcn.inst[inst].ring_enc[2].sched.ready = false;
+ adev->vcn.inst[inst].ring_dec.sched.ready = true;
+ } else {
+
+ ring = &adev->vcn.inst[inst].ring_dec;
- ring = &adev->vcn.inst[j].ring_dec;
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ring->doorbell_index, inst);
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
- ring->doorbell_index, j);
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ ring = &adev->vcn.inst[inst].ring_enc[i];
r = amdgpu_ring_test_helper(ring);
if (r)
return r;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- ring = &adev->vcn.inst[j].ring_enc[i];
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c45bebeb0aaa..2d1835d06ecb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -345,8 +345,9 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
- int i, j, r;
+ int j, r;
if (amdgpu_sriov_vf(adev)) {
r = vcn_v3_0_start_sriov(adev);
@@ -354,57 +355,53 @@ static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
return r;
/* initialize VCN dec and enc ring buffers */
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, inst)) {
+ ring->sched.ready = false;
+ ring->no_scheduler = true;
+ dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
+ } else {
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v3_0_dec_ring_set_wptr(ring);
+ ring->sched.ready = true;
+ }
- ring = &adev->vcn.inst[i].ring_dec;
- if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ ring = &adev->vcn.inst[inst].ring_enc[j];
+ if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, inst)) {
ring->sched.ready = false;
ring->no_scheduler = true;
dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
} else {
ring->wptr = 0;
ring->wptr_old = 0;
- vcn_v3_0_dec_ring_set_wptr(ring);
+ vcn_v3_0_enc_ring_set_wptr(ring);
ring->sched.ready = true;
}
-
- for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
- ring = &adev->vcn.inst[i].ring_enc[j];
- if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
- ring->sched.ready = false;
- ring->no_scheduler = true;
- dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
- } else {
- ring->wptr = 0;
- ring->wptr_old = 0;
- vcn_v3_0_enc_ring_set_wptr(ring);
- ring->sched.ready = true;
- }
- }
}
- } else {
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ }
- ring = &adev->vcn.inst[i].ring_dec;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
- ring->doorbell_index, i);
+ ring = &adev->vcn.inst[inst].ring_dec;
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ring->doorbell_index, inst);
- for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
- ring = &adev->vcn.inst[i].ring_enc[j];
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
- }
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ ring = &adev->vcn.inst[inst].ring_enc[j];
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index c87b4e46f2b0..afe2eba9aac4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -299,37 +299,34 @@ static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r;
+ int inst = ip_block->instance;
+ int r;
if (amdgpu_sriov_vf(adev)) {
r = vcn_v4_0_start_sriov(adev);
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->wptr = 0;
- ring->wptr_old = 0;
- vcn_v4_0_unified_ring_set_wptr(ring);
- ring->sched.ready = true;
- }
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v4_0_unified_ring_set_wptr(ring);
+ ring->sched.ready = true;
} else {
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ring = &adev->vcn.inst[i].ring_enc[0];
+ ring = &adev->vcn.inst[inst].ring_enc[0];
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
- ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * inst), inst);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 0b55d801ae88..0dc26dc173cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -257,49 +257,46 @@ static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r, vcn_inst;
+ int inst = ip_block->instance;
+ int r = 0, vcn_inst;
if (amdgpu_sriov_vf(adev)) {
r = vcn_v4_0_3_start_sriov(adev);
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->wptr = 0;
- ring->wptr_old = 0;
- vcn_v4_0_3_unified_ring_set_wptr(ring);
- ring->sched.ready = true;
- }
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v4_0_3_unified_ring_set_wptr(ring);
+ ring->sched.ready = true;
} else {
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
- ring = &adev->vcn.inst[i].ring_enc[0];
-
- if (ring->use_doorbell) {
- adev->nbio.funcs->vcn_doorbell_range(
- adev, ring->use_doorbell,
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst,
- adev->vcn.inst[i].aid_id);
-
- WREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL,
- ring->doorbell_index
- << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- /* Read DB_CTRL to flush the write DB_CTRL command. */
- RREG32_SOC15(
- VCN, GET_INST(VCN, ring->me),
- regVCN_RB1_DB_CTRL);
- }
-
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
+ vcn_inst = GET_INST(VCN, inst);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+
+ if (ring->use_doorbell) {
+ adev->nbio.funcs->vcn_doorbell_range(
+ adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 9 * vcn_inst,
+ adev->vcn.inst[inst].aid_id);
+
+ WREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL,
+ ring->doorbell_index
+ << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ /* Read DB_CTRL to flush the write DB_CTRL command. */
+ RREG32_SOC15(
+ VCN, GET_INST(VCN, ring->me),
+ regVCN_RB1_DB_CTRL);
}
+
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
}
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index b88fdb00cc5e..36e4477c99f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -268,21 +268,20 @@ static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r;
+ int inst = ip_block->instance;
+ int r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ring = &adev->vcn.inst[i].ring_enc[0];
+ ring = &adev->vcn.inst[inst].ring_enc[0];
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
- ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * inst), inst);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 15cdc7be9062..687d413a50b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -232,21 +232,20 @@ static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r;
+ int inst = ip_block->instance;
+ int r;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ring = &adev->vcn.inst[i].ring_enc[0];
+ ring = &adev->vcn.inst[inst].ring_enc[0];
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
- ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * inst), inst);
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 24/32] drm/amdgpu: suspend for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (22 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 23/32] drm/amdgpu: hw_init " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 25/32] drm/amdgpu: resume " boyuan.zhang
` (8 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_suspend(), and perform
suspend ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 35 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 6 +++--
10 files changed, 50 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 307615ffeb79..968355228095 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -294,40 +294,39 @@ bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type t
return ret;
}
-int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+int amdgpu_vcn_suspend(struct amdgpu_device *adev, int inst)
{
unsigned int size;
void *ptr;
- int i, idx;
+ int idx;
bool in_ras_intr = amdgpu_ras_intr_triggered();
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
- cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
/* err_event_athub will corrupt VCPU buffer, so we need to
* restore fw data and clear buffer in amdgpu_vcn_resume() */
if (in_ras_intr)
return 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->vcn.inst[i].vcpu_bo == NULL)
- return 0;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
- ptr = adev->vcn.inst[i].cpu_addr;
+ if (adev->vcn.inst[inst].vcpu_bo == NULL)
+ return 0;
- adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
- if (!adev->vcn.inst[i].saved_bo)
- return -ENOMEM;
+ size = amdgpu_bo_size(adev->vcn.inst[inst].vcpu_bo);
+ ptr = adev->vcn.inst[inst].cpu_addr;
- if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
- drm_dev_exit(idx);
- }
+ adev->vcn.inst[inst].saved_bo = kvmalloc(size, GFP_KERNEL);
+ if (!adev->vcn.inst[inst].saved_bo)
+ return -ENOMEM;
+
+ if (drm_dev_enter(adev_to_drm(adev), &idx)) {
+ memcpy_fromio(adev->vcn.inst[inst].saved_bo, ptr, size);
+ drm_dev_exit(idx);
}
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 883b9f9776a1..0695433a269c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -486,7 +486,7 @@ enum vcn_ring_type {
int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_suspend(struct amdgpu_device *adev);
+int amdgpu_vcn_suspend(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 8203f80be316..806ed6c550fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -226,7 +226,7 @@ static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
int inst = ip_block->instance;
int r;
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -300,9 +300,10 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
{
- int r;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
bool idle_work_unexecuted;
+ int r;
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (idle_work_unexecuted) {
@@ -314,7 +315,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 0481a07054eb..397aec069862 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -257,7 +257,7 @@ static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -335,13 +335,15 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v2_0_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index f225a0b214d0..088a3521ac5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -316,7 +316,7 @@ static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -412,13 +412,15 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v2_5_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 2d1835d06ecb..bd8322cdbcfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -325,7 +325,7 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -444,13 +444,15 @@ static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v3_0_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index afe2eba9aac4..c195742ee4f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -277,7 +277,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -372,13 +372,15 @@ static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v4_0_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 0dc26dc173cb..ed0f25f7ff5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -235,7 +235,7 @@ static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -331,13 +331,15 @@ static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v4_0_3_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 36e4477c99f3..75ea91749276 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -246,7 +246,7 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -323,13 +323,15 @@ static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v4_0_5_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 687d413a50b7..69aa555b7227 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -210,7 +210,7 @@ static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
drm_dev_exit(idx);
}
- r = amdgpu_vcn_suspend(adev);
+ r = amdgpu_vcn_suspend(adev, inst);
if (r)
return r;
@@ -287,13 +287,15 @@ static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
*/
static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block)
{
+ struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int r;
r = vcn_v5_0_0_hw_fini(ip_block);
if (r)
return r;
- r = amdgpu_vcn_suspend(ip_block->adev);
+ r = amdgpu_vcn_suspend(adev, inst);
return r;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 25/32] drm/amdgpu: resume for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (23 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 24/32] drm/amdgpu: suspend " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 26/32] drm/amdgpu: setup_ucode " boyuan.zhang
` (7 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_resume(), and perform
resume ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 60 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 +-
10 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 968355228095..67081fb4e96d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -330,47 +330,47 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev, int inst)
return 0;
}
-int amdgpu_vcn_resume(struct amdgpu_device *adev)
+int amdgpu_vcn_resume(struct amdgpu_device *adev, int inst)
{
unsigned int size;
void *ptr;
- int i, idx;
+ int idx;
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->vcn.inst[i].vcpu_bo == NULL)
- return -EINVAL;
+ if (adev->vcn.inst[inst].vcpu_bo == NULL)
+ return -EINVAL;
+
+ size = amdgpu_bo_size(adev->vcn.inst[inst].vcpu_bo);
+ ptr = adev->vcn.inst[inst].cpu_addr;
- size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
- ptr = adev->vcn.inst[i].cpu_addr;
+ if (adev->vcn.inst[inst].saved_bo != NULL) {
+ if (drm_dev_enter(adev_to_drm(adev), &idx)) {
+ memcpy_toio(ptr, adev->vcn.inst[inst].saved_bo, size);
+ drm_dev_exit(idx);
+ }
+ kvfree(adev->vcn.inst[inst].saved_bo);
+ adev->vcn.inst[inst].saved_bo = NULL;
+ } else {
+ const struct common_firmware_header *hdr;
+ unsigned int offset;
- if (adev->vcn.inst[i].saved_bo != NULL) {
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
+ memcpy_toio(adev->vcn.inst[inst].cpu_addr,
+ adev->vcn.inst[inst].fw->data + offset,
+ le32_to_cpu(hdr->ucode_size_bytes));
drm_dev_exit(idx);
}
- kvfree(adev->vcn.inst[i].saved_bo);
- adev->vcn.inst[i].saved_bo = NULL;
- } else {
- const struct common_firmware_header *hdr;
- unsigned int offset;
-
- hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
- if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_toio(adev->vcn.inst[i].cpu_addr,
- adev->vcn.inst[i].fw->data + offset,
- le32_to_cpu(hdr->ucode_size_bytes));
- drm_dev_exit(idx);
- }
- size -= le32_to_cpu(hdr->ucode_size_bytes);
- ptr += le32_to_cpu(hdr->ucode_size_bytes);
- }
- memset_io(ptr, 0, size);
+ size -= le32_to_cpu(hdr->ucode_size_bytes);
+ ptr += le32_to_cpu(hdr->ucode_size_bytes);
}
+ memset_io(ptr, 0, size);
}
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 0695433a269c..72341b7027a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -487,7 +487,7 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_suspend(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_resume(struct amdgpu_device *adev);
+int amdgpu_vcn_resume(struct amdgpu_device *adev, int inst);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 806ed6c550fb..11153ca0c3d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -156,7 +156,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -331,7 +331,7 @@ static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 397aec069862..d36ab4368a25 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -161,7 +161,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -359,7 +359,7 @@ static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 088a3521ac5a..963086b47b1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -191,7 +191,7 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -436,7 +436,7 @@ static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index bd8322cdbcfe..098a523073b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -174,7 +174,7 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -468,7 +468,7 @@ static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index c195742ee4f7..bdc3f37fe44a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -182,7 +182,7 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -396,7 +396,7 @@ static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index ed0f25f7ff5f..c44adeb4494c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -139,7 +139,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -355,7 +355,7 @@ static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 75ea91749276..dd392b787790 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -144,7 +144,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -347,7 +347,7 @@ static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 69aa555b7227..b9fdb91fa86c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -128,7 +128,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
amdgpu_vcn_setup_ucode(adev);
- r = amdgpu_vcn_resume(adev);
+ r = amdgpu_vcn_resume(adev, inst);
if (r)
return r;
@@ -311,7 +311,7 @@ static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block)
{
int r;
- r = amdgpu_vcn_resume(ip_block->adev);
+ r = amdgpu_vcn_resume(ip_block->adev, ip_block->instance);
if (r)
return r;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 26/32] drm/amdgpu: setup_ucode for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (24 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 25/32] drm/amdgpu: resume " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 27/32] drm/amdgpu: set funcs " boyuan.zhang
` (6 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to amdgpu_vcn_setup_ucode(), and perform
setup ucode ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 37 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +-
10 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 67081fb4e96d..e442430e7e72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1044,34 +1044,31 @@ enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
}
}
-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int inst)
{
- int i;
unsigned int idx;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
const struct common_firmware_header *hdr;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
- /* currently only support 2 FW instances */
- if (i >= 2) {
- dev_info(adev->dev, "More then 2 VCN FW instances!\n");
- break;
- }
- idx = AMDGPU_UCODE_ID_VCN + i;
- adev->firmware.ucode[idx].ucode_id = idx;
- adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(4, 0, 3))
- break;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data;
+ /* currently only support 2 FW instances */
+ if (inst >= 2) {
+ dev_info(adev->dev, "More then 2 VCN FW instances!\n");
+ return;
}
+ idx = AMDGPU_UCODE_ID_VCN + inst;
+ adev->firmware.ucode[idx].ucode_id = idx;
+ adev->firmware.ucode[idx].fw = adev->vcn.inst[inst].fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(4, 0, 3))
+ return;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 72341b7027a2..88f46a7d02de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -505,7 +505,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int inst);
void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 11153ca0c3d9..ab06c4173b66 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -154,7 +154,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
/* Override the work func */
adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index d36ab4368a25..59c6458c99af 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -159,7 +159,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 963086b47b1d..d90aa2a9f94e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -189,7 +189,7 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 098a523073b8..3547798ec335 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -172,7 +172,7 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index bdc3f37fe44a..eec9d4a0a0b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -180,7 +180,7 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index c44adeb4494c..f78c006aec27 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -137,7 +137,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index dd392b787790..31f05f377ffe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -142,7 +142,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index b9fdb91fa86c..c0746684eea4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -126,7 +126,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 27/32] drm/amdgpu: set funcs for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (25 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 26/32] drm/amdgpu: setup_ucode " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 28/32] drm/amdgpu: print_ip_state " boyuan.zhang
` (5 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass instance parameter to set_dec_ring_funcs(), set_enc_ring_funcs(),
and set_irq_funcs(), and perform function setup ONLY for the given vcn
instance, instead of for all vcn instances. Modify each vcn generation
accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 59 +++++++++++------------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 62 +++++++++++--------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 46 ++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 31 ++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 36 ++++++--------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 36 ++++++--------
6 files changed, 112 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index d90aa2a9f94e..b0d14330722b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -92,9 +92,9 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
};
-static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
@@ -139,9 +139,9 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
adev->vcn.num_enc_rings = 2;
}
- vcn_v2_5_set_dec_ring_funcs(adev);
- vcn_v2_5_set_enc_ring_funcs(adev);
- vcn_v2_5_set_irq_funcs(adev);
+ vcn_v2_5_set_dec_ring_funcs(adev, inst);
+ vcn_v2_5_set_enc_ring_funcs(adev, inst);
+ vcn_v2_5_set_irq_funcs(adev, inst);
vcn_v2_5_set_ras_funcs(adev);
return amdgpu_vcn_early_init(adev, inst);
@@ -1737,29 +1737,25 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
};
-static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
- adev->vcn.inst[i].ring_dec.me = i;
- }
+ adev->vcn.inst[inst].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_dec.me = inst;
}
-static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i, j;
+ int i;
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
- adev->vcn.inst[j].ring_enc[i].me = j;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ adev->vcn.inst[inst].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[i].me = inst;
}
}
@@ -1904,19 +1900,16 @@ static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = {
.process = amdgpu_vcn_process_poison_irq,
};
-static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v2_5_irq_funcs;
- adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
- }
+ adev->vcn.inst[inst].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs;
}
static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 3547798ec335..9a9acec4c4ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -102,9 +102,9 @@ static int amdgpu_ih_clientid_vcns[] = {
};
static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
-static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
@@ -144,9 +144,9 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
adev->vcn.num_enc_rings = 2;
}
- vcn_v3_0_set_dec_ring_funcs(adev);
- vcn_v3_0_set_enc_ring_funcs(adev);
- vcn_v3_0_set_irq_funcs(adev);
+ vcn_v3_0_set_dec_ring_funcs(adev, inst);
+ vcn_v3_0_set_enc_ring_funcs(adev, inst);
+ vcn_v3_0_set_irq_funcs(adev, inst);
return amdgpu_vcn_early_init(adev, inst);
}
@@ -2062,34 +2062,28 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
};
-static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- if (!DEC_SW_RING_ENABLED)
- adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
- else
- adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
- adev->vcn.inst[i].ring_dec.me = i;
- }
+ if (!DEC_SW_RING_ENABLED)
+ adev->vcn.inst[inst].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
+ else
+ adev->vcn.inst[inst].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_dec.me = inst;
}
-static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i, j;
+ int j;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
- adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
- adev->vcn.inst[i].ring_enc[j].me = i;
- }
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ adev->vcn.inst[inst].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[j].me = inst;
}
}
@@ -2231,17 +2225,13 @@ static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
.process = vcn_v3_0_process_interrupt,
};
-static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
- }
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v3_0_irq_funcs;
}
static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index eec9d4a0a0b9..ff256fb4d054 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -94,8 +94,8 @@ static int amdgpu_ih_clientid_vcns[] = {
};
static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
-static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
@@ -127,8 +127,8 @@ static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block)
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
- vcn_v4_0_set_unified_ring_funcs(adev);
- vcn_v4_0_set_irq_funcs(adev);
+ vcn_v4_0_set_unified_ring_funcs(adev, inst);
+ vcn_v4_0_set_irq_funcs(adev, inst);
vcn_v4_0_set_ras_funcs(adev);
return amdgpu_vcn_early_init(adev, inst);
@@ -1923,21 +1923,17 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
*
* Set unified ring functions
*/
-static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
- vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
+ if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2))
+ vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true;
- adev->vcn.inst[i].ring_enc[0].funcs =
- (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
- adev->vcn.inst[i].ring_enc[0].me = i;
- }
+ adev->vcn.inst[inst].ring_enc[0].funcs =
+ (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[0].me = inst;
}
/**
@@ -2135,20 +2131,16 @@ static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = {
*
* Set VCN block interrupt irq functions
*/
-static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v4_0_irq_funcs;
- adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
- }
+ adev->vcn.inst[inst].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs;
}
static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index f78c006aec27..544c96e082b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -85,8 +85,8 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
(offset & 0x1FFFF)
static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
-static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
@@ -110,8 +110,8 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block)
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
- vcn_v4_0_3_set_unified_ring_funcs(adev);
- vcn_v4_0_3_set_irq_funcs(adev);
+ vcn_v4_0_3_set_unified_ring_funcs(adev, inst);
+ vcn_v4_0_3_set_irq_funcs(adev, inst);
vcn_v4_0_3_set_ras_funcs(adev);
return amdgpu_vcn_early_init(adev, inst);
@@ -1525,17 +1525,15 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
*
* Set unified ring functions
*/
-static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i, vcn_inst;
+ int vcn_inst;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
- adev->vcn.inst[i].ring_enc[0].me = i;
- vcn_inst = GET_INST(VCN, i);
- adev->vcn.inst[i].aid_id =
- vcn_inst / adev->vcn.num_inst_per_aid;
- }
+ adev->vcn.inst[inst].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[0].me = inst;
+ vcn_inst = GET_INST(VCN, inst);
+ adev->vcn.inst[inst].aid_id =
+ vcn_inst / adev->vcn.num_inst_per_aid;
}
/**
@@ -1718,13 +1716,10 @@ static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = {
*
* Set VCN block interrupt irq functions
*/
-static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
+ adev->vcn.inst->irq.num_types++;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- adev->vcn.inst->irq.num_types++;
- }
adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 31f05f377ffe..880353f75296 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -93,8 +93,8 @@ static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN1
};
-static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
@@ -116,8 +116,8 @@ static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
- vcn_v4_0_5_set_unified_ring_funcs(adev);
- vcn_v4_0_5_set_irq_funcs(adev);
+ vcn_v4_0_5_set_unified_ring_funcs(adev, inst);
+ vcn_v4_0_5_set_irq_funcs(adev, inst);
return amdgpu_vcn_early_init(adev, inst);
}
@@ -1424,17 +1424,13 @@ static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
*
* Set unified ring functions
*/
-static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
- adev->vcn.inst[i].ring_enc[0].me = i;
- }
+ adev->vcn.inst[inst].ring_enc[0].funcs = &vcn_v4_0_5_unified_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[0].me = inst;
}
/**
@@ -1599,17 +1595,13 @@ static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = {
*
* Set VCN block interrupt irq functions
*/
-static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v4_0_5_irq_funcs;
- }
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v4_0_5_irq_funcs;
}
static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index c0746684eea4..a4d1b9a086b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -76,8 +76,8 @@ static int amdgpu_ih_clientid_vcns[] = {
SOC15_IH_CLIENTID_VCN1
};
-static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
@@ -100,8 +100,8 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
/* re-use enc ring as unified ring */
adev->vcn.num_enc_rings = 1;
- vcn_v5_0_0_set_unified_ring_funcs(adev);
- vcn_v5_0_0_set_irq_funcs(adev);
+ vcn_v5_0_0_set_unified_ring_funcs(adev, inst);
+ vcn_v5_0_0_set_irq_funcs(adev, inst);
return amdgpu_vcn_early_init(adev, inst);
}
@@ -1151,17 +1151,13 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = {
*
* Set unified ring functions
*/
-static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs;
- adev->vcn.inst[i].ring_enc[0].me = i;
- }
+ adev->vcn.inst[inst].ring_enc[0].funcs = &vcn_v5_0_0_unified_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[0].me = inst;
}
/**
@@ -1326,17 +1322,13 @@ static const struct amdgpu_irq_src_funcs vcn_v5_0_0_irq_funcs = {
*
* Set VCN block interrupt irq functions
*/
-static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v5_0_0_irq_funcs;
- }
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v5_0_0_irq_funcs;
}
static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 28/32] drm/amdgpu: print_ip_state for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (26 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 27/32] drm/amdgpu: set funcs " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-22 8:40 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 29/32] drm/amdgpu: dump_ip_state " boyuan.zhang
` (4 subsequent siblings)
32 siblings, 1 reply; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Perform print_ip_state only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 33 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 33 ++++++++++++-------------
8 files changed, 128 insertions(+), 136 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index ab06c4173b66..9255bcfc6c3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1933,7 +1933,8 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
uint32_t inst_off, is_powered;
@@ -1941,24 +1942,22 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 59c6458c99af..94f000ed4895 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2041,7 +2041,8 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
uint32_t inst_off, is_powered;
@@ -2049,24 +2050,22 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index b0d14330722b..7c9a0169215e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1915,7 +1915,8 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
uint32_t inst_off, is_powered;
@@ -1923,24 +1924,22 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 9a9acec4c4ce..061c958700d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2237,7 +2237,8 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
uint32_t inst_off;
bool is_powered;
@@ -2246,24 +2247,22 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index ff256fb4d054..fdf346bf3e34 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2146,7 +2146,8 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
uint32_t inst_off, is_powered;
@@ -2154,24 +2155,22 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 544c96e082b9..daaf2fb6b3e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1726,7 +1726,8 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
uint32_t inst_off, is_powered;
@@ -1734,24 +1735,22 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 880353f75296..ff8db22b9614 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1607,7 +1607,8 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
uint32_t inst_off, is_powered;
@@ -1615,24 +1616,22 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index a4d1b9a086b2..c83a5c09f410 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1334,7 +1334,8 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
uint32_t inst_off, is_powered;
@@ -1342,24 +1343,22 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
return;
drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i)) {
- drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst)) {
+ drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
+ return;
+ }
- inst_off = i * reg_count;
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered) {
- drm_printf(p, "\nActive Instance:VCN%d\n", i);
- for (j = 0; j < reg_count; j++)
- drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
- adev->vcn.ip_dump[inst_off + j]);
- } else {
- drm_printf(p, "\nInactive Instance:VCN%d\n", i);
- }
+ if (is_powered) {
+ drm_printf(p, "\nActive Instance:VCN%d\n", inst);
+ for (j = 0; j < reg_count; j++)
+ drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
+ adev->vcn.ip_dump[inst_off + j]);
+ } else {
+ drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 28/32] drm/amdgpu: print_ip_state for each vcn instance
2024-10-17 13:20 ` [PATCH 28/32] drm/amdgpu: print_ip_state " boyuan.zhang
@ 2024-10-22 8:40 ` Khatri, Sunil
0 siblings, 0 replies; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 8:40 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
[-- Attachment #1: Type: text/plain, Size: 17538 bytes --]
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com
<mailto:christian.koenig@amd.com>>
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Perform print_ip_state only for the instance of the current vcn IP block,
> instead of perform it for all vcn instances.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 33 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 33 ++++++++++++-------------
> 8 files changed, 128 insertions(+), 136 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index ab06c4173b66..9255bcfc6c3d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1933,7 +1933,8 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
> static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
> uint32_t inst_off, is_powered;
>
> @@ -1941,24 +1942,22 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 59c6458c99af..94f000ed4895 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -2041,7 +2041,8 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
> static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
> uint32_t inst_off, is_powered;
>
> @@ -2049,24 +2050,22 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index b0d14330722b..7c9a0169215e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1915,7 +1915,8 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
> uint32_t inst_off, is_powered;
>
> @@ -1923,24 +1924,22 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 9a9acec4c4ce..061c958700d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2237,7 +2237,8 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
> uint32_t inst_off;
> bool is_powered;
> @@ -2246,24 +2247,22 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index ff256fb4d054..fdf346bf3e34 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -2146,7 +2146,8 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
> uint32_t inst_off, is_powered;
>
> @@ -2154,24 +2155,22 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 544c96e082b9..daaf2fb6b3e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1726,7 +1726,8 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> uint32_t inst_off, is_powered;
>
> @@ -1734,24 +1735,22 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 880353f75296..ff8db22b9614 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1607,7 +1607,8 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
> uint32_t inst_off, is_powered;
>
> @@ -1615,24 +1616,22 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index a4d1b9a086b2..c83a5c09f410 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1334,7 +1334,8 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev, int inst)
> static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
> uint32_t inst_off, is_powered;
>
> @@ -1342,24 +1343,22 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> return;
>
> drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i)) {
> - drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> - continue;
> - }
> + if (adev->vcn.harvest_config & (1 << inst)) {
> + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", inst);
> + return;
> + }
>
> - inst_off = i * reg_count;
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered) {
> - drm_printf(p, "\nActive Instance:VCN%d\n", i);
> - for (j = 0; j < reg_count; j++)
> - drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
> - adev->vcn.ip_dump[inst_off + j]);
> - } else {
> - drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> - }
> + if (is_powered) {
> + drm_printf(p, "\nActive Instance:VCN%d\n", inst);
> + for (j = 0; j < reg_count; j++)
> + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
> + adev->vcn.ip_dump[inst_off + j]);
> + } else {
> + drm_printf(p, "\nInactive Instance:VCN%d\n", inst);
> }
> }
>
[-- Attachment #2: Type: text/html, Size: 53862 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (27 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 28/32] drm/amdgpu: print_ip_state " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-22 8:56 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 30/32] drm/amdgpu: wait_for_idle " boyuan.zhang
` (3 subsequent siblings)
32 siblings, 1 reply; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Perform dump_ip_state only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 +++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
8 files changed, 112 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 9255bcfc6c3d..27e0f206c9dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
@@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
}
static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 94f000ed4895..665b749c5ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
@@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
}
static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7c9a0169215e..5332b2903ce1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
@@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
}
static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 061c958700d8..40a3d29d4e71 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
@@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
}
static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index fdf346bf3e34..3b2f4f1e0939 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
@@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
- i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
+ inst));
}
static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index daaf2fb6b3e5..be03d31cb206 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off, inst_id;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
@@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- inst_id = GET_INST(VCN, i);
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
- inst_id));
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+
+ inst_id = GET_INST(VCN, inst);
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
+ inst_id));
}
static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ff8db22b9614..43b1f3d06157 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
@@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
- i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
+ inst));
}
static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index c83a5c09f410..65554c4e86cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
@@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
}
static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
2024-10-17 13:20 ` [PATCH 29/32] drm/amdgpu: dump_ip_state " boyuan.zhang
@ 2024-10-22 8:56 ` Khatri, Sunil
2024-10-22 8:59 ` Khatri, Sunil
0 siblings, 1 reply; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 8:56 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher
[-- Attachment #1: Type: text/plain, Size: 18046 bytes --]
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com
<mailto:christian.koenig@amd.com>>
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Perform dump_ip_state only for the instance of the current vcn IP block,
> instead of perform it for all vcn instances.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 +++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
> 8 files changed, 112 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 9255bcfc6c3d..27e0f206c9dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
> @@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 94f000ed4895..665b749c5ac0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
> @@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 7c9a0169215e..5332b2903ce1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
> @@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
Since this for loop is removed which dump for each instances,clear my
understanding here, there are multiple ip_blocks for vcn now and
ip_block->instance is 0, 1, 2, 3 etc representing one instance ?
Assuming the use case of 2 instances so first time when
vcn_v2_5_dump_ip_state is called it will comes with ip_block->instance =
0 and then 1 and 2 in sequence as we are dumping that information in
loop and storing in coredump in that sequence only.
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
> Storage we have linear to accomodate each vcn instance. So we need to make sure that when dump is called for instance sequentially we are adding values in vcn.ip_dump in same order so print should give right value else there could be a mismatch based on existing logic. Please try to cause a dump and hack around the code so is_powered is bypassed and we dump the values for each instance thats the only way to see if its working fine.
By looking at the code it seems it should work but there are some vcn
variable which i am not so sure in new design. Also patch for dump
should come first and then print to reverse the order of 28 and 29 patch.
But testing is needed to make sure its working fine.
Regards
Sunil khatri
> }
>
> static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 061c958700d8..40a3d29d4e71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
> @@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index fdf346bf3e34..3b2f4f1e0939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
> @@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
> - i));
> - }
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
> + inst));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index daaf2fb6b3e5..be03d31cb206 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off, inst_id;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> @@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> -
> - inst_id = GET_INST(VCN, i);
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
> - inst_id));
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
> +
> + inst_id = GET_INST(VCN, inst);
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
> + inst_id));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index ff8db22b9614..43b1f3d06157 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
> @@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
> - i));
> - }
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
> + inst));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index c83a5c09f410..65554c4e86cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
> @@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
[-- Attachment #2: Type: text/html, Size: 18708 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread* RE: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
2024-10-22 8:56 ` Khatri, Sunil
@ 2024-10-22 8:59 ` Khatri, Sunil
2024-10-22 12:37 ` Khatri, Sunil
0 siblings, 1 reply; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 8:59 UTC (permalink / raw)
To: Khatri, Sunil, Zhang, Boyuan, amd-gfx@lists.freedesktop.org,
Liu, Leo, Koenig, Christian, Deucher, Alexander
[-- Attachment #1: Type: text/plain, Size: 20680 bytes --]
[AMD Official Use Only - AMD Internal Distribution Only]
Validate the ip dump date first for vcn before committing. I reviewed based on the code changes as it looks fine.
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Khatri, Sunil
Sent: Tuesday, October 22, 2024 2:27 PM
To: Zhang, Boyuan <Boyuan.Zhang@amd.com>; amd-gfx@lists.freedesktop.org; Liu, Leo <Leo.Liu@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com<mailto:christian.koenig@amd.com>>
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com<mailto:boyuan.zhang@amd.com> wrote:
From: Boyuan Zhang <boyuan.zhang@amd.com><mailto:boyuan.zhang@amd.com>
Perform dump_ip_state only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com><mailto:boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 27 +++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 +++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
8 files changed, 112 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 9255bcfc6c3d..27e0f206c9dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
@@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
}
static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 94f000ed4895..665b749c5ac0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
@@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
}
static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7c9a0169215e..5332b2903ce1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
@@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
Since this for loop is removed which dump for each instances,clear my understanding here, there are multiple ip_blocks for vcn now and ip_block->instance is 0, 1, 2, 3 etc representing one instance ?
Assuming the use case of 2 instances so first time when vcn_v2_5_dump_ip_state is called it will comes with ip_block->instance = 0 and then 1 and 2 in sequence as we are dumping that information in loop and storing in coredump in that sequence only.
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
Storage we have linear to accomodate each vcn instance. So we need to make sure that when dump is called for instance sequentially we are adding values in vcn.ip_dump in same order so print should give right value else there could be a mismatch based on existing logic. Please try to cause a dump and hack around the code so is_powered is bypassed and we dump the values for each instance thats the only way to see if its working fine.
By looking at the code it seems it should work but there are some vcn variable which i am not so sure in new design. Also patch for dump should come first and then print to reverse the order of 28 and 29 patch.
But testing is needed to make sure its working fine.
Regards
Sunil khatri
}
static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 061c958700d8..40a3d29d4e71 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
@@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
}
static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index fdf346bf3e34..3b2f4f1e0939 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
@@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
- i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
+ inst));
}
static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index daaf2fb6b3e5..be03d31cb206 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off, inst_id;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
@@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
-
- inst_id = GET_INST(VCN, i);
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
- inst_id));
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+
+ inst_id = GET_INST(VCN, inst);
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
+ inst_id));
}
static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ff8db22b9614..43b1f3d06157 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
@@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
-
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
- i));
- }
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
+ inst));
}
static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index c83a5c09f410..65554c4e86cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, j;
+ int inst = ip_block->instance;
+ int j;
bool is_powered;
uint32_t inst_off;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
@@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
if (!adev->vcn.ip_dump)
return;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- inst_off = i * reg_count;
- /* mmUVD_POWER_STATUS is always readable and is first element of the array */
- adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
- is_powered = (adev->vcn.ip_dump[inst_off] &
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+ inst_off = inst * reg_count;
+ /* mmUVD_POWER_STATUS is always readable and is first element of the array */
+ adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
+ is_powered = (adev->vcn.ip_dump[inst_off] &
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
- if (is_powered)
- for (j = 1; j < reg_count; j++)
- adev->vcn.ip_dump[inst_off + j] =
- RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
- }
+ if (is_powered)
+ for (j = 1; j < reg_count; j++)
+ adev->vcn.ip_dump[inst_off + j] =
+ RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
}
static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
[-- Attachment #2: Type: text/html, Size: 42813 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
2024-10-22 8:59 ` Khatri, Sunil
@ 2024-10-22 12:37 ` Khatri, Sunil
0 siblings, 0 replies; 45+ messages in thread
From: Khatri, Sunil @ 2024-10-22 12:37 UTC (permalink / raw)
To: Zhang, Boyuan, amd-gfx@lists.freedesktop.org, Liu, Leo,
Koenig, Christian, Deucher, Alexander
[-- Attachment #1: Type: text/plain, Size: 25723 bytes --]
Hello Boyuan
It probably wont work fine as memory allocated for core dump also needs
to change based on ip design where not we have an ip_block for each
instance too.
So here is what i think and let me know if that sounds fine with you.
Once you get the review complete for patches #1 - #27 get them merged
and on that code base i will rework the changes needs for core dump for
vcn and then you could get rest of your changes reviewed and merged.
Also i am assuming there is no dependency of patches if they are in
order and build independently so you can leave the ipdump patches #28
and #29 and let the review process complete. I need to change them
according to new design and validate too.
Ignore the review on these two patches till then :)
Regards
Sunil Khatri
On 10/22/2024 2:29 PM, Khatri, Sunil wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>
> Validate the ip dump date first for vcn before committing. I reviewed
> based on the code changes as it looks fine.
>
> *From:*amd-gfx <amd-gfx-bounces@lists.freedesktop.org> *On Behalf Of
> *Khatri, Sunil
> *Sent:* Tuesday, October 22, 2024 2:27 PM
> *To:* Zhang, Boyuan <Boyuan.Zhang@amd.com>;
> amd-gfx@lists.freedesktop.org; Liu, Leo <Leo.Liu@amd.com>; Koenig,
> Christian <Christian.Koenig@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>
> *Subject:* Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn
> instance
>
> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com
> <mailto:christian.koenig@amd.com>>
>
> On 10/17/2024 6:50 PM, boyuan.zhang@amd.com
> <mailto:boyuan.zhang@amd.com> wrote:
>
> From: Boyuan Zhang<boyuan.zhang@amd.com> <mailto:boyuan.zhang@amd.com>
>
> Perform dump_ip_state only for the instance of the current vcn IP block,
>
> instead of perform it for all vcn instances.
>
> Signed-off-by: Boyuan Zhang<boyuan.zhang@amd.com> <mailto:boyuan.zhang@amd.com>
>
> ---
>
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 +++++++++----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 27 +++++++++----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +++++++++----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 27 +++++++++----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 +++++++++++-----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
>
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
>
> 8 files changed, 112 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>
> index 9255bcfc6c3d..27e0f206c9dd 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>
> @@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
>
> @@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
>
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
>
> - }
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>
> index 94f000ed4895..665b749c5ac0 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>
> @@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
>
> @@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
>
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
>
> - }
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>
> index 7c9a0169215e..5332b2903ce1 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>
> @@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
>
> @@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> Since this for loop is removed which dump for each instances,clear my
> understanding here, there are multiple ip_blocks for vcn now and
> ip_block->instance is 0, 1, 2, 3 etc representing one instance ?
> Assuming the use case of 2 instances so first time when
> vcn_v2_5_dump_ip_state is called it will comes with ip_block->instance
> = 0 and then 1 and 2 in sequence as we are dumping that information in
> loop and storing in coredump in that sequence only.
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
>
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
>
> - }
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
>
> Storage we have linear to accomodate each vcn instance. So we need to make sure that when dump is called for instance sequentially we are adding values in vcn.ip_dump in same order so print should give right value else there could be a mismatch based on existing logic. Please try to cause a dump and hack around the code so is_powered is bypassed and we dump the values for each instance thats the only way to see if its working fine.
>
> By looking at the code it seems it should work but there are some vcn
> variable which i am not so sure in new design. Also patch for dump
> should come first and then print to reverse the order of 28 and 29 patch.
> But testing is needed to make sure its working fine.
> Regards
> Sunil khatri
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>
> index 061c958700d8..40a3d29d4e71 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>
> @@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
>
> @@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
>
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
>
> - }
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>
> index fdf346bf3e34..3b2f4f1e0939 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>
> @@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
>
> @@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> -
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
>
> - i));
>
> - }
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> +
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
>
> + inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>
> index daaf2fb6b3e5..be03d31cb206 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>
> @@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
>
> static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off, inst_id;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>
> @@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> -
>
> - inst_id = GET_INST(VCN, i);
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> -
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
>
> - inst_id));
>
> - }
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
> +
>
> + inst_id = GET_INST(VCN, inst);
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> +
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
>
> + inst_id));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>
> index ff8db22b9614..43b1f3d06157 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>
> @@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
>
> static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
>
> @@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> -
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
>
> - i));
>
> - }
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> +
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
>
> + inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>
> index c83a5c09f410..65554c4e86cd 100644
>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>
> @@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
>
> static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> {
>
> struct amdgpu_device *adev = ip_block->adev;
>
> - int i, j;
>
> + int inst = ip_block->instance;
>
> + int j;
>
> bool is_powered;
>
> uint32_t inst_off;
>
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
>
> @@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
>
> if (!adev->vcn.ip_dump)
>
> return;
>
>
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>
> - if (adev->vcn.harvest_config & (1 << i))
>
> - continue;
>
> + if (adev->vcn.harvest_config & (1 << inst))
>
> + return;
>
>
>
> - inst_off = i * reg_count;
>
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
>
> - is_powered = (adev->vcn.ip_dump[inst_off] &
>
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> + inst_off = inst * reg_count;
>
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
>
> + is_powered = (adev->vcn.ip_dump[inst_off] &
>
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
>
>
> - if (is_powered)
>
> - for (j = 1; j < reg_count; j++)
>
> - adev->vcn.ip_dump[inst_off + j] =
>
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
>
> - }
>
> + if (is_powered)
>
> + for (j = 1; j < reg_count; j++)
>
> + adev->vcn.ip_dump[inst_off + j] =
>
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
>
> }
>
>
>
> static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
>
[-- Attachment #2: Type: text/html, Size: 41431 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH 30/32] drm/amdgpu: wait_for_idle for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (28 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 29/32] drm/amdgpu: dump_ip_state " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 31/32] drm/amdgpu: is_idle " boyuan.zhang
` (2 subsequent siblings)
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Perform wait_for_idle only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 18 +++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 ++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 17 ++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 13 ++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 17 ++++++++---------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 17 ++++++++---------
6 files changed, 47 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 5332b2903ce1..936d37b8fd3c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1777,16 +1777,16 @@ static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 40a3d29d4e71..d1074490fdc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2105,17 +2105,16 @@ static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 3b2f4f1e0939..a6d3425b499b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1968,17 +1968,16 @@ static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index be03d31cb206..258c14fdfd23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1566,14 +1566,13 @@ static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,
- UVD_STATUS__IDLE, UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, inst), regUVD_STATUS,
+ UVD_STATUS__IDLE, UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 43b1f3d06157..90a39a461e86 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1465,17 +1465,16 @@ static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 65554c4e86cd..456951bf304f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1192,17 +1192,16 @@ static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
+ if (ret)
+ return ret;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 31/32] drm/amdgpu: is_idle for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (29 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 30/32] drm/amdgpu: wait_for_idle " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-17 13:20 ` [PATCH 32/32] drm/amdgpu: set_powergating " boyuan.zhang
2024-10-22 6:25 ` [PATCH 00/32] Separating vcn power management by instance Christian König
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Perform is_idle only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 +++++------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 11 +++++------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 11 +++++------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 9 ++++-----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 11 +++++------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 11 +++++------
6 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 936d37b8fd3c..0b62729fca89 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1762,14 +1762,13 @@ static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev, int inst)
static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, inst, mmUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index d1074490fdc9..5b11062b873d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2090,14 +2090,13 @@ static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev, int inst)
static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, inst, mmUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index a6d3425b499b..69fff5df1c68 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1946,14 +1946,13 @@ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev, int inst
static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, inst, regUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 258c14fdfd23..cb30d5e5bc70 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1546,12 +1546,11 @@ static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev, int in
static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
- UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, GET_INST(VCN, inst), regUVD_STATUS) ==
+ UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 90a39a461e86..68397bea5a18 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1443,14 +1443,13 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev, int in
static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, inst, regUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 456951bf304f..fd78472b906a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1170,14 +1170,13 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev, int in
static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 1;
+ int inst = ip_block->instance;
+ int ret = 1;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
- }
+ ret &= (RREG32_SOC15(VCN, inst, regUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH 32/32] drm/amdgpu: set_powergating for each vcn instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (30 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 31/32] drm/amdgpu: is_idle " boyuan.zhang
@ 2024-10-17 13:20 ` boyuan.zhang
2024-10-22 6:25 ` [PATCH 00/32] Separating vcn power management by instance Christian König
32 siblings, 0 replies; 45+ messages in thread
From: boyuan.zhang @ 2024-10-17 13:20 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher; +Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Perform set_powergating_state only for the instance of the current vcn
IP block, instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 313 ++++++++++++------------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 19 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 20 +-
6 files changed, 199 insertions(+), 213 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 0b62729fca89..d41211d35013 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -612,114 +612,111 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
*
* Disable clock gating for VCN block
*/
-static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
{
uint32_t data;
- int i;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* UVD disable CGC */
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
- data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
- else
- data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
- data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
- data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
- data &= ~(UVD_CGC_GATE__SYS_MASK
- | UVD_CGC_GATE__UDEC_MASK
- | UVD_CGC_GATE__MPEG2_MASK
- | UVD_CGC_GATE__REGS_MASK
- | UVD_CGC_GATE__RBC_MASK
- | UVD_CGC_GATE__LMI_MC_MASK
- | UVD_CGC_GATE__LMI_UMC_MASK
- | UVD_CGC_GATE__IDCT_MASK
- | UVD_CGC_GATE__MPRD_MASK
- | UVD_CGC_GATE__MPC_MASK
- | UVD_CGC_GATE__LBSI_MASK
- | UVD_CGC_GATE__LRBBM_MASK
- | UVD_CGC_GATE__UDEC_RE_MASK
- | UVD_CGC_GATE__UDEC_CM_MASK
- | UVD_CGC_GATE__UDEC_IT_MASK
- | UVD_CGC_GATE__UDEC_DB_MASK
- | UVD_CGC_GATE__UDEC_MP_MASK
- | UVD_CGC_GATE__WCB_MASK
- | UVD_CGC_GATE__VCPU_MASK
- | UVD_CGC_GATE__MMSCH_MASK);
-
- WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
-
- SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
-
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
- | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
- | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
- | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
- | UVD_CGC_CTRL__SYS_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MODE_MASK
- | UVD_CGC_CTRL__MPEG2_MODE_MASK
- | UVD_CGC_CTRL__REGS_MODE_MASK
- | UVD_CGC_CTRL__RBC_MODE_MASK
- | UVD_CGC_CTRL__LMI_MC_MODE_MASK
- | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
- | UVD_CGC_CTRL__IDCT_MODE_MASK
- | UVD_CGC_CTRL__MPRD_MODE_MASK
- | UVD_CGC_CTRL__MPC_MODE_MASK
- | UVD_CGC_CTRL__LBSI_MODE_MASK
- | UVD_CGC_CTRL__LRBBM_MODE_MASK
- | UVD_CGC_CTRL__WCB_MODE_MASK
- | UVD_CGC_CTRL__VCPU_MODE_MASK
- | UVD_CGC_CTRL__MMSCH_MODE_MASK);
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- /* turn on */
- data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
- data |= (UVD_SUVD_CGC_GATE__SRE_MASK
- | UVD_SUVD_CGC_GATE__SIT_MASK
- | UVD_SUVD_CGC_GATE__SMP_MASK
- | UVD_SUVD_CGC_GATE__SCM_MASK
- | UVD_SUVD_CGC_GATE__SDB_MASK
- | UVD_SUVD_CGC_GATE__SRE_H264_MASK
- | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SIT_H264_MASK
- | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SCM_H264_MASK
- | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SDB_H264_MASK
- | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SCLR_MASK
- | UVD_SUVD_CGC_GATE__UVD_SC_MASK
- | UVD_SUVD_CGC_GATE__ENT_MASK
- | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
- | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
- | UVD_SUVD_CGC_GATE__SITE_MASK
- | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
- | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
- | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
- | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
- | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
- WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
-
- data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
- data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
- | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
- | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
- | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
- WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+ /* UVD disable CGC */
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
+ data &= ~(UVD_CGC_GATE__SYS_MASK
+ | UVD_CGC_GATE__UDEC_MASK
+ | UVD_CGC_GATE__MPEG2_MASK
+ | UVD_CGC_GATE__REGS_MASK
+ | UVD_CGC_GATE__RBC_MASK
+ | UVD_CGC_GATE__LMI_MC_MASK
+ | UVD_CGC_GATE__LMI_UMC_MASK
+ | UVD_CGC_GATE__IDCT_MASK
+ | UVD_CGC_GATE__MPRD_MASK
+ | UVD_CGC_GATE__MPC_MASK
+ | UVD_CGC_GATE__LBSI_MASK
+ | UVD_CGC_GATE__LRBBM_MASK
+ | UVD_CGC_GATE__UDEC_RE_MASK
+ | UVD_CGC_GATE__UDEC_CM_MASK
+ | UVD_CGC_GATE__UDEC_IT_MASK
+ | UVD_CGC_GATE__UDEC_DB_MASK
+ | UVD_CGC_GATE__UDEC_MP_MASK
+ | UVD_CGC_GATE__WCB_MASK
+ | UVD_CGC_GATE__VCPU_MASK
+ | UVD_CGC_GATE__MMSCH_MASK);
+
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
+
+ SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK
+ | UVD_CGC_CTRL__MMSCH_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ /* turn on */
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
+ data |= (UVD_SUVD_CGC_GATE__SRE_MASK
+ | UVD_SUVD_CGC_GATE__SIT_MASK
+ | UVD_SUVD_CGC_GATE__SMP_MASK
+ | UVD_SUVD_CGC_GATE__SCM_MASK
+ | UVD_SUVD_CGC_GATE__SDB_MASK
+ | UVD_SUVD_CGC_GATE__SRE_H264_MASK
+ | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_H264_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCM_H264_MASK
+ | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_H264_MASK
+ | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
+ | UVD_SUVD_CGC_GATE__SCLR_MASK
+ | UVD_SUVD_CGC_GATE__UVD_SC_MASK
+ | UVD_SUVD_CGC_GATE__ENT_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
+ | UVD_SUVD_CGC_GATE__SITE_MASK
+ | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
+ | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
+ | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
+ | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
+ data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
}
static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
@@ -777,59 +774,56 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
*
* Enable clock gating for VCN block
*/
-static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
+static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
{
uint32_t data = 0;
- int i;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* enable UVD CGC */
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
- data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
- else
- data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
- data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
- data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
- | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
- | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
- | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
- | UVD_CGC_CTRL__SYS_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MODE_MASK
- | UVD_CGC_CTRL__MPEG2_MODE_MASK
- | UVD_CGC_CTRL__REGS_MODE_MASK
- | UVD_CGC_CTRL__RBC_MODE_MASK
- | UVD_CGC_CTRL__LMI_MC_MODE_MASK
- | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
- | UVD_CGC_CTRL__IDCT_MODE_MASK
- | UVD_CGC_CTRL__MPRD_MODE_MASK
- | UVD_CGC_CTRL__MPC_MODE_MASK
- | UVD_CGC_CTRL__LBSI_MODE_MASK
- | UVD_CGC_CTRL__LRBBM_MODE_MASK
- | UVD_CGC_CTRL__WCB_MODE_MASK
- | UVD_CGC_CTRL__VCPU_MODE_MASK);
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
- data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
- | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
- | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
- | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
- | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
- WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+ /* enable UVD CGC */
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+ data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ else
+ data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+ data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+ data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
+ data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
+ | UVD_CGC_CTRL__SYS_MODE_MASK
+ | UVD_CGC_CTRL__UDEC_MODE_MASK
+ | UVD_CGC_CTRL__MPEG2_MODE_MASK
+ | UVD_CGC_CTRL__REGS_MODE_MASK
+ | UVD_CGC_CTRL__RBC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_MC_MODE_MASK
+ | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
+ | UVD_CGC_CTRL__IDCT_MODE_MASK
+ | UVD_CGC_CTRL__MPRD_MODE_MASK
+ | UVD_CGC_CTRL__MPC_MODE_MASK
+ | UVD_CGC_CTRL__LBSI_MODE_MASK
+ | UVD_CGC_CTRL__LRBBM_MODE_MASK
+ | UVD_CGC_CTRL__WCB_MODE_MASK
+ | UVD_CGC_CTRL__VCPU_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
+
+ data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
+ data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
+ | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
+ WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
}
static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
@@ -1032,7 +1026,7 @@ static int vcn_v2_5_start(struct amdgpu_device *adev, unsigned int inst)
return 0;
/*SW clock gating */
- vcn_v2_5_disable_clock_gating(adev);
+ vcn_v2_5_disable_clock_gating(adev, inst);
if (adev->vcn.harvest_config & (1 << inst))
return 0;
@@ -1471,7 +1465,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, unsigned int inst)
/* clear status */
WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
- vcn_v2_5_enable_clock_gating(adev);
+ vcn_v2_5_enable_clock_gating(adev, inst);
/* enable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS),
@@ -1795,6 +1789,7 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE);
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev))
return 0;
@@ -1802,9 +1797,9 @@ static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
if (enable) {
if (!vcn_v2_5_is_idle(ip_block))
return -EBUSY;
- vcn_v2_5_enable_clock_gating(adev);
+ vcn_v2_5_enable_clock_gating(adev, inst);
} else {
- vcn_v2_5_disable_clock_gating(adev);
+ vcn_v2_5_disable_clock_gating(adev, inst);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 5b11062b873d..e89600e6f86c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2123,19 +2123,17 @@ static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
- int i;
+ int inst = ip_block->instance;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (enable) {
- if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
- return -EBUSY;
- vcn_v3_0_enable_clock_gating(adev, i);
- } else {
- vcn_v3_0_disable_clock_gating(adev, i);
- }
+ if (enable) {
+ if (RREG32_SOC15(VCN, inst, mmUVD_STATUS) != UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v3_0_enable_clock_gating(adev, inst);
+ } else {
+ vcn_v3_0_disable_clock_gating(adev, inst);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 69fff5df1c68..e1b2ada8d69a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1994,19 +1994,17 @@ static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
- int i;
+ int inst = ip_block->instance;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (enable) {
- if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
- return -EBUSY;
- vcn_v4_0_enable_clock_gating(adev, i);
- } else {
- vcn_v4_0_disable_clock_gating(adev, i);
- }
+ if (enable) {
+ if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v4_0_enable_clock_gating(adev, inst);
+ } else {
+ vcn_v4_0_disable_clock_gating(adev, inst);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index cb30d5e5bc70..d1db91d8de79 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1588,18 +1588,17 @@ static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = state == AMD_CG_STATE_GATE;
- int i;
+ int inst = ip_block->instance;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (enable) {
- if (RREG32_SOC15(VCN, GET_INST(VCN, i),
- regUVD_STATUS) != UVD_STATUS__IDLE)
- return -EBUSY;
- vcn_v4_0_3_enable_clock_gating(adev, i);
- } else {
- vcn_v4_0_3_disable_clock_gating(adev, i);
- }
+ if (enable) {
+ if (RREG32_SOC15(VCN, GET_INST(VCN, inst),
+ regUVD_STATUS) != UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v4_0_3_enable_clock_gating(adev, inst);
+ } else {
+ vcn_v4_0_3_disable_clock_gating(adev, inst);
}
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 68397bea5a18..0f178dcf23fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1491,19 +1491,17 @@ static int vcn_v4_0_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- int i;
+ int inst = ip_block->instance;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (enable) {
- if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
- return -EBUSY;
- vcn_v4_0_5_enable_clock_gating(adev, i);
- } else {
- vcn_v4_0_5_disable_clock_gating(adev, i);
- }
+ if (enable) {
+ if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v4_0_5_enable_clock_gating(adev, inst);
+ } else {
+ vcn_v4_0_5_disable_clock_gating(adev, inst);
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index fd78472b906a..c651de11e095 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1218,19 +1218,17 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
{
struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- int i;
+ int inst = ip_block->instance;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (enable) {
- if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
- return -EBUSY;
- vcn_v5_0_0_enable_clock_gating(adev, i);
- } else {
- vcn_v5_0_0_disable_clock_gating(adev, i);
- }
+ if (enable) {
+ if (RREG32_SOC15(VCN, inst, regUVD_STATUS) != UVD_STATUS__IDLE)
+ return -EBUSY;
+ vcn_v5_0_0_enable_clock_gating(adev, inst);
+ } else {
+ vcn_v5_0_0_disable_clock_gating(adev, inst);
}
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH 00/32] Separating vcn power management by instance
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
` (31 preceding siblings ...)
2024-10-17 13:20 ` [PATCH 32/32] drm/amdgpu: set_powergating " boyuan.zhang
@ 2024-10-22 6:25 ` Christian König
2024-10-25 2:53 ` Boyuan Zhang
32 siblings, 1 reply; 45+ messages in thread
From: Christian König @ 2024-10-22 6:25 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, alexander.deucher, Khatri, Sunil
Patches #1-#5, #7, #8, #32 are Acked-by: Christian König
<christian.koenig@amd.com>
Patches #9 - #19, #27 are Reviewed-by: Christian König
<christian.koenig@amd.com>
Patch #6 the drm/amdgpu prefix is missing from the subject line, apart
from that the patch is Reviewed-by: Christian König
<christian.koenig@amd.com>
For patches #20-#26 I'm not sure if those won't break the driver in
between. Alex what do you think?
Patches #28 and #29 look good to me as well, but I leave the review to
Sunil he wrote that code and should know it best.
Patch #30:
+ int ret = 0;
...
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
That will get you a warning for an unneeded local variable
initialization from the automated checkers.
The init was only necessary because we previously had the loop over all
instances here.
Patch #31:
int inst = ip_block->instance;
int ret = 1;
if (adev->vcn.harvest_config & (1 << inst))
return ret;
ret &= (RREG32_SOC15(VCN, inst, mmUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
That code looks really strange now, maybe drop the local variable ret.
Regards,
Christian
Am 17.10.24 um 15:20 schrieb boyuan.zhang@amd.com:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Previously, all vcn instance will be powered on/off at the same time
> even only one of the instance requests power status change. This patch set
> enables vcn to ONLY power on/off the instance that requires power status
> change. Other vcn instances will remain the original power status.
>
> v4:
> code polishing and minor fixes.
>
> v3:
> move all of the per instance variables from struct amdgpu_vcn to
> struct amdgpu_vcn_inst. (patch 10 - 11)
>
> update amdgpu_device_ip_set_powergating_state() to take the instance as a
> new parameter, remove the duplicated function in v2. (patch 19)
>
> update all amdgpu_vcn_* helpers to handle vcn instance. All functions
> are now only handle the given vcn instance. (patch 20 - 26)
>
> update all vcn ip callback functions to handle vcn instance. All functions
> are now only handle the given vcn instance. (patch 27 - 32)
>
>
> v2:
> complete re-work for all PM changes as suggested-by Christian König and
> Alex Deucher. Adding instance to all existing functions, instead of create
> new functions. Remove all duplicated PM functions in previous patch set.
> Use a new logic to track instance for ip_block with same type as
> suggested by Alex. Also, fix wrong ip block index and remove redundant logic
> suggested by Christian. Finally rebase all patches based on Sunil's ip block
> changes.
>
> Patch 1-6 are SMU changes to only power ON/OFF given VCN instance.
>
> Patch 7-8 pass ip_block instead of adev pointer for set_powergating_state,
> set_clockgating_state, and is_idle
>
> Patch 9 is to track VCN instance in VCN ip_block.
>
> Patch 10 move all of the per instance variables from struct amdgpu_vcn to
> struct amdgpu_vcn_inst.
>
> Patch 11 VCN change to separate gating status for each VCN instance.
>
> Patch 12-17 are to handle ip callback functions separately for each
> VCN instance, so that only the given instance will be powered on/off.
>
> Patch 18 is VCN change to handle idle work separately for each VCN instance.
>
> Patch 19 is to set powergating state by VCN instance in amdgpu_vcn.
>
> Patch 20-26 update all amdgpu_vcn_* helpers to handle vcn instance. All functions
> are now only handle the given vcn instance.
>
> Patch 27-32 update all vcn ip callback functions to handle vcn instance. All functions
> are now only handle the given vcn instance.
>
> Boyuan Zhang (32):
> drm/amd/pm: add inst to dpm_set_vcn_enable
> drm/amd/pm: power up or down vcn by instance
> drm/amd/pm: add inst to smu_dpm_set_vcn_enable
> drm/amd/pm: add inst to set_powergating_by_smu
> drm/amd/pm: add inst to dpm_set_powergating_by_smu
> add inst to amdgpu_dpm_enable_vcn
> drm/amdgpu: pass ip_block in set_powergating_state
> drm/amdgpu: pass ip_block in set_clockgating_state
> drm/amdgpu: track instances of the same IP block
> drm/amdgpu: move per inst variables to amdgpu_vcn_inst
> drm/amdgpu/vcn: separate gating state by instance
> drm/amdgpu: power vcn 2_5 by instance
> drm/amdgpu: power vcn 3_0 by instance
> drm/amdgpu: power vcn 4_0 by instance
> drm/amdgpu: power vcn 4_0_3 by instance
> drm/amdgpu: power vcn 4_0_5 by instance
> drm/amdgpu: power vcn 5_0_0 by instance
> drm/amdgpu/vcn: separate idle work by instance
> drm/amdgpu: set powergating state by vcn instance
> drm/amdgpu: early_init for each vcn instance
> drm/amdgpu: sw_init for each vcn instance
> drm/amdgpu: sw_fini for each vcn instance
> drm/amdgpu: hw_init for each vcn instance
> drm/amdgpu: suspend for each vcn instance
> drm/amdgpu: resume for each vcn instance
> drm/amdgpu: setup_ucode for each vcn instance
> drm/amdgpu: set funcs for each vcn instance
> drm/amdgpu: print_ip_state for each vcn instance
> drm/amdgpu: dump_ip_state for each vcn instance
> drm/amdgpu: wait_for_idle for each vcn instance
> drm/amdgpu: is_idle for each vcn instance
> drm/amdgpu: set_powergating for each vcn instance
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 22 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 41 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 24 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 338 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 24 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/cik.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 18 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/soc21.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/soc24.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 10 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 14 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 23 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 25 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 16 +-
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 20 +-
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 12 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 140 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 124 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 1154 ++++++++---------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 909 +++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 801 ++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 727 +++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 782 ++++++-----
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 690 +++++-----
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/vi.c | 8 +-
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
> drivers/gpu/drm/amd/include/amd_shared.h | 6 +-
> .../gpu/drm/amd/include/kgd_pp_interface.h | 4 +-
> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 55 +-
> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 18 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 6 +-
> .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 10 +-
> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 6 +-
> .../powerplay/hwmgr/smu7_clockpowergating.c | 12 +-
> .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 12 +-
> .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 6 +-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 65 +-
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 +-
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +-
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 3 +-
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +-
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 +-
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 +-
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 19 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 4 +-
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 4 +-
> .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 38 +-
> 112 files changed, 3442 insertions(+), 3433 deletions(-)
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH 00/32] Separating vcn power management by instance
2024-10-22 6:25 ` [PATCH 00/32] Separating vcn power management by instance Christian König
@ 2024-10-25 2:53 ` Boyuan Zhang
0 siblings, 0 replies; 45+ messages in thread
From: Boyuan Zhang @ 2024-10-25 2:53 UTC (permalink / raw)
To: Christian König, amd-gfx, leo.liu, alexander.deucher,
Khatri, Sunil
On 2024-10-22 02:25, Christian König wrote:
> Patches #1-#5, #7, #8, #32 are Acked-by: Christian König
> <christian.koenig@amd.com>
Added Acked-by, and ready to be submitted.
>
> Patches #9 - #19, #27 are Reviewed-by: Christian König
> <christian.koenig@amd.com>
Added Reviewed-by, and ready to be submitted.
>
> Patch #6 the drm/amdgpu prefix is missing from the subject line, apart
> from that the patch is Reviewed-by: Christian König
> <christian.koenig@amd.com>
Fixed in new patch-set just submitted (patch 06/29), and added Reviewed-by.
>
> For patches #20-#26 I'm not sure if those won't break the driver in
> between. Alex what do you think?
Need Alex's input.
>
> Patches #28 and #29 look good to me as well, but I leave the review to
> Sunil he wrote that code and should know it best.
Patches #28 and #29 has been dropped in the new patch set based on
discussion with Sunil, will be submitted later on once his work is done.
>
> Patch #30:
>
> + int ret = 0;
>
> ...
> + ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
>
>
> That will get you a warning for an unneeded local variable
> initialization from the automated checkers.
>
> The init was only necessary because we previously had the loop over
> all instances here.
Fixed in new patch-set just submitted (patch 28/29)
>
> Patch #31:
>
> int inst = ip_block->instance;
> int ret = 1;
>
> if (adev->vcn.harvest_config & (1 << inst))
> return ret;
>
> ret &= (RREG32_SOC15(VCN, inst, mmUVD_STATUS) == UVD_STATUS__IDLE);
>
> return ret;
>
> That code looks really strange now, maybe drop the local variable ret.
Patch #31 has been dropped in the new patch set based on discussion with
Sunil, will be submitted later on once his work is done.
>
> Regards,
> Christian
>
> Am 17.10.24 um 15:20 schrieb boyuan.zhang@amd.com:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Previously, all vcn instance will be powered on/off at the same time
>> even only one of the instance requests power status change. This
>> patch set
>> enables vcn to ONLY power on/off the instance that requires power status
>> change. Other vcn instances will remain the original power status.
>>
>> v4:
>> code polishing and minor fixes.
>>
>> v3:
>> move all of the per instance variables from struct amdgpu_vcn to
>> struct amdgpu_vcn_inst. (patch 10 - 11)
>>
>> update amdgpu_device_ip_set_powergating_state() to take the instance
>> as a
>> new parameter, remove the duplicated function in v2. (patch 19)
>>
>> update all amdgpu_vcn_* helpers to handle vcn instance. All functions
>> are now only handle the given vcn instance. (patch 20 - 26)
>>
>> update all vcn ip callback functions to handle vcn instance. All
>> functions
>> are now only handle the given vcn instance. (patch 27 - 32)
>>
>>
>> v2:
>> complete re-work for all PM changes as suggested-by Christian König and
>> Alex Deucher. Adding instance to all existing functions, instead of
>> create
>> new functions. Remove all duplicated PM functions in previous patch set.
>> Use a new logic to track instance for ip_block with same type as
>> suggested by Alex. Also, fix wrong ip block index and remove
>> redundant logic
>> suggested by Christian. Finally rebase all patches based on Sunil's
>> ip block
>> changes.
>>
>> Patch 1-6 are SMU changes to only power ON/OFF given VCN instance.
>>
>> Patch 7-8 pass ip_block instead of adev pointer for
>> set_powergating_state,
>> set_clockgating_state, and is_idle
>>
>> Patch 9 is to track VCN instance in VCN ip_block.
>>
>> Patch 10 move all of the per instance variables from struct
>> amdgpu_vcn to
>> struct amdgpu_vcn_inst.
>>
>> Patch 11 VCN change to separate gating status for each VCN instance.
>>
>> Patch 12-17 are to handle ip callback functions separately for each
>> VCN instance, so that only the given instance will be powered on/off.
>>
>> Patch 18 is VCN change to handle idle work separately for each VCN
>> instance.
>>
>> Patch 19 is to set powergating state by VCN instance in amdgpu_vcn.
>>
>> Patch 20-26 update all amdgpu_vcn_* helpers to handle vcn instance.
>> All functions
>> are now only handle the given vcn instance.
>>
>> Patch 27-32 update all vcn ip callback functions to handle vcn
>> instance. All functions
>> are now only handle the given vcn instance.
>>
>> Boyuan Zhang (32):
>> drm/amd/pm: add inst to dpm_set_vcn_enable
>> drm/amd/pm: power up or down vcn by instance
>> drm/amd/pm: add inst to smu_dpm_set_vcn_enable
>> drm/amd/pm: add inst to set_powergating_by_smu
>> drm/amd/pm: add inst to dpm_set_powergating_by_smu
>> add inst to amdgpu_dpm_enable_vcn
>> drm/amdgpu: pass ip_block in set_powergating_state
>> drm/amdgpu: pass ip_block in set_clockgating_state
>> drm/amdgpu: track instances of the same IP block
>> drm/amdgpu: move per inst variables to amdgpu_vcn_inst
>> drm/amdgpu/vcn: separate gating state by instance
>> drm/amdgpu: power vcn 2_5 by instance
>> drm/amdgpu: power vcn 3_0 by instance
>> drm/amdgpu: power vcn 4_0 by instance
>> drm/amdgpu: power vcn 4_0_3 by instance
>> drm/amdgpu: power vcn 4_0_5 by instance
>> drm/amdgpu: power vcn 5_0_0 by instance
>> drm/amdgpu/vcn: separate idle work by instance
>> drm/amdgpu: set powergating state by vcn instance
>> drm/amdgpu: early_init for each vcn instance
>> drm/amdgpu: sw_init for each vcn instance
>> drm/amdgpu: sw_fini for each vcn instance
>> drm/amdgpu: hw_init for each vcn instance
>> drm/amdgpu: suspend for each vcn instance
>> drm/amdgpu: resume for each vcn instance
>> drm/amdgpu: setup_ucode for each vcn instance
>> drm/amdgpu: set funcs for each vcn instance
>> drm/amdgpu: print_ip_state for each vcn instance
>> drm/amdgpu: dump_ip_state for each vcn instance
>> drm/amdgpu: wait_for_idle for each vcn instance
>> drm/amdgpu: is_idle for each vcn instance
>> drm/amdgpu: set_powergating for each vcn instance
>>
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 22 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 41 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 24 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 338 +++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 24 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/cik.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 16 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 12 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 12 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 12 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 16 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 18 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/nv.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 16 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/si.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/soc24.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 10 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 14 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 23 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 25 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 16 +-
>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 20 +-
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 12 +-
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 140 +-
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 124 +-
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 1154 ++++++++---------
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 909 +++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 801 ++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 727 +++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 782 ++++++-----
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 690 +++++-----
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/vi.c | 8 +-
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
>> drivers/gpu/drm/amd/include/amd_shared.h | 6 +-
>> .../gpu/drm/amd/include/kgd_pp_interface.h | 4 +-
>> drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 55 +-
>> drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 3 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 18 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 6 +-
>> .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 10 +-
>> .../drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 6 +-
>> .../powerplay/hwmgr/smu7_clockpowergating.c | 12 +-
>> .../drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 12 +-
>> .../drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c | 6 +-
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 65 +-
>> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 +-
>> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +-
>> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 3 +-
>> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +-
>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 +-
>> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 +-
>> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 +-
>> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +-
>> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 19 +-
>> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 4 +-
>> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 4 +-
>> .../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 38 +-
>> 112 files changed, 3442 insertions(+), 3433 deletions(-)
>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread