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* Various fixes for gfx6
@ 2016-09-01 17:44 Tom St Denis
       [not found] ` <20160901174447.13037-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 11+ messages in thread
From: Tom St Denis @ 2016-09-01 17:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Patch #1 adds missing mutex locking around se/sh/instance writes.

Patches #2/3 perform various cleanups.

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 1/3] drm/amd/amdgpu: Add GRBM lock to various SI functions
       [not found] ` <20160901174447.13037-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-01 17:44   ` Tom St Denis
       [not found]     ` <20160901174447.13037-2-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2016-09-01 17:44   ` [PATCH 2/3] drm/amd/amdgpu: Simplify mask creation in gfx6 Tom St Denis
  2016-09-01 17:44   ` [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6 Tom St Denis
  2 siblings, 1 reply; 11+ messages in thread
From: Tom St Denis @ 2016-09-01 17:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Add missing lock around SE/SH/INSTANCE selections.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 17a560cd6420..099539f0fa53 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -946,6 +946,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 	u32 disabled_rbs = 0;
 	u32 enabled_rbs = 0;
 
+	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < se_num; i++) {
 		for (j = 0; j < sh_per_se; j++) {
 			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -954,6 +955,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 		}
 	}
 	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+	mutex_unlock(&adev->grbm_idx_mutex);
 
 	mask = 1;
 	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
@@ -965,6 +967,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 	adev->gfx.config.backend_enable_mask = enabled_rbs;
 	adev->gfx.config.num_rbs = hweight32(enabled_rbs);
 
+	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < se_num; i++) {
 		gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
 		data = 0;
@@ -986,6 +989,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
 		WREG32(PA_SC_RASTER_CONFIG, data);
 	}
 	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 /*
 static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
@@ -1017,6 +1021,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
 	u32 data, mask;
 	u32 active_cu = 0;
 
+	mutex_lock(&adev->grbm_idx_mutex);
 	for (i = 0; i < se_num; i++) {
 		for (j = 0; j < sh_per_se; j++) {
 			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -1035,6 +1040,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
 		}
 	}
 	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
 static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
@@ -2497,10 +2503,12 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
 	u32 mask = 0, tmp, tmp1;
 	int i;
 
+	mutex_lock(&adev->grbm_idx_mutex);
 	gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
 	tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
 	tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
 	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
+	mutex_unlock(&adev->grbm_idx_mutex);
 
 	tmp &= 0xffff0000;
 
-- 
2.9.3

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^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/amd/amdgpu: Simplify mask creation in gfx6
       [not found] ` <20160901174447.13037-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2016-09-01 17:44   ` [PATCH 1/3] drm/amd/amdgpu: Add GRBM lock to various SI functions Tom St Denis
@ 2016-09-01 17:44   ` Tom St Denis
  2016-09-01 17:44   ` [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6 Tom St Denis
  2 siblings, 0 replies; 11+ messages in thread
From: Tom St Denis @ 2016-09-01 17:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 099539f0fa53..5f508c96496f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -911,13 +911,7 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 
 static u32 gfx_v6_0_create_bitmask(u32 bit_width)
 {
-	u32 i, mask = 0;
-
-	for (i = 0; i < bit_width; i++) {
-		mask <<= 1;
-		mask |= 1;
-	}
-	return mask;
+	return (u32)(((u64)1 << bit_width) - 1);
 }
 
 static u32 gfx_v6_0_get_rb_disabled(struct amdgpu_device *adev,
-- 
2.9.3

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found] ` <20160901174447.13037-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2016-09-01 17:44   ` [PATCH 1/3] drm/amd/amdgpu: Add GRBM lock to various SI functions Tom St Denis
  2016-09-01 17:44   ` [PATCH 2/3] drm/amd/amdgpu: Simplify mask creation in gfx6 Tom St Denis
@ 2016-09-01 17:44   ` Tom St Denis
       [not found]     ` <20160901174447.13037-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2 siblings, 1 reply; 11+ messages in thread
From: Tom St Denis @ 2016-09-01 17:44 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Various whitespace and logical simplifications for gfx6.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
 1 file changed, 5 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 5f508c96496f..63ca77937714 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
 				 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
 
 	WREG32(VGT_NUM_INSTANCES, 1);
-
 	WREG32(CP_PERFMON_CNTL, 0);
-
 	WREG32(SQ_CONFIG, 0);
-
 	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 					  FORCE_EOV_MAX_REZ_CNT(255)));
 
@@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
 	WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 
 	udelay(50);
-
 }
 
 
@@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
 
 static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
 {
-	u32 rptr;
-
-	rptr = ring->adev->wb.wb[ring->rptr_offs];
-
-	return rptr;
+	return ring->adev->wb.wb[ring->rptr_offs];
 }
 
 static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-	u32 wptr;
 
-	wptr = RREG32(CP_RB0_WPTR);
-
-	return wptr;
+	return RREG32(CP_RB0_WPTR);
 }
 
 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
@@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
 
 static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 {
-	u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
-
-	return rptr;
+	return ring->adev->wb.wb[ring->rptr_offs];
 }
 
 static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
@@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
 	ring->wptr = 0;
 	WREG32(CP_RB1_WPTR, ring->wptr);
 
-
 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
 	WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
 	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
 
 	mdelay(1);
 	WREG32(CP_RB1_CNTL, tmp);
-
 	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
 
 	ring = &adev->gfx.compute_ring[1];
@@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
 
 	mdelay(1);
 	WREG32(CP_RB2_CNTL, tmp);
-
 	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
 
 	adev->gfx.compute_ring[0].ready = true;
@@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
 
 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
 {
-	int r;
-
-	r = gfx_v6_0_cp_gfx_load_microcode(adev);
-
-	return r;
-
+	return gfx_v6_0_cp_gfx_load_microcode(adev);
 }
 
 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
@@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
 	WREG32(RLC_CNTL, 0);
 
 	gfx_v6_0_enable_gui_idle_interrupt(adev, false);
-
 	gfx_v6_0_wait_for_rlc_serdes(adev);
 }
 
@@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
 		return -EINVAL;
 
 	gfx_v6_0_rlc_stop(adev);
-
 	gfx_v6_0_rlc_reset(adev);
-
 	gfx_v6_0_init_pg(adev);
-
 	gfx_v6_0_init_cg(adev);
 
 	WREG32(RLC_RL_BASE, 0);
@@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
 	WREG32(RLC_UCODE_ADDR, 0);
 
 	gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
-
 	gfx_v6_0_rlc_start(adev);
 
 	return 0;
@@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
 		WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
 
 		gfx_v6_0_wait_for_rlc_serdes(adev);
-
 		gfx_v6_0_update_rlc(adev, tmp);
 
 		WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
@@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
 static int gfx_v6_0_wait_for_idle(void *handle)
 {
 	unsigned i;
-	u32 tmp;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
-		tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
-
-		if (!tmp)
+		if (gfx_v6_0_is_idle(handle))
 			return 0;
 		udelay(1);
 	}
-- 
2.9.3

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/amd/amdgpu: Add GRBM lock to various SI functions
       [not found]     ` <20160901174447.13037-2-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-01 17:57       ` Christian König
  0 siblings, 0 replies; 11+ messages in thread
From: Christian König @ 2016-09-01 17:57 UTC (permalink / raw)
  To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Am 01.09.2016 um 19:44 schrieb Tom St Denis:
> Add missing lock around SE/SH/INSTANCE selections.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

This one and #2 are Reviewed-by: Christian König <christian.koenig@amd.com>.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 17a560cd6420..099539f0fa53 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -946,6 +946,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
>   	u32 disabled_rbs = 0;
>   	u32 enabled_rbs = 0;
>   
> +	mutex_lock(&adev->grbm_idx_mutex);
>   	for (i = 0; i < se_num; i++) {
>   		for (j = 0; j < sh_per_se; j++) {
>   			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
> @@ -954,6 +955,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
>   		}
>   	}
>   	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
> +	mutex_unlock(&adev->grbm_idx_mutex);
>   
>   	mask = 1;
>   	for (i = 0; i < max_rb_num_per_se * se_num; i++) {
> @@ -965,6 +967,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
>   	adev->gfx.config.backend_enable_mask = enabled_rbs;
>   	adev->gfx.config.num_rbs = hweight32(enabled_rbs);
>   
> +	mutex_lock(&adev->grbm_idx_mutex);
>   	for (i = 0; i < se_num; i++) {
>   		gfx_v6_0_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
>   		data = 0;
> @@ -986,6 +989,7 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev,
>   		WREG32(PA_SC_RASTER_CONFIG, data);
>   	}
>   	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
> +	mutex_unlock(&adev->grbm_idx_mutex);
>   }
>   /*
>   static void gmc_v6_0_init_compute_vmid(struct amdgpu_device *adev)
> @@ -1017,6 +1021,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
>   	u32 data, mask;
>   	u32 active_cu = 0;
>   
> +	mutex_lock(&adev->grbm_idx_mutex);
>   	for (i = 0; i < se_num; i++) {
>   		for (j = 0; j < sh_per_se; j++) {
>   			gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
> @@ -1035,6 +1040,7 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev,
>   		}
>   	}
>   	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
> +	mutex_unlock(&adev->grbm_idx_mutex);
>   }
>   
>   static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
> @@ -2497,10 +2503,12 @@ static u32 gfx_v6_0_get_cu_active_bitmap(struct amdgpu_device *adev,
>   	u32 mask = 0, tmp, tmp1;
>   	int i;
>   
> +	mutex_lock(&adev->grbm_idx_mutex);
>   	gfx_v6_0_select_se_sh(adev, se, sh, 0xffffffff);
>   	tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
>   	tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
>   	gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
> +	mutex_unlock(&adev->grbm_idx_mutex);
>   
>   	tmp &= 0xffff0000;
>   


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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]     ` <20160901174447.13037-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
@ 2016-09-01 17:59       ` Christian König
       [not found]         ` <7364a051-e423-57db-5a7f-d66d12cdeec7-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
  2016-09-02  3:22       ` Edward O'Callaghan
  1 sibling, 1 reply; 11+ messages in thread
From: Christian König @ 2016-09-01 17:59 UTC (permalink / raw)
  To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis

Am 01.09.2016 um 19:44 schrieb Tom St Denis:
> Various whitespace and logical simplifications for gfx6.
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
>   1 file changed, 5 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5f508c96496f..63ca77937714 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>   				 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
>   
>   	WREG32(VGT_NUM_INSTANCES, 1);
> -
>   	WREG32(CP_PERFMON_CNTL, 0);
> -
>   	WREG32(SQ_CONFIG, 0);
> -
>   	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
>   					  FORCE_EOV_MAX_REZ_CNT(255)));
>   
> @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>   	WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
>   
>   	udelay(50);
> -
>   }
>   
>   
> @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>   
>   static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>   {
> -	u32 rptr;
> -
> -	rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -	return rptr;
> +	return ring->adev->wb.wb[ring->rptr_offs];
>   }
>   
>   static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> -	u32 wptr;
>   
> -	wptr = RREG32(CP_RB0_WPTR);
> -
> -	return wptr;
> +	return RREG32(CP_RB0_WPTR);
>   }
>   
>   static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>   
>   static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
>   {
> -	u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -	return rptr;
> +	return ring->adev->wb.wb[ring->rptr_offs];
>   }

Am I blind or are the gfx_v6_0_ring_get_rptr_compute() and 
gfx_v6_0_ring_get_rptr_gfx() functions identical?

If that's true might be a good idea to just use one function.

Either way patch is Reviewed-by: Christian König <christian.koenig@amd.com>

Christian.

>   
>   static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>   	ring->wptr = 0;
>   	WREG32(CP_RB1_WPTR, ring->wptr);
>   
> -
>   	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
>   	WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
>   	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
>   
>   	mdelay(1);
>   	WREG32(CP_RB1_CNTL, tmp);
> -
>   	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
>   
>   	ring = &adev->gfx.compute_ring[1];
> @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>   
>   	mdelay(1);
>   	WREG32(CP_RB2_CNTL, tmp);
> -
>   	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
>   
>   	adev->gfx.compute_ring[0].ready = true;
> @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
>   
>   static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
>   {
> -	int r;
> -
> -	r = gfx_v6_0_cp_gfx_load_microcode(adev);
> -
> -	return r;
> -
> +	return gfx_v6_0_cp_gfx_load_microcode(adev);
>   }
>   
>   static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
>   	WREG32(RLC_CNTL, 0);
>   
>   	gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> -
>   	gfx_v6_0_wait_for_rlc_serdes(adev);
>   }
>   
> @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>   		return -EINVAL;
>   
>   	gfx_v6_0_rlc_stop(adev);
> -
>   	gfx_v6_0_rlc_reset(adev);
> -
>   	gfx_v6_0_init_pg(adev);
> -
>   	gfx_v6_0_init_cg(adev);
>   
>   	WREG32(RLC_RL_BASE, 0);
> @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>   	WREG32(RLC_UCODE_ADDR, 0);
>   
>   	gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> -
>   	gfx_v6_0_rlc_start(adev);
>   
>   	return 0;
> @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
>   		WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
>   
>   		gfx_v6_0_wait_for_rlc_serdes(adev);
> -
>   		gfx_v6_0_update_rlc(adev, tmp);
>   
>   		WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
>   static int gfx_v6_0_wait_for_idle(void *handle)
>   {
>   	unsigned i;
> -	u32 tmp;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
>   	for (i = 0; i < adev->usec_timeout; i++) {
> -		tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> -
> -		if (!tmp)
> +		if (gfx_v6_0_is_idle(handle))
>   			return 0;
>   		udelay(1);
>   	}


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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]     ` <20160901174447.13037-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
  2016-09-01 17:59       ` Christian König
@ 2016-09-02  3:22       ` Edward O'Callaghan
       [not found]         ` <717365b4-0cdd-95a4-9e8c-4b04660844c6-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
  1 sibling, 1 reply; 11+ messages in thread
From: Edward O'Callaghan @ 2016-09-02  3:22 UTC (permalink / raw)
  To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Tom St Denis


[-- Attachment #1.1.1: Type: text/plain, Size: 4825 bytes --]



On 09/02/2016 03:44 AM, Tom St Denis wrote:
> Various whitespace and logical simplifications for gfx6.
> 
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
>  1 file changed, 5 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5f508c96496f..63ca77937714 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>  				 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
>  
>  	WREG32(VGT_NUM_INSTANCES, 1);
> -
>  	WREG32(CP_PERFMON_CNTL, 0);
> -
>  	WREG32(SQ_CONFIG, 0);
> -
>  	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
>  					  FORCE_EOV_MAX_REZ_CNT(255)));
>  
> @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>  	WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
>  
>  	udelay(50);
> -
>  }
>  
>  
> @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>  
>  static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>  {
> -	u32 rptr;
> -
> -	rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -	return rptr;
> +	return ring->adev->wb.wb[ring->rptr_offs];
>  }
>  
>  static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>  {
>  	struct amdgpu_device *adev = ring->adev;

Also adev seems to be unused here?

> -	u32 wptr;
>  
> -	wptr = RREG32(CP_RB0_WPTR);
> -
> -	return wptr;
> +	return RREG32(CP_RB0_WPTR);
>  }
>  
>  static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>  
>  static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
>  {
> -	u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -	return rptr;
> +	return ring->adev->wb.wb[ring->rptr_offs];
>  }
>  
>  static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>  	ring->wptr = 0;
>  	WREG32(CP_RB1_WPTR, ring->wptr);
>  
> -
>  	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
>  	WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
>  	WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
>  
>  	mdelay(1);
>  	WREG32(CP_RB1_CNTL, tmp);
> -
>  	WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
>  
>  	ring = &adev->gfx.compute_ring[1];
> @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>  
>  	mdelay(1);
>  	WREG32(CP_RB2_CNTL, tmp);
> -
>  	WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
>  
>  	adev->gfx.compute_ring[0].ready = true;
> @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
>  
>  static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
>  {
> -	int r;
> -
> -	r = gfx_v6_0_cp_gfx_load_microcode(adev);
> -
> -	return r;
> -
> +	return gfx_v6_0_cp_gfx_load_microcode(adev);
>  }
>  
>  static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
>  	WREG32(RLC_CNTL, 0);
>  
>  	gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> -
>  	gfx_v6_0_wait_for_rlc_serdes(adev);
>  }
>  
> @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>  		return -EINVAL;
>  
>  	gfx_v6_0_rlc_stop(adev);
> -
>  	gfx_v6_0_rlc_reset(adev);
> -
>  	gfx_v6_0_init_pg(adev);
> -
>  	gfx_v6_0_init_cg(adev);
>  
>  	WREG32(RLC_RL_BASE, 0);
> @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>  	WREG32(RLC_UCODE_ADDR, 0);
>  
>  	gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> -
>  	gfx_v6_0_rlc_start(adev);
>  
>  	return 0;
> @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
>  		WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
>  
>  		gfx_v6_0_wait_for_rlc_serdes(adev);
> -
>  		gfx_v6_0_update_rlc(adev, tmp);
>  
>  		WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
>  static int gfx_v6_0_wait_for_idle(void *handle)
>  {
>  	unsigned i;
> -	u32 tmp;
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>  
>  	for (i = 0; i < adev->usec_timeout; i++) {
> -		tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> -
> -		if (!tmp)
> +		if (gfx_v6_0_is_idle(handle))
>  			return 0;
>  		udelay(1);
>  	}
> 


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_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]         ` <7364a051-e423-57db-5a7f-d66d12cdeec7-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2016-09-02 11:54           ` StDenis, Tom
       [not found]             ` <CY4PR12MB1768BF04DBC2C421B0FC969FF7E50-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 11+ messages in thread
From: StDenis, Tom @ 2016-09-02 11:54 UTC (permalink / raw)
  To: Christian König,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org


[-- Attachment #1.1: Type: text/plain, Size: 6023 bytes --]

Nope your eyes are fine.  Note that the same pattern exists in gfx_v8_0.c as well.  I guess different ring struct pointers are passed so they're not talking to the same ring.


We could merge those to reduce the # of LOC.


Tom


________________________________
From: Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
Sent: Thursday, September 1, 2016 13:59
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6

Am 01.09.2016 um 19:44 schrieb Tom St Denis:
> Various whitespace and logical simplifications for gfx6.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
>   1 file changed, 5 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5f508c96496f..63ca77937714 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>                                 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
>
>        WREG32(VGT_NUM_INSTANCES, 1);
> -
>        WREG32(CP_PERFMON_CNTL, 0);
> -
>        WREG32(SQ_CONFIG, 0);
> -
>        WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
>                                          FORCE_EOV_MAX_REZ_CNT(255)));
>
> @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
>
>        udelay(50);
> -
>   }
>
>
> @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>
>   static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>   {
> -     u32 rptr;
> -
> -     rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>   }
>
>   static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>   {
>        struct amdgpu_device *adev = ring->adev;
> -     u32 wptr;
>
> -     wptr = RREG32(CP_RB0_WPTR);
> -
> -     return wptr;
> +     return RREG32(CP_RB0_WPTR);
>   }
>
>   static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>
>   static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
>   {
> -     u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>   }

Am I blind or are the gfx_v6_0_ring_get_rptr_compute() and
gfx_v6_0_ring_get_rptr_gfx() functions identical?

If that's true might be a good idea to just use one function.

Either way patch is Reviewed-by: Christian König <christian.koenig-urvtwAKJhsc@public.gmane.orgm>

Christian.

>
>   static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>        ring->wptr = 0;
>        WREG32(CP_RB1_WPTR, ring->wptr);
>
> -
>        rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
>        WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
>        WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
>
>        mdelay(1);
>        WREG32(CP_RB1_CNTL, tmp);
> -
>        WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
>
>        ring = &adev->gfx.compute_ring[1];
> @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>
>        mdelay(1);
>        WREG32(CP_RB2_CNTL, tmp);
> -
>        WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
>
>        adev->gfx.compute_ring[0].ready = true;
> @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
>
>   static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
>   {
> -     int r;
> -
> -     r = gfx_v6_0_cp_gfx_load_microcode(adev);
> -
> -     return r;
> -
> +     return gfx_v6_0_cp_gfx_load_microcode(adev);
>   }
>
>   static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
>        WREG32(RLC_CNTL, 0);
>
>        gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> -
>        gfx_v6_0_wait_for_rlc_serdes(adev);
>   }
>
> @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>                return -EINVAL;
>
>        gfx_v6_0_rlc_stop(adev);
> -
>        gfx_v6_0_rlc_reset(adev);
> -
>        gfx_v6_0_init_pg(adev);
> -
>        gfx_v6_0_init_cg(adev);
>
>        WREG32(RLC_RL_BASE, 0);
> @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>        WREG32(RLC_UCODE_ADDR, 0);
>
>        gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> -
>        gfx_v6_0_rlc_start(adev);
>
>        return 0;
> @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
>                WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
>
>                gfx_v6_0_wait_for_rlc_serdes(adev);
> -
>                gfx_v6_0_update_rlc(adev, tmp);
>
>                WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
>   static int gfx_v6_0_wait_for_idle(void *handle)
>   {
>        unsigned i;
> -     u32 tmp;
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
>        for (i = 0; i < adev->usec_timeout; i++) {
> -             tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> -
> -             if (!tmp)
> +             if (gfx_v6_0_is_idle(handle))
>                        return 0;
>                udelay(1);
>        }



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_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]             ` <CY4PR12MB1768BF04DBC2C421B0FC969FF7E50-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2016-09-02 12:06               ` Christian König
       [not found]                 ` <aa1ac326-ed57-21f5-df8f-5ceb4ae32ae8-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
  0 siblings, 1 reply; 11+ messages in thread
From: Christian König @ 2016-09-02 12:06 UTC (permalink / raw)
  To: StDenis, Tom,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org


[-- Attachment #1.1: Type: text/plain, Size: 6622 bytes --]


> We could merge those to reduce the # of LOC.
>
Yes, please do so if you have time.

BTW: Do you know any tool/hack/whatever to find unused structure 
members? E.g. members which are never accessed or only set but never read?

We seem to have quite a number of those in amdgpu, radeon as well as 
TTM. Would be nice to clean such stuff up.

Christian.

Am 02.09.2016 um 13:54 schrieb StDenis, Tom:
>
> Nope your eyes are fine.  Note that the same pattern exists in 
> gfx_v8_0.c as well.  I guess different ring struct pointers are passed 
> so they're not talking to the same ring.
>
>
> We could merge those to reduce the # of LOC.
>
>
> Tom
>
>
>
> ------------------------------------------------------------------------
> *From:* Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
> *Sent:* Thursday, September 1, 2016 13:59
> *To:* Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* StDenis, Tom
> *Subject:* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
> Am 01.09.2016 um 19:44 schrieb Tom St Denis:
> > Various whitespace and logical simplifications for gfx6.
> >
> > Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 
> +++++------------------------------
> >   1 file changed, 5 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > index 5f508c96496f..63ca77937714 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> > @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct 
> amdgpu_device *adev)
> > SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
> >
> >        WREG32(VGT_NUM_INSTANCES, 1);
> > -
> >        WREG32(CP_PERFMON_CNTL, 0);
> > -
> >        WREG32(SQ_CONFIG, 0);
> > -
> >        WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
> > FORCE_EOV_MAX_REZ_CNT(255)));
> >
> > @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct 
> amdgpu_device *adev)
> >        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
> >
> >        udelay(50);
> > -
> >   }
> >
> >
> > @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct 
> amdgpu_device *adev)
> >
> >   static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
> >   {
> > -     u32 rptr;
> > -
> > -     rptr = ring->adev->wb.wb[ring->rptr_offs];
> > -
> > -     return rptr;
> > +     return ring->adev->wb.wb[ring->rptr_offs];
> >   }
> >
> >   static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
> >   {
> >        struct amdgpu_device *adev = ring->adev;
> > -     u32 wptr;
> >
> > -     wptr = RREG32(CP_RB0_WPTR);
> > -
> > -     return wptr;
> > +     return RREG32(CP_RB0_WPTR);
> >   }
> >
> >   static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> > @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct 
> amdgpu_ring *ring)
> >
> >   static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
> >   {
> > -     u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> > -
> > -     return rptr;
> > +     return ring->adev->wb.wb[ring->rptr_offs];
> >   }
>
> Am I blind or are the gfx_v6_0_ring_get_rptr_compute() and
> gfx_v6_0_ring_get_rptr_gfx() functions identical?
>
> If that's true might be a good idea to just use one function.
>
> Either way patch is Reviewed-by: Christian König 
> <christian.koenig-5C7GfCeVMHo@public.gmane.org>
>
> Christian.
>
> >
> >   static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> > @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct 
> amdgpu_device *adev)
> >        ring->wptr = 0;
> >        WREG32(CP_RB1_WPTR, ring->wptr);
> >
> > -
> >        rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
> >        WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
> >        WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
> >
> >        mdelay(1);
> >        WREG32(CP_RB1_CNTL, tmp);
> > -
> >        WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
> >
> >        ring = &adev->gfx.compute_ring[1];
> > @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct 
> amdgpu_device *adev)
> >
> >        mdelay(1);
> >        WREG32(CP_RB2_CNTL, tmp);
> > -
> >        WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
> >
> >        adev->gfx.compute_ring[0].ready = true;
> > @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct 
> amdgpu_device *adev, bool enable)
> >
> >   static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
> >   {
> > -     int r;
> > -
> > -     r = gfx_v6_0_cp_gfx_load_microcode(adev);
> > -
> > -     return r;
> > -
> > +     return gfx_v6_0_cp_gfx_load_microcode(adev);
> >   }
> >
> >   static void gfx_v6_0_enable_gui_idle_interrupt(struct 
> amdgpu_device *adev,
> > @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct 
> amdgpu_device *adev)
> >        WREG32(RLC_CNTL, 0);
> >
> >        gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> > -
> >        gfx_v6_0_wait_for_rlc_serdes(adev);
> >   }
> >
> > @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct 
> amdgpu_device *adev)
> >                return -EINVAL;
> >
> >        gfx_v6_0_rlc_stop(adev);
> > -
> >        gfx_v6_0_rlc_reset(adev);
> > -
> >        gfx_v6_0_init_pg(adev);
> > -
> >        gfx_v6_0_init_cg(adev);
> >
> >        WREG32(RLC_RL_BASE, 0);
> > @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct 
> amdgpu_device *adev)
> >        WREG32(RLC_UCODE_ADDR, 0);
> >
> >        gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> > -
> >        gfx_v6_0_rlc_start(adev);
> >
> >        return 0;
> > @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct 
> amdgpu_device *adev, bool enable)
> >                WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
> >
> >                gfx_v6_0_wait_for_rlc_serdes(adev);
> > -
> >                gfx_v6_0_update_rlc(adev, tmp);
> >
> >                WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> > @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
> >   static int gfx_v6_0_wait_for_idle(void *handle)
> >   {
> >        unsigned i;
> > -     u32 tmp;
> >        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >
> >        for (i = 0; i < adev->usec_timeout; i++) {
> > -             tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> > -
> > -             if (!tmp)
> > +             if (gfx_v6_0_is_idle(handle))
> >                        return 0;
> >                udelay(1);
> >        }
>
>


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_______________________________________________
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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]         ` <717365b4-0cdd-95a4-9e8c-4b04660844c6-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
@ 2016-09-02 12:06           ` StDenis, Tom
  0 siblings, 0 replies; 11+ messages in thread
From: StDenis, Tom @ 2016-09-02 12:06 UTC (permalink / raw)
  To: Edward O'Callaghan,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org


[-- Attachment #1.1: Type: text/plain, Size: 5620 bytes --]

The "adev" variable must be in scope when using the RREG32/WREG32 (and derivatives) macros.


Tom


________________________________
From: Edward O'Callaghan <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
Sent: Thursday, September 1, 2016 23:22
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: StDenis, Tom
Subject: Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6



On 09/02/2016 03:44 AM, Tom St Denis wrote:
> Various whitespace and logical simplifications for gfx6.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
>  1 file changed, 5 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5f508c96496f..63ca77937714 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>                                 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
>
>        WREG32(VGT_NUM_INSTANCES, 1);
> -
>        WREG32(CP_PERFMON_CNTL, 0);
> -
>        WREG32(SQ_CONFIG, 0);
> -
>        WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
>                                          FORCE_EOV_MAX_REZ_CNT(255)));
>
> @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
>
>        udelay(50);
> -
>  }
>
>
> @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>
>  static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>  {
> -     u32 rptr;
> -
> -     rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>  }
>
>  static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>  {
>        struct amdgpu_device *adev = ring->adev;

Also adev seems to be unused here?

> -     u32 wptr;
>
> -     wptr = RREG32(CP_RB0_WPTR);
> -
> -     return wptr;
> +     return RREG32(CP_RB0_WPTR);
>  }
>
>  static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>
>  static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
>  {
> -     u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>  }
>
>  static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>        ring->wptr = 0;
>        WREG32(CP_RB1_WPTR, ring->wptr);
>
> -
>        rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
>        WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
>        WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
>
>        mdelay(1);
>        WREG32(CP_RB1_CNTL, tmp);
> -
>        WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
>
>        ring = &adev->gfx.compute_ring[1];
> @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>
>        mdelay(1);
>        WREG32(CP_RB2_CNTL, tmp);
> -
>        WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
>
>        adev->gfx.compute_ring[0].ready = true;
> @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
>
>  static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
>  {
> -     int r;
> -
> -     r = gfx_v6_0_cp_gfx_load_microcode(adev);
> -
> -     return r;
> -
> +     return gfx_v6_0_cp_gfx_load_microcode(adev);
>  }
>
>  static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
>        WREG32(RLC_CNTL, 0);
>
>        gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> -
>        gfx_v6_0_wait_for_rlc_serdes(adev);
>  }
>
> @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>                return -EINVAL;
>
>        gfx_v6_0_rlc_stop(adev);
> -
>        gfx_v6_0_rlc_reset(adev);
> -
>        gfx_v6_0_init_pg(adev);
> -
>        gfx_v6_0_init_cg(adev);
>
>        WREG32(RLC_RL_BASE, 0);
> @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>        WREG32(RLC_UCODE_ADDR, 0);
>
>        gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> -
>        gfx_v6_0_rlc_start(adev);
>
>        return 0;
> @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
>                WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
>
>                gfx_v6_0_wait_for_rlc_serdes(adev);
> -
>                gfx_v6_0_update_rlc(adev, tmp);
>
>                WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
>  static int gfx_v6_0_wait_for_idle(void *handle)
>  {
>        unsigned i;
> -     u32 tmp;
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
>        for (i = 0; i < adev->usec_timeout; i++) {
> -             tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> -
> -             if (!tmp)
> +             if (gfx_v6_0_is_idle(handle))
>                        return 0;
>                udelay(1);
>        }
>


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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6
       [not found]                 ` <aa1ac326-ed57-21f5-df8f-5ceb4ae32ae8-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2016-09-02 12:08                   ` StDenis, Tom
  0 siblings, 0 replies; 11+ messages in thread
From: StDenis, Tom @ 2016-09-02 12:08 UTC (permalink / raw)
  To: Christian König,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org


[-- Attachment #1.1: Type: text/plain, Size: 7249 bytes --]

I'll submit a few new patches merging them in gfx 6/7/8 individually.


As for refactoring not really.  A static check would only work if all of the code were in one unit.  When I was adding the config data to debugfs I just grep'ed manually to discover that they're not really read anywhere in the kernel for instance.


Tom


________________________________
From: Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
Sent: Friday, September 2, 2016 08:06
To: StDenis, Tom; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6



We could merge those to reduce the # of LOC.

Yes, please do so if you have time.

BTW: Do you know any tool/hack/whatever to find unused structure members? E.g. members which are never accessed or only set but never read?

We seem to have quite a number of those in amdgpu, radeon as well as TTM. Would be nice to clean such stuff up.

Christian.

Am 02.09.2016 um 13:54 schrieb StDenis, Tom:

Nope your eyes are fine.  Note that the same pattern exists in gfx_v8_0.c as well.  I guess different ring struct pointers are passed so they're not talking to the same ring.


We could merge those to reduce the # of LOC.


Tom


________________________________
From: Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org><mailto:deathsimple@vodafone.de>
Sent: Thursday, September 1, 2016 13:59
To: Tom St Denis; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lMiVNPc3mojA@public.gmane.orgsktop.org>
Cc: StDenis, Tom
Subject: Re: [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6

Am 01.09.2016 um 19:44 schrieb Tom St Denis:
> Various whitespace and logical simplifications for gfx6.
>
> Signed-off-by: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org><mailto:tom.stdenis@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 40 +++++------------------------------
>   1 file changed, 5 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 5f508c96496f..63ca77937714 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1211,11 +1211,8 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>                                 SC_EARLYZ_TILE_FIFO_SIZE(adev->gfx.config.sc_earlyz_tile_fifo_size)));
>
>        WREG32(VGT_NUM_INSTANCES, 1);
> -
>        WREG32(CP_PERFMON_CNTL, 0);
> -
>        WREG32(SQ_CONFIG, 0);
> -
>        WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
>                                          FORCE_EOV_MAX_REZ_CNT(255)));
>
> @@ -1240,7 +1237,6 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
>        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
>
>        udelay(50);
> -
>   }
>
>
> @@ -1661,21 +1657,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
>
>   static u32 gfx_v6_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>   {
> -     u32 rptr;
> -
> -     rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>   }
>
>   static u32 gfx_v6_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
>   {
>        struct amdgpu_device *adev = ring->adev;
> -     u32 wptr;
>
> -     wptr = RREG32(CP_RB0_WPTR);
> -
> -     return wptr;
> +     return RREG32(CP_RB0_WPTR);
>   }
>
>   static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
> @@ -1688,9 +1677,7 @@ static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
>
>   static u32 gfx_v6_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
>   {
> -     u32 rptr = ring->adev->wb.wb[ring->rptr_offs];
> -
> -     return rptr;
> +     return ring->adev->wb.wb[ring->rptr_offs];
>   }

Am I blind or are the gfx_v6_0_ring_get_rptr_compute() and
gfx_v6_0_ring_get_rptr_gfx() functions identical?

If that's true might be a good idea to just use one function.

Either way patch is Reviewed-by: Christian König <christian.koenig-urvtwAKJhsc@public.gmane.orgm><mailto:christian.koenig-5C7GfCeVMHo@public.gmane.org>

Christian.

>
>   static u32 gfx_v6_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> @@ -1770,14 +1757,12 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>        ring->wptr = 0;
>        WREG32(CP_RB1_WPTR, ring->wptr);
>
> -
>        rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
>        WREG32(CP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
>        WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
>
>        mdelay(1);
>        WREG32(CP_RB1_CNTL, tmp);
> -
>        WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
>
>        ring = &adev->gfx.compute_ring[1];
> @@ -1797,7 +1782,6 @@ static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
>
>        mdelay(1);
>        WREG32(CP_RB2_CNTL, tmp);
> -
>        WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
>
>        adev->gfx.compute_ring[0].ready = true;
> @@ -1825,12 +1809,7 @@ static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
>
>   static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
>   {
> -     int r;
> -
> -     r = gfx_v6_0_cp_gfx_load_microcode(adev);
> -
> -     return r;
> -
> +     return gfx_v6_0_cp_gfx_load_microcode(adev);
>   }
>
>   static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
> @@ -2172,7 +2151,6 @@ static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
>        WREG32(RLC_CNTL, 0);
>
>        gfx_v6_0_enable_gui_idle_interrupt(adev, false);
> -
>        gfx_v6_0_wait_for_rlc_serdes(adev);
>   }
>
> @@ -2223,11 +2201,8 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>                return -EINVAL;
>
>        gfx_v6_0_rlc_stop(adev);
> -
>        gfx_v6_0_rlc_reset(adev);
> -
>        gfx_v6_0_init_pg(adev);
> -
>        gfx_v6_0_init_cg(adev);
>
>        WREG32(RLC_RL_BASE, 0);
> @@ -2254,7 +2229,6 @@ static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
>        WREG32(RLC_UCODE_ADDR, 0);
>
>        gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
> -
>        gfx_v6_0_rlc_start(adev);
>
>        return 0;
> @@ -2278,7 +2252,6 @@ static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
>                WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
>
>                gfx_v6_0_wait_for_rlc_serdes(adev);
> -
>                gfx_v6_0_update_rlc(adev, tmp);
>
>                WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
> @@ -2931,13 +2904,10 @@ static bool gfx_v6_0_is_idle(void *handle)
>   static int gfx_v6_0_wait_for_idle(void *handle)
>   {
>        unsigned i;
> -     u32 tmp;
>        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
>        for (i = 0; i < adev->usec_timeout; i++) {
> -             tmp = RREG32(GRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
> -
> -             if (!tmp)
> +             if (gfx_v6_0_is_idle(handle))
>                        return 0;
>                udelay(1);
>        }




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^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-09-02 12:08 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-01 17:44 Various fixes for gfx6 Tom St Denis
     [not found] ` <20160901174447.13037-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-01 17:44   ` [PATCH 1/3] drm/amd/amdgpu: Add GRBM lock to various SI functions Tom St Denis
     [not found]     ` <20160901174447.13037-2-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-01 17:57       ` Christian König
2016-09-01 17:44   ` [PATCH 2/3] drm/amd/amdgpu: Simplify mask creation in gfx6 Tom St Denis
2016-09-01 17:44   ` [PATCH 3/3] drm/amd/amdgpu: Various tidy ups for gfx6 Tom St Denis
     [not found]     ` <20160901174447.13037-4-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2016-09-01 17:59       ` Christian König
     [not found]         ` <7364a051-e423-57db-5a7f-d66d12cdeec7-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-09-02 11:54           ` StDenis, Tom
     [not found]             ` <CY4PR12MB1768BF04DBC2C421B0FC969FF7E50-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-09-02 12:06               ` Christian König
     [not found]                 ` <aa1ac326-ed57-21f5-df8f-5ceb4ae32ae8-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-09-02 12:08                   ` StDenis, Tom
2016-09-02  3:22       ` Edward O'Callaghan
     [not found]         ` <717365b4-0cdd-95a4-9e8c-4b04660844c6-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
2016-09-02 12:06           ` StDenis, Tom

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