From: David Francis <David.Francis@amd.com>
To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org
Cc: Leo Li <sunpeng.li@amd.com>,
David Francis <David.Francis@amd.com>,
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors
Date: Wed, 21 Aug 2019 16:01:29 -0400 [thread overview]
Message-ID: <20190821200129.11575-17-David.Francis@amd.com> (raw)
In-Reply-To: <20190821200129.11575-1-David.Francis@amd.com>
Whenever a connector on an MST network is attached, detached, or
undergoes a modeset, the DSC configs for each stream on that
topology will be recalculated. This can change their required
bandwidth, requiring a full reprogramming, as though a modeset
was performed, even if that stream did not change timing.
Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset,
for each crtc that shares a MST topology with that stream and
supports DSC, add that crtc (and all affected connectors and
planes) to the atomic state and set mode_changed on its state
v2: Do this check only on Navi and before adding connectors
and planes on modesetting crtcs
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Lyude Paul <lyude@redhat.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 145fd73025dc..702fb0e29053 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6475,7 +6475,73 @@ static int do_aquire_global_lock(struct drm_device *dev,
return ret < 0 ? ret : 0;
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+/*
+ * TODO: This logic should at some point be moved into DRM
+ */
+static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
+{
+ struct drm_connector *connector;
+ struct drm_connector_state *conn_state;
+ struct drm_connector_list_iter conn_iter;
+ struct drm_crtc_state *new_crtc_state;
+ struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add;
+ int i, j;
+ struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 };
+
+ for_each_new_connector_in_state(state, connector, conn_state, i) {
+ if (conn_state->crtc != crtc)
+ continue;
+
+ aconnector = to_amdgpu_dm_connector(connector);
+ if (!aconnector->port)
+ aconnector = NULL;
+ else
+ break;
+ }
+
+ if (!aconnector)
+ return 0;
+
+ i = 0;
+ drm_connector_list_iter_begin(state->dev, &conn_iter);
+ drm_for_each_connector_iter(connector, &conn_iter) {
+ if (!connector->state || !connector->state->crtc)
+ continue;
+
+ aconnector_to_add = to_amdgpu_dm_connector(connector);
+ if (!aconnector_to_add->port)
+ continue;
+
+ if (aconnector_to_add->port->mgr != aconnector->port->mgr)
+ continue;
+
+ if (!aconnector_to_add->dc_sink)
+ continue;
+
+ if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported)
+ continue;
+
+ if (i >= AMDGPU_MAX_CRTCS)
+ continue;
+
+ crtcs_affected[i] = connector->state->crtc;
+ i++;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ for (j = 0; j < i; j++) {
+ new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]);
+ if (IS_ERR(new_crtc_state))
+ return PTR_ERR(new_crtc_state);
+ new_crtc_state->mode_changed = true;
+ }
+
+ return 0;
+
+}
+#endif
static void get_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state,
struct dm_connector_state *new_con_state)
@@ -7160,6 +7226,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (adev->asic_type >= CHIP_NAVI10) {
+ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+ ret = add_affected_mst_dsc_crtcs(state, crtc);
+ if (ret)
+ goto fail;
+ }
+ }
+ }
+#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
!new_crtc_state->color_mgmt_changed &&
--
2.17.1
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next prev parent reply other threads:[~2019-08-21 20:01 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 20:01 [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi David Francis
2019-08-21 20:01 ` [PATCH v3 01/16] Revert "drm/amd/display: skip dsc config for navi10 bring up" David Francis
2019-08-21 20:01 ` [PATCH v3 02/16] Revert "drm/amd/display: navi10 bring up skip dsc encoder config" David Francis
2019-08-21 20:01 ` [PATCH v3 03/16] Revert "drm/amd/display: add global master update lock for DCN2" David Francis
2019-08-21 20:01 ` [PATCH v3 04/16] Revert "drm/amd/display: Fix underscan not using proper scaling" David Francis
2019-08-21 20:01 ` [PATCH v3 05/16] drm/amd/display: Enable SST DSC in DM David Francis
2019-08-21 20:01 ` [PATCH v3 09/16] drm/dp-mst: Parse FEC capability on MST ports David Francis
[not found] ` <20190821200129.11575-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-21 20:01 ` [PATCH v3 06/16] drm/dp-mst: Add PBN calculation for DSC modes David Francis
[not found] ` <20190821200129.11575-7-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-21 20:03 ` Lyude Paul
2019-08-21 20:01 ` [PATCH v3 07/16] drm/amd/display: Use correct helpers to compute timeslots David Francis
2019-08-21 20:01 ` [PATCH v3 08/16] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
2019-08-21 20:01 ` [PATCH v3 10/16] drm/dp-mst: Add MST support to DP DPCD R/W functions David Francis
[not found] ` <20190821200129.11575-11-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-21 21:08 ` Lyude Paul
2019-08-21 20:01 ` [PATCH v3 11/16] drm/dp-mst: Fill branch->num_ports David Francis
2019-08-21 20:01 ` [PATCH v3 12/16] drm/dp-mst: Add helpers for querying and enabling MST DSC David Francis
2019-08-21 20:01 ` [PATCH v3 13/16] drm/amd/display: Validate DSC caps on MST endpoints David Francis
2019-08-22 13:26 ` Francis, David
2019-08-21 20:01 ` [PATCH v3 14/16] drm/amd/display: Write DSC enable to MST DPCD David Francis
2019-08-21 20:01 ` [PATCH v3 15/16] drm/amd/display: MST DSC compute fair share David Francis
2019-08-21 20:01 ` David Francis [this message]
2019-08-21 20:02 ` [PATCH v3 16/16] drm/amd/display: Trigger modesets on MST DSC connectors Francis, David
[not found] ` <BN8PR12MB3217348063E5E6798009996AEFAA0-h6+T2+wrnx1RCczRXbE7rwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-08-21 20:43 ` Lyude Paul
2019-08-21 21:20 ` [PATCH v3 00/16] Display Stream Compression (DSC) for AMD Navi Lyude Paul
[not found] ` <731de9e59c86128c01ff5473a908888545f10390.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2019-08-22 13:47 ` Francis, David
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