* [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings
@ 2020-07-03 8:58 Evan Quan
2020-07-03 8:58 ` [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid " Evan Quan
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
These are needed for temp1/2/3 related hwmon interfaces.
Change-Id: I4fe04dc65ba2153bbb9c507769a9d8ddeac66094
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 6 +-----
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 17 +++++++++++++----
3 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 3687e7620eb8..0b33cde05133 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -56,10 +56,6 @@
#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
-#define CTF_OFFSET_EDGE 5
-#define CTF_OFFSET_HOTSPOT 5
-#define CTF_OFFSET_HBM 5
-
#define MSG_MAP(msg, index, valid_in_vf) \
[SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
@@ -1048,7 +1044,7 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->mem_crit_max = pptable->TmemLimit *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
+ range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 311166f1975c..4de3cdcae437 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -66,6 +66,10 @@
#define WORKLOAD_MAP(profile, workload) \
[profile] = {1, (workload)}
+#define CTF_OFFSET_EDGE 5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
+
static const struct smu_temperature_range smu11_thermal_policy[] =
{
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 97d14539c95e..350b469646bd 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1856,13 +1856,22 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
static int navi10_get_thermal_temperature_range(struct smu_context *smu,
struct smu_temperature_range *range)
{
- struct smu_table_context *table_context = &smu->smu_table;
- struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
+ PPTable_t *pptable = smu->smu_table.driver_pptable;
- if (!range || !powerplay_table)
+ if (!range)
return -EINVAL;
- range->max = powerplay_table->software_shutdown_temp *
+ range->max = pptable->TedgeLimit *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ range->hotspot_crit_max = pptable->ThotspotLimit *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ range->mem_crit_max = pptable->TmemLimit *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
return 0;
--
2.27.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid temperature limit settings 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan @ 2020-07-03 8:58 ` Evan Quan 2020-07-03 8:58 ` [PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp Evan Quan ` (3 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, Evan Quan These are needed for temp1/2/3 related hwmon interfaces. Change-Id: I76ec427aaae67a0dd257e2b1d7908990eb79a5b2 Signed-off-by: Evan Quan <evan.quan@amd.com> --- .../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 46be02e4b93c..afa8e46cd2ab 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -1644,13 +1644,22 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, struct smu_temperature_range *range) { - struct smu_table_context *table_context = &smu->smu_table; - struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; + PPTable_t *pptable = smu->smu_table.driver_pptable; - if (!range || !powerplay_table) + if (!range) return -EINVAL; - range->max = powerplay_table->software_shutdown_temp * + range->max = pptable->TemperatureLimit[TEMP_EDGE] * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; return 0; -- 2.27.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan 2020-07-03 8:58 ` [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid " Evan Quan @ 2020-07-03 8:58 ` Evan Quan 2020-07-03 8:58 ` [PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving Evan Quan ` (2 subsequent siblings) 4 siblings, 0 replies; 7+ messages in thread From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, Evan Quan As it's needed in the succeeding thermal irq setting. Change-Id: Iee34fb6515a88a684c7f1214e40edb7e65245f8d Signed-off-by: Evan Quan <evan.quan@amd.com> --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 4 ++++ drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++++ drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++++ 4 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index 0b33cde05133..6518acf4df0a 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -1029,6 +1029,9 @@ static int arcturus_force_clk_levels(struct smu_context *smu, static int arcturus_get_thermal_temperature_range(struct smu_context *smu, struct smu_temperature_range *range) { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; PPTable_t *pptable = smu->smu_table.driver_pptable; if (!range) @@ -1046,6 +1049,7 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu, SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index ba8e162f44ab..4251f7dc3d68 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -119,6 +119,7 @@ struct smu_temperature_range { int mem_min; int mem_crit_max; int mem_emergency_max; + int software_shutdown_temp; }; struct smu_state_validation_block { diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 350b469646bd..0a1e1835f455 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1856,6 +1856,9 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_ static int navi10_get_thermal_temperature_range(struct smu_context *smu, struct smu_temperature_range *range) { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_powerplay_table *powerplay_table = + table_context->power_play_table; PPTable_t *pptable = smu->smu_table.driver_pptable; if (!range) @@ -1873,6 +1876,7 @@ static int navi10_get_thermal_temperature_range(struct smu_context *smu, SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index afa8e46cd2ab..18a7b695b128 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -1644,6 +1644,9 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, struct smu_temperature_range *range) { + struct smu_table_context *table_context = &smu->smu_table; + struct smu_11_0_7_powerplay_table *powerplay_table = + table_context->power_play_table; PPTable_t *pptable = smu->smu_table.driver_pptable; if (!range) @@ -1661,6 +1664,7 @@ static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; return 0; } -- 2.27.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan 2020-07-03 8:58 ` [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid " Evan Quan 2020-07-03 8:58 ` [PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp Evan Quan @ 2020-07-03 8:58 ` Evan Quan 2020-07-03 8:58 ` [PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting Evan Quan 2020-07-03 8:58 ` [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting Evan Quan 4 siblings, 0 replies; 7+ messages in thread From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, Evan Quan This can help to maintain clear code layer. Change-Id: I9c95dd70273ab56c1ddb40592574ed283a34737f Signed-off-by: Evan Quan <evan.quan@amd.com> --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 33 +++++++++++++++++++ drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 2 ++ .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 +- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 2 ++ .../drm/amd/powerplay/sienna_cichlid_ppt.c | 2 ++ drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 - drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 19 +---------- 7 files changed, 41 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 3d62a99bad84..16ff64644e2e 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -991,6 +991,33 @@ static int smu_sw_fini(void *handle) return 0; } +static int smu_get_thermal_temperature_range(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_temperature_range *range = + &smu->thermal_range; + int ret = 0; + + if (!smu->ppt_funcs->get_thermal_temperature_range) + return 0; + + ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); + if (ret) + return ret; + + adev->pm.dpm.thermal.min_temp = range->min; + adev->pm.dpm.thermal.max_temp = range->max; + adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; + adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; + adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; + adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; + adev->pm.dpm.thermal.min_mem_temp = range->mem_min; + adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; + adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; + + return ret; +} + static int smu_smc_hw_setup(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -1095,6 +1122,12 @@ static int smu_smc_hw_setup(struct smu_context *smu) return ret; } + ret = smu_get_thermal_temperature_range(smu); + if (ret) { + dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); + return ret; + } + ret = smu_enable_thermal_alert(smu); if (ret) { dev_err(adev->dev, "Failed to enable thermal alert!\n"); diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index 6518acf4df0a..209ccf38c020 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -1037,6 +1037,8 @@ static int arcturus_get_thermal_temperature_range(struct smu_context *smu, if (!range) return -EINVAL; + memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); + range->max = pptable->TedgeLimit * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 4251f7dc3d68..dede24959652 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -146,7 +146,6 @@ struct smu_power_state { struct smu_state_pcie_block pcie; struct smu_state_display_block display; struct smu_state_memroy_block memory; - struct smu_temperature_range temperatures; struct smu_state_software_algorithm_block software; struct smu_uvd_clocks uvd_clocks; struct smu_hw_power_state hardware; @@ -386,6 +385,7 @@ struct smu_context struct smu_feature smu_feature; struct amd_pp_display_configuration *display_config; struct smu_baco_context smu_baco; + struct smu_temperature_range thermal_range; void *od_settings; #if defined(CONFIG_DEBUG_FS) struct dentry *debugfs_sclk; diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 0a1e1835f455..a04a0ba632a9 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1864,6 +1864,8 @@ static int navi10_get_thermal_temperature_range(struct smu_context *smu, if (!range) return -EINVAL; + memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); + range->max = pptable->TedgeLimit * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 18a7b695b128..4180b9196504 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -1652,6 +1652,8 @@ static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu, if (!range) return -EINVAL; + memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); + range->max = pptable->TemperatureLimit[TEMP_EDGE] * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) * diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h index 5deb30452ff8..db11b9e28646 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h @@ -85,7 +85,6 @@ #define smu_dpm_set_jpeg_enable(smu, enable) smu_ppt_funcs(dpm_set_jpeg_enable, 0, smu, enable) #define smu_set_watermarks_table(smu, tab, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, tab, clock_ranges) #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw) -#define smu_get_thermal_temperature_range(smu, range) smu_ppt_funcs(get_thermal_temperature_range, 0, smu, range) #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu) #define smu_get_dpm_ultimate_freq(smu, param, min, max) smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max) #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 34bb0f0320f6..3404db490eb3 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1086,17 +1086,10 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) int smu_v11_0_enable_thermal_alert(struct smu_context *smu) { int ret = 0; - struct smu_temperature_range range; struct amdgpu_device *adev = smu->adev; - memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); - - ret = smu_get_thermal_temperature_range(smu, &range); - if (ret) - return ret; - if (smu->smu_table.thermal_controller_type) { - ret = smu_set_thermal_range(smu, range); + ret = smu_set_thermal_range(smu, smu->thermal_range); if (ret) return ret; @@ -1109,16 +1102,6 @@ int smu_v11_0_enable_thermal_alert(struct smu_context *smu) return ret; } - adev->pm.dpm.thermal.min_temp = range.min; - adev->pm.dpm.thermal.max_temp = range.max; - adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; - adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; - adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; - adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; - adev->pm.dpm.thermal.min_mem_temp = range.mem_min; - adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; - adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; - return ret; } -- 2.27.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan ` (2 preceding siblings ...) 2020-07-03 8:58 ` [PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving Evan Quan @ 2020-07-03 8:58 ` Evan Quan 2020-07-03 8:58 ` [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting Evan Quan 4 siblings, 0 replies; 7+ messages in thread From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, Evan Quan Put the common code in smu_v11_0.c instead of having one copy each. Change-Id: I6d0c27c5810ebc3273ef8b4fae07ac6dbed2715c Signed-off-by: Evan Quan <evan.quan@amd.com> --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 3404db490eb3..86a118a3a80c 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1089,10 +1089,6 @@ int smu_v11_0_enable_thermal_alert(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; if (smu->smu_table.thermal_controller_type) { - ret = smu_set_thermal_range(smu, smu->thermal_range); - if (ret) - return ret; - ret = amdgpu_irq_get(adev, &smu->irq_source, 0); if (ret) return ret; @@ -1347,6 +1343,8 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, unsigned tyep, enum amdgpu_interrupt_state state) { + struct smu_context *smu = &adev->smu; + uint32_t low, high; uint32_t val = 0; switch (state) { @@ -1367,9 +1365,19 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, break; case AMDGPU_IRQ_STATE_ENABLE: /* For THM irqs */ + low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, + smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); + high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, + smu->thermal_range.software_shutdown_temp); + val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); + val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); + val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); -- 2.27.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan ` (3 preceding siblings ...) 2020-07-03 8:58 ` [PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting Evan Quan @ 2020-07-03 8:58 ` Evan Quan 2020-07-09 20:54 ` Alex Deucher 4 siblings, 1 reply; 7+ messages in thread From: Evan Quan @ 2020-07-03 8:58 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, Evan Quan Leftover of previous cleanups. Change-Id: I36a018349647125513e47edda66db2005bd8b0c5 Signed-off-by: Evan Quan <evan.quan@amd.com> --- drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 32 ------------------- .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 -- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 ------------------- .../drm/amd/powerplay/sienna_cichlid_ppt.c | 32 ------------------- drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 -- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++-------- 6 files changed, 3 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c index 209ccf38c020..56dc20a617fd 100644 --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c @@ -2314,37 +2314,6 @@ static void arcturus_log_thermal_throttling_event(struct smu_context *smu) log_buf); } -static int arcturus_set_thermal_range(struct smu_context *smu, - struct smu_temperature_range range) -{ - struct amdgpu_device *adev = smu->adev; - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; - uint32_t val; - struct smu_table_context *table_context = &smu->smu_table; - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; - - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - static const struct pptable_funcs arcturus_ppt_funcs = { /* translate smu index into arcturus specific index */ .get_smu_msg_index = arcturus_get_smu_msg_index, @@ -2427,7 +2396,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = { .set_df_cstate = arcturus_set_df_cstate, .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, - .set_thermal_range = arcturus_set_thermal_range, }; void arcturus_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index dede24959652..52e5603dcc97 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -480,7 +480,6 @@ struct pptable_funcs { int (*set_cpu_power_state)(struct smu_context *smu); bool (*is_dpm_running)(struct smu_context *smu); int (*tables_init)(struct smu_context *smu, struct smu_table *tables); - int (*set_thermal_fan_table)(struct smu_context *smu); int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, @@ -570,7 +569,6 @@ struct pptable_funcs { int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu); int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); void (*log_thermal_throttling_event)(struct smu_context *smu); - int (*set_thermal_range)(struct smu_context *smu, struct smu_temperature_range range); }; typedef enum { diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index a04a0ba632a9..41bd6d157271 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -2340,37 +2340,6 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu) return navi10_dummy_pstate_control(smu, true); } -static int navi10_set_thermal_range(struct smu_context *smu, - struct smu_temperature_range range) -{ - struct amdgpu_device *adev = smu->adev; - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; - uint32_t val; - struct smu_table_context *table_context = &smu->smu_table; - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; - - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - static const struct pptable_funcs navi10_ppt_funcs = { .tables_init = navi10_tables_init, .alloc_dpm_context = navi10_allocate_dpm_context, @@ -2452,7 +2421,6 @@ static const struct pptable_funcs navi10_ppt_funcs = { .run_btc = navi10_run_btc, .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround, .set_power_source = smu_v11_0_set_power_source, - .set_thermal_range = navi10_set_thermal_range, }; void navi10_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 4180b9196504..ebe8b5a88f0b 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -1795,37 +1795,6 @@ static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; } -static int sienna_cichlid_set_thermal_range(struct smu_context *smu, - struct smu_temperature_range range) -{ - struct amdgpu_device *adev = smu->adev; - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; - uint32_t val; - struct smu_table_context *table_context = &smu->smu_table; - struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; - - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); - - if (low > high) - return -EINVAL; - - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); - - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); - - return 0; -} - static void sienna_cichlid_dump_pptable(struct smu_context *smu) { struct smu_table_context *table_context = &smu->smu_table; @@ -2563,7 +2532,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .baco_exit = smu_v11_0_baco_exit, .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, - .set_thermal_range = sienna_cichlid_set_thermal_range, }; void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h index db11b9e28646..8c5cf3860e38 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h @@ -60,7 +60,6 @@ #define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu) #define smu_set_default_od8_settings(smu) smu_ppt_funcs(set_default_od8_settings, 0, smu) #define smu_tables_init(smu, tab) smu_ppt_funcs(tables_init, 0, smu, tab) -#define smu_set_thermal_fan_table(smu) smu_ppt_funcs(set_thermal_fan_table, 0, smu) #define smu_enable_thermal_alert(smu) smu_ppt_funcs(enable_thermal_alert, 0, smu) #define smu_disable_thermal_alert(smu) smu_ppt_funcs(disable_thermal_alert, 0, smu) #define smu_smc_read_sensor(smu, sensor, data, size) smu_ppt_funcs(read_sensor, -EINVAL, smu, sensor, data, size) @@ -90,7 +89,6 @@ #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level) #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu) #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap) -#define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range) #define smu_disable_umc_cdr_12gbps_workaround(smu) smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu) #define smu_set_power_source(smu, power_src) smu_ppt_funcs(set_power_source, 0, smu, power_src) #define smu_i2c_eeprom_init(smu, control) smu_ppt_funcs(i2c_eeprom_init, 0, smu, control) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 86a118a3a80c..f711c1da1cad 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1085,20 +1085,10 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) int smu_v11_0_enable_thermal_alert(struct smu_context *smu) { - int ret = 0; - struct amdgpu_device *adev = smu->adev; - - if (smu->smu_table.thermal_controller_type) { - ret = amdgpu_irq_get(adev, &smu->irq_source, 0); - if (ret) - return ret; + if (smu->smu_table.thermal_controller_type) + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); - ret = smu_set_thermal_fan_table(smu); - if (ret) - return ret; - } - - return ret; + return 0; } int smu_v11_0_disable_thermal_alert(struct smu_context *smu) -- 2.27.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting 2020-07-03 8:58 ` [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting Evan Quan @ 2020-07-09 20:54 ` Alex Deucher 0 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2020-07-09 20:54 UTC (permalink / raw) To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list On Fri, Jul 3, 2020 at 4:59 AM Evan Quan <evan.quan@amd.com> wrote: > > Leftover of previous cleanups. > > Change-Id: I36a018349647125513e47edda66db2005bd8b0c5 > Signed-off-by: Evan Quan <evan.quan@amd.com> Series is: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 32 ------------------- > .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 2 -- > drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 32 ------------------- > .../drm/amd/powerplay/sienna_cichlid_ppt.c | 32 ------------------- > drivers/gpu/drm/amd/powerplay/smu_internal.h | 2 -- > drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++-------- > 6 files changed, 3 insertions(+), 113 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c > index 209ccf38c020..56dc20a617fd 100644 > --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c > @@ -2314,37 +2314,6 @@ static void arcturus_log_thermal_throttling_event(struct smu_context *smu) > log_buf); > } > > -static int arcturus_set_thermal_range(struct smu_context *smu, > - struct smu_temperature_range range) > -{ > - struct amdgpu_device *adev = smu->adev; > - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; > - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; > - uint32_t val; > - struct smu_table_context *table_context = &smu->smu_table; > - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; > - > - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, > - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); > - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); > - > - if (low > high) > - return -EINVAL; > - > - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); > - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); > - > - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); > - > - return 0; > -} > - > static const struct pptable_funcs arcturus_ppt_funcs = { > /* translate smu index into arcturus specific index */ > .get_smu_msg_index = arcturus_get_smu_msg_index, > @@ -2427,7 +2396,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = { > .set_df_cstate = arcturus_set_df_cstate, > .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, > .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, > - .set_thermal_range = arcturus_set_thermal_range, > }; > > void arcturus_set_ppt_funcs(struct smu_context *smu) > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > index dede24959652..52e5603dcc97 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h > @@ -480,7 +480,6 @@ struct pptable_funcs { > int (*set_cpu_power_state)(struct smu_context *smu); > bool (*is_dpm_running)(struct smu_context *smu); > int (*tables_init)(struct smu_context *smu, struct smu_table *tables); > - int (*set_thermal_fan_table)(struct smu_context *smu); > int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); > int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); > int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, > @@ -570,7 +569,6 @@ struct pptable_funcs { > int (*disable_umc_cdr_12gbps_workaround)(struct smu_context *smu); > int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); > void (*log_thermal_throttling_event)(struct smu_context *smu); > - int (*set_thermal_range)(struct smu_context *smu, struct smu_temperature_range range); > }; > > typedef enum { > diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > index a04a0ba632a9..41bd6d157271 100644 > --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c > @@ -2340,37 +2340,6 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu) > return navi10_dummy_pstate_control(smu, true); > } > > -static int navi10_set_thermal_range(struct smu_context *smu, > - struct smu_temperature_range range) > -{ > - struct amdgpu_device *adev = smu->adev; > - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; > - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; > - uint32_t val; > - struct smu_table_context *table_context = &smu->smu_table; > - struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; > - > - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, > - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); > - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); > - > - if (low > high) > - return -EINVAL; > - > - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); > - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); > - > - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); > - > - return 0; > -} > - > static const struct pptable_funcs navi10_ppt_funcs = { > .tables_init = navi10_tables_init, > .alloc_dpm_context = navi10_allocate_dpm_context, > @@ -2452,7 +2421,6 @@ static const struct pptable_funcs navi10_ppt_funcs = { > .run_btc = navi10_run_btc, > .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround, > .set_power_source = smu_v11_0_set_power_source, > - .set_thermal_range = navi10_set_thermal_range, > }; > > void navi10_set_ppt_funcs(struct smu_context *smu) > diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c > index 4180b9196504..ebe8b5a88f0b 100644 > --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c > +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c > @@ -1795,37 +1795,6 @@ static bool sienna_cichlid_is_baco_supported(struct smu_context *smu) > return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false; > } > > -static int sienna_cichlid_set_thermal_range(struct smu_context *smu, > - struct smu_temperature_range range) > -{ > - struct amdgpu_device *adev = smu->adev; > - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; > - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; > - uint32_t val; > - struct smu_table_context *table_context = &smu->smu_table; > - struct smu_11_0_7_powerplay_table *powerplay_table = table_context->power_play_table; > - > - low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, > - range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES); > - high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp); > - > - if (low > high) > - return -EINVAL; > - > - val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); > - val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); > - val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); > - > - WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); > - > - return 0; > -} > - > static void sienna_cichlid_dump_pptable(struct smu_context *smu) > { > struct smu_table_context *table_context = &smu->smu_table; > @@ -2563,7 +2532,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { > .baco_exit = smu_v11_0_baco_exit, > .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, > .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, > - .set_thermal_range = sienna_cichlid_set_thermal_range, > }; > > void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) > diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h > index db11b9e28646..8c5cf3860e38 100644 > --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h > +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h > @@ -60,7 +60,6 @@ > #define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu) > #define smu_set_default_od8_settings(smu) smu_ppt_funcs(set_default_od8_settings, 0, smu) > #define smu_tables_init(smu, tab) smu_ppt_funcs(tables_init, 0, smu, tab) > -#define smu_set_thermal_fan_table(smu) smu_ppt_funcs(set_thermal_fan_table, 0, smu) > #define smu_enable_thermal_alert(smu) smu_ppt_funcs(enable_thermal_alert, 0, smu) > #define smu_disable_thermal_alert(smu) smu_ppt_funcs(disable_thermal_alert, 0, smu) > #define smu_smc_read_sensor(smu, sensor, data, size) smu_ppt_funcs(read_sensor, -EINVAL, smu, sensor, data, size) > @@ -90,7 +89,6 @@ > #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level) > #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu) > #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap) > -#define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range) > #define smu_disable_umc_cdr_12gbps_workaround(smu) smu_ppt_funcs(disable_umc_cdr_12gbps_workaround, 0, smu) > #define smu_set_power_source(smu, power_src) smu_ppt_funcs(set_power_source, 0, smu, power_src) > #define smu_i2c_eeprom_init(smu, control) smu_ppt_funcs(i2c_eeprom_init, 0, smu, control) > diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > index 86a118a3a80c..f711c1da1cad 100644 > --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c > @@ -1085,20 +1085,10 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) > > int smu_v11_0_enable_thermal_alert(struct smu_context *smu) > { > - int ret = 0; > - struct amdgpu_device *adev = smu->adev; > - > - if (smu->smu_table.thermal_controller_type) { > - ret = amdgpu_irq_get(adev, &smu->irq_source, 0); > - if (ret) > - return ret; > + if (smu->smu_table.thermal_controller_type) > + return amdgpu_irq_get(smu->adev, &smu->irq_source, 0); > > - ret = smu_set_thermal_fan_table(smu); > - if (ret) > - return ret; > - } > - > - return ret; > + return 0; > } > > int smu_v11_0_disable_thermal_alert(struct smu_context *smu) > -- > 2.27.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-07-09 20:54 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-07-03 8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan 2020-07-03 8:58 ` [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid " Evan Quan 2020-07-03 8:58 ` [PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp Evan Quan 2020-07-03 8:58 ` [PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving Evan Quan 2020-07-03 8:58 ` [PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting Evan Quan 2020-07-03 8:58 ` [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting Evan Quan 2020-07-09 20:54 ` Alex Deucher
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