* [PATCH 01/16] drm/amd/powerplay: add more members for dpm table
@ 2020-07-10 4:47 Evan Quan
2020-07-10 4:47 ` [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11 Evan Quan
` (14 more replies)
0 siblings, 15 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Change-Id: Ic80359adb8c0e018f306782f24e3f8906436f5e2
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 3d746b75396e..289c571d6e4e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -48,6 +48,7 @@
#define SMU11_TOOL_SIZE 0x19000
+#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 2
#define CLK_MAP(clk, index) \
@@ -91,9 +92,17 @@ struct smu_11_0_max_sustainable_clocks {
uint32_t soc_clock;
};
+struct smu_11_0_dpm_clk_level {
+ bool enabled;
+ uint32_t value;
+};
+
struct smu_11_0_dpm_table {
- uint32_t min; /* MHz */
- uint32_t max; /* MHz */
+ uint32_t min; /* MHz */
+ uint32_t max; /* MHz */
+ uint32_t count;
+ bool is_fine_grained;
+ struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
};
struct smu_11_0_pcie_table {
@@ -107,7 +116,9 @@ struct smu_11_0_dpm_tables {
struct smu_11_0_dpm_table uclk_table;
struct smu_11_0_dpm_table eclk_table;
struct smu_11_0_dpm_table vclk_table;
+ struct smu_11_0_dpm_table vclk1_table;
struct smu_11_0_dpm_table dclk_table;
+ struct smu_11_0_dpm_table dclk1_table;
struct smu_11_0_dpm_table dcef_table;
struct smu_11_0_dpm_table pixel_table;
struct smu_11_0_dpm_table display_table;
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-13 14:49 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting Evan Quan
` (13 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Maximum the code sharing around smu V11.
Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 289c571d6e4e..14d6eef8cf17 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -285,6 +285,10 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value);
+int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct smu_11_0_dpm_table *single_dpm_table);
+
int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min_value,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 03be59492af1..7206b9f76042 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1951,6 +1951,44 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
value);
}
+int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ struct smu_11_0_dpm_table *single_dpm_table)
+{
+ int ret = 0;
+ uint32_t clk;
+ int i;
+
+ ret = smu_v11_0_get_dpm_level_count(smu,
+ clk_type,
+ &single_dpm_table->count);
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
+ return ret;
+ }
+
+ for (i = 0; i < single_dpm_table->count; i++) {
+ ret = smu_v11_0_get_dpm_freq_by_index(smu,
+ clk_type,
+ i,
+ &clk);
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
+ return ret;
+ }
+
+ single_dpm_table->dpm_levels[i].value = clk;
+ single_dpm_table->dpm_levels[i].enabled = true;
+
+ if (i == 0)
+ single_dpm_table->min = clk;
+ else if (i == single_dpm_table->count - 1)
+ single_dpm_table->max = clk;
+ }
+
+ return 0;
+}
+
int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min_value,
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
2020-07-10 4:47 ` [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11 Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-13 14:49 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 04/16] drm/amd/powerplay: update Navi10 default dpm table setup Evan Quan
` (12 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Preparing for coming code sharing around performance level
setting.
Change-Id: Iaa77af7a272121503f09ad5fbfbe9dff2d2597b1
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 ++++++++-----------
1 file changed, 119 insertions(+), 178 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 5b793e354704..a3747ab4af32 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
return mapping.map_to;
}
-
static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
{
struct smu_11_0_cmn2aisc_mapping mapping;
@@ -338,23 +337,11 @@ static int arcturus_allocate_dpm_context(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- if (smu_dpm->dpm_context)
- return -EINVAL;
-
- smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
+ smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
GFP_KERNEL);
if (!smu_dpm->dpm_context)
return -ENOMEM;
-
- if (smu_dpm->golden_dpm_context)
- return -EINVAL;
-
- smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
- GFP_KERNEL);
- if (!smu_dpm->golden_dpm_context)
- return -ENOMEM;
-
- smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
+ smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
GFP_KERNEL);
@@ -382,119 +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
return 0;
}
-static int
-arcturus_set_single_dpm_table(struct smu_context *smu,
- struct arcturus_single_dpm_table *single_dpm_table,
- PPCLK_e clk_id)
-{
- int ret = 0;
- uint32_t i, num_of_levels = 0, clk;
-
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_GetDpmFreqByIndex,
- (clk_id << 16 | 0xFF),
- &num_of_levels);
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
- return ret;
- }
-
- single_dpm_table->count = num_of_levels;
- for (i = 0; i < num_of_levels; i++) {
- ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_GetDpmFreqByIndex,
- (clk_id << 16 | i),
- &clk);
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
- return ret;
- }
- single_dpm_table->dpm_levels[i].value = clk;
- single_dpm_table->dpm_levels[i].enabled = true;
- }
- return 0;
-}
-
-static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
-{
- dpm_state->soft_min_level = 0x0;
- dpm_state->soft_max_level = 0xffff;
- dpm_state->hard_min_level = 0x0;
- dpm_state->hard_max_level = 0xffff;
-}
-
static int arcturus_set_default_dpm_table(struct smu_context *smu)
{
- int ret;
-
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
- struct arcturus_single_dpm_table *single_dpm_table;
-
- dpm_table = smu_dpm->dpm_context;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table = NULL;
+ int ret = 0;
- /* socclk */
- single_dpm_table = &(dpm_table->soc_table);
+ /* socclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.soc_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
- ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
- PPCLK_SOCCLK);
- if (ret) {
- dev_err(smu->adev->dev, "[%s] failed to get socclk dpm levels!\n", __func__);
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_SOCCLK,
+ dpm_table);
+ if (ret)
return ret;
- }
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
} else {
- single_dpm_table->count = 1;
- single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
}
- arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
- /* gfxclk */
- single_dpm_table = &(dpm_table->gfx_table);
+ /* gfxclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.gfx_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
- ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
- PPCLK_GFXCLK);
- if (ret) {
- dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_GFXCLK,
+ dpm_table);
+ if (ret)
return ret;
- }
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
} else {
- single_dpm_table->count = 1;
- single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
}
- arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
- /* memclk */
- single_dpm_table = &(dpm_table->mem_table);
+ /* memclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.uclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
- ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
- PPCLK_UCLK);
- if (ret) {
- dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get memclk dpm levels!");
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_UCLK,
+ dpm_table);
+ if (ret)
return ret;
- }
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
} else {
- single_dpm_table->count = 1;
- single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
}
- arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
- /* fclk */
- single_dpm_table = &(dpm_table->fclk_table);
+ /* fclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.fclk_table;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
- ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
- PPCLK_FCLK);
- if (ret) {
- dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get fclk dpm levels!");
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_FCLK,
+ dpm_table);
+ if (ret)
return ret;
- }
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
} else {
- single_dpm_table->count = 1;
- single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
}
- arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
-
- memcpy(smu_dpm->golden_dpm_context, dpm_table,
- sizeof(struct arcturus_dpm_table));
return 0;
}
@@ -622,7 +574,7 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu)
static int arcturus_get_clk_table(struct smu_context *smu,
struct pp_clock_levels_with_latency *clocks,
- struct arcturus_single_dpm_table *dpm_table)
+ struct smu_11_0_dpm_table *dpm_table)
{
int i, count;
@@ -824,14 +776,14 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
int i, now, size = 0;
int ret = 0;
struct pp_clock_levels_with_latency clocks;
- struct arcturus_single_dpm_table *single_dpm_table;
+ struct smu_11_0_dpm_table *single_dpm_table;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
+ struct smu_11_0_dpm_context *dpm_context = NULL;
if (amdgpu_ras_intr_triggered())
return snprintf(buf, PAGE_SIZE, "unavailable\n");
- dpm_table = smu_dpm->dpm_context;
+ dpm_context = smu_dpm->dpm_context;
switch (type) {
case SMU_SCLK:
@@ -841,7 +793,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
- single_dpm_table = &(dpm_table->gfx_table);
+ single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
@@ -868,7 +820,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
- single_dpm_table = &(dpm_table->mem_table);
+ single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
@@ -891,7 +843,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
- single_dpm_table = &(dpm_table->soc_table);
+ single_dpm_table = &(dpm_context->dpm_tables.soc_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
@@ -914,7 +866,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return ret;
}
- single_dpm_table = &(dpm_table->fclk_table);
+ single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
if (ret) {
dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
@@ -937,20 +889,19 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
return size;
}
-static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
- uint32_t feature_mask)
+static int arcturus_upload_dpm_level(struct smu_context *smu,
+ bool max,
+ uint32_t feature_mask,
+ uint32_t level)
{
- struct arcturus_single_dpm_table *single_dpm_table;
- struct arcturus_dpm_table *dpm_table =
+ struct smu_11_0_dpm_context *dpm_context =
smu->smu_dpm.dpm_context;
uint32_t freq;
int ret = 0;
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
(feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
- single_dpm_table = &(dpm_table->gfx_table);
- freq = max ? single_dpm_table->dpm_state.soft_max_level :
- single_dpm_table->dpm_state.soft_min_level;
+ freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_GFXCLK << 16) | (freq & 0xffff),
@@ -964,9 +915,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
(feature_mask & FEATURE_DPM_UCLK_MASK)) {
- single_dpm_table = &(dpm_table->mem_table);
- freq = max ? single_dpm_table->dpm_state.soft_max_level :
- single_dpm_table->dpm_state.soft_min_level;
+ freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_UCLK << 16) | (freq & 0xffff),
@@ -980,9 +929,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
(feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
- single_dpm_table = &(dpm_table->soc_table);
- freq = max ? single_dpm_table->dpm_state.soft_max_level :
- single_dpm_table->dpm_state.soft_min_level;
+ freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
ret = smu_send_smc_msg_with_param(smu,
(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
(PPCLK_SOCCLK << 16) | (freq & 0xffff),
@@ -1000,8 +947,8 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
static int arcturus_force_clk_levels(struct smu_context *smu,
enum smu_clk_type type, uint32_t mask)
{
- struct arcturus_dpm_table *dpm_table;
- struct arcturus_single_dpm_table *single_dpm_table;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *single_dpm_table = NULL;
uint32_t soft_min_level, soft_max_level;
uint32_t smu_version;
int ret = 0;
@@ -1021,12 +968,9 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
soft_min_level = mask ? (ffs(mask) - 1) : 0;
soft_max_level = mask ? (fls(mask) - 1) : 0;
- dpm_table = smu->smu_dpm.dpm_context;
-
switch (type) {
case SMU_SCLK:
- single_dpm_table = &(dpm_table->gfx_table);
-
+ single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
if (soft_max_level >= single_dpm_table->count) {
dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
soft_max_level, single_dpm_table->count - 1);
@@ -1034,18 +978,19 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
break;
}
- single_dpm_table->dpm_state.soft_min_level =
- single_dpm_table->dpm_levels[soft_min_level].value;
- single_dpm_table->dpm_state.soft_max_level =
- single_dpm_table->dpm_levels[soft_max_level].value;
-
- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ ret = arcturus_upload_dpm_level(smu,
+ false,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_min_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
break;
}
- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ ret = arcturus_upload_dpm_level(smu,
+ true,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_max_level);
if (ret)
dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
@@ -1256,8 +1201,7 @@ static int arcturus_get_fan_speed_percent(struct smu_context *smu,
return ret;
}
-
-static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
+static uint32_t arcturus_find_lowest_dpm_level(struct smu_11_0_dpm_table *table)
{
uint32_t i;
@@ -1274,7 +1218,7 @@ static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table
}
static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
- struct arcturus_single_dpm_table *table)
+ struct smu_11_0_dpm_table *table)
{
int i = 0;
@@ -1299,34 +1243,33 @@ static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
return i;
}
-
-
static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
{
- struct arcturus_dpm_table *dpm_table =
- (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
uint32_t soft_level;
int ret = 0;
/* gfxclk */
if (highest)
- soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
+ soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
else
- soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
+ soft_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
- dpm_table->gfx_table.dpm_state.soft_min_level =
- dpm_table->gfx_table.dpm_state.soft_max_level =
- dpm_table->gfx_table.dpm_levels[soft_level].value;
-
- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ ret = arcturus_upload_dpm_level(smu,
+ false,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload boot level to %s!\n",
highest ? "highest" : "lowest");
return ret;
}
- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ ret = arcturus_upload_dpm_level(smu,
+ true,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload dpm max level to %s!\n!",
highest ? "highest" : "lowest");
@@ -1345,27 +1288,29 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
static int arcturus_unforce_dpm_levels(struct smu_context *smu)
{
- struct arcturus_dpm_table *dpm_table =
- (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_context *dpm_context =
+ (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
uint32_t soft_min_level, soft_max_level;
int ret = 0;
/* gfxclk */
- soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
- soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
- dpm_table->gfx_table.dpm_state.soft_min_level =
- dpm_table->gfx_table.dpm_levels[soft_min_level].value;
- dpm_table->gfx_table.dpm_state.soft_max_level =
- dpm_table->gfx_table.dpm_levels[soft_max_level].value;
-
- ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
+ soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
+ soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
+
+ ret = arcturus_upload_dpm_level(smu,
+ false,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_min_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload DPM Bootup Levels!");
return ret;
}
- ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
+ ret = arcturus_upload_dpm_level(smu,
+ true,
+ FEATURE_DPM_GFXCLK_MASK,
+ soft_max_level);
if (ret) {
dev_err(smu->adev->dev, "Failed to upload DPM Max Levels!");
return ret;
@@ -1388,18 +1333,15 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
uint32_t *mclk_mask,
uint32_t *soc_mask)
{
- struct arcturus_dpm_table *dpm_table =
- (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
- struct arcturus_single_dpm_table *gfx_dpm_table;
- struct arcturus_single_dpm_table *mem_dpm_table;
- struct arcturus_single_dpm_table *soc_dpm_table;
+ struct smu_11_0_dpm_context *dpm_context =
+ (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_dpm_table;
+ struct smu_11_0_dpm_table *mem_dpm_table;
+ struct smu_11_0_dpm_table *soc_dpm_table;
- if (!smu->smu_dpm.dpm_context)
- return -EINVAL;
-
- gfx_dpm_table = &dpm_table->gfx_table;
- mem_dpm_table = &dpm_table->mem_table;
- soc_dpm_table = &dpm_table->soc_table;
+ gfx_dpm_table = &dpm_context->dpm_tables.gfx_table;
+ mem_dpm_table = &dpm_context->dpm_tables.uclk_table;
+ soc_dpm_table = &dpm_context->dpm_tables.soc_table;
*sclk_mask = 0;
*mclk_mask = 0;
@@ -2153,7 +2095,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
return ret;
}
-
static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
uint8_t address, uint32_t numbytes,
uint8_t *data)
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 04/16] drm/amd/powerplay: update Navi10 default dpm table setup
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
2020-07-10 4:47 ` [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11 Evan Quan
2020-07-10 4:47 ` [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 05/16] drm/amd/powerplay: update Sienna Cichlid " Evan Quan
` (11 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: I8114cf31e6ec8c9af4578d51749eb213befdcc71
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 182 ++++++++++++++++++---
1 file changed, 158 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d96e8334b5e2..a022e93a487c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -689,41 +689,175 @@ static int navi10_allocate_dpm_context(struct smu_context *smu)
static int navi10_set_default_dpm_table(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct smu_table_context *table_context = &smu->smu_table;
- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
- PPTable_t *driver_ppt = NULL;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table;
+ int ret = 0;
int i;
- driver_ppt = table_context->driver_pptable;
-
- dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
- dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+ /* socclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.soc_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_SOCCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
- dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
+ /* gfxclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.gfx_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_GFXCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
- dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
+ /* uclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.uclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_UCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
- dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
+ /* vclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.vclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_VCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
- dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
+ /* dclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.dclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
- dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
+ /* dcefclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.dcef_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCEFCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
- dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
+ /* pixelclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.pixel_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_PIXCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
- dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
+ /* displayclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.display_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DISPCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
- dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ /* phyclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.phy_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_PHYCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+ /* lclk dpm table setup */
for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 05/16] drm/amd/powerplay: update Sienna Cichlid default dpm table setup
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (2 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 04/16] drm/amd/powerplay: update Navi10 default dpm table setup Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 06/16] drm/amd/powerplay: add new UMD pstate data structure Evan Quan
` (10 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Change-Id: Idaa853356720e48ab3279f420ba1ae18bb7de4fd
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 234 ++++++++++++++++--
1 file changed, 211 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index f2bbe56798d7..d750d06378e9 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -597,41 +597,229 @@ static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct smu_table_context *table_context = &smu->smu_table;
- struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
- PPTable_t *driver_ppt = NULL;
+ struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
+ PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
+ struct smu_11_0_dpm_table *dpm_table;
+ int ret = 0;
int i;
- driver_ppt = table_context->driver_pptable;
+ /* socclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.soc_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_SOCCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+
+ /* gfxclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.gfx_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_GFXCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+
+ /* uclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.uclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_UCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
- dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
+ /* fclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.fclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_FCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
- dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
+ /* vclk0 dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.vclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_VCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
- dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
+ /* vclk1 dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.vclk1_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_VCLK1,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
- dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
+ /* dclk0 dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.dclk_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
- dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
+ /* dclk1 dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.dclk1_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCLK1,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
- dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
+ /* dcefclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.dcef_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DCEFCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
- dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
+ /* pixelclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.pixel_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_PIXCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
- dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
+ /* displayclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.display_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_DISPCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
- dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
- dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
+ /* phyclk dpm table setup */
+ dpm_table = &dpm_context->dpm_tables.phy_table;
+ if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+ ret = smu_v11_0_set_single_dpm_table(smu,
+ SMU_PHYCLK,
+ dpm_table);
+ if (ret)
+ return ret;
+ dpm_table->is_fine_grained =
+ !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
+ } else {
+ dpm_table->count = 1;
+ dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
+ dpm_table->dpm_levels[0].enabled = true;
+ dpm_table->min = dpm_table->dpm_levels[0].value;
+ dpm_table->max = dpm_table->dpm_levels[0].value;
+ }
+ /* lclk dpm table setup */
for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 06/16] drm/amd/powerplay: add new UMD pstate data structure
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (3 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 05/16] drm/amd/powerplay: update Sienna Cichlid " Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 07/16] drm/amd/powerplay: update UMD pstate clock settings Evan Quan
` (9 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Change-Id: I3f2ef5ee2e6e433518f726988bbe5970848b99c8
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 66912884f093..91c8b69da026 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -352,6 +352,20 @@ struct smu_baco_context
bool platform_support;
};
+struct pstates_clk_freq {
+ uint32_t min;
+ uint32_t standard;
+ uint32_t peak;
+};
+
+struct smu_umd_pstate_table {
+ struct pstates_clk_freq gfxclk_pstate;
+ struct pstates_clk_freq socclk_pstate;
+ struct pstates_clk_freq uclk_pstate;
+ struct pstates_clk_freq vclk_pstate;
+ struct pstates_clk_freq dclk_pstate;
+};
+
#define WORKLOAD_POLICY_MAX 7
struct smu_context
{
@@ -376,6 +390,7 @@ struct smu_context
struct dentry *debugfs_sclk;
#endif
+ struct smu_umd_pstate_table pstate_table;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 07/16] drm/amd/powerplay: update UMD pstate clock settings
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (4 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 06/16] drm/amd/powerplay: add new UMD pstate data structure Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 08/16] drm/amd/powerplay: update the common API for performance level setting Evan Quan
` (8 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Preparing for coming code sharing around performance level
setting.
Change-Id: I51b1536b62995f0fecd51b91f238793f57485aa9
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +-
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 47 ++++++---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 99 ++++++++++++++++---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 35 ++++---
4 files changed, 141 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6839faaab611..4080b3c792ac 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2168,6 +2168,8 @@ int smu_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2180,11 +2182,11 @@ int smu_read_sensor(struct smu_context *smu,
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
- *((uint32_t *)data) = smu->pstate_sclk;
+ *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
- *((uint32_t *)data) = smu->pstate_mclk;
+ *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a3747ab4af32..33d472ffb2be 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -548,27 +548,44 @@ static int arcturus_run_btc(struct smu_context *smu)
static int arcturus_populate_umd_state_clk(struct smu_context *smu)
{
- struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
- struct arcturus_dpm_table *dpm_table = NULL;
- struct arcturus_single_dpm_table *gfx_table = NULL;
- struct arcturus_single_dpm_table *mem_table = NULL;
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ &dpm_context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ &dpm_context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ &dpm_context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
+
+ pstate_table->gfxclk_pstate.min = gfx_table->min;
+ pstate_table->gfxclk_pstate.peak = gfx_table->max;
- dpm_table = smu_dpm->dpm_context;
- gfx_table = &(dpm_table->gfx_table);
- mem_table = &(dpm_table->mem_table);
+ pstate_table->uclk_pstate.min = mem_table->min;
+ pstate_table->uclk_pstate.peak = mem_table->max;
- smu->pstate_sclk = gfx_table->dpm_levels[0].value;
- smu->pstate_mclk = mem_table->dpm_levels[0].value;
+ pstate_table->socclk_pstate.min = soc_table->min;
+ pstate_table->socclk_pstate.peak = soc_table->max;
if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
- mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
- smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
- smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
+ soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
+ pstate_table->gfxclk_pstate.standard =
+ gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
+ pstate_table->uclk_pstate.standard =
+ mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+ pstate_table->socclk_pstate.standard =
+ soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
+ } else {
+ pstate_table->gfxclk_pstate.standard =
+ pstate_table->gfxclk_pstate.min;
+ pstate_table->uclk_pstate.standard =
+ pstate_table->uclk_pstate.min;
+ pstate_table->socclk_pstate.standard =
+ pstate_table->socclk_pstate.min;
}
- smu->pstate_sclk = smu->pstate_sclk * 100;
- smu->pstate_mclk = smu->pstate_mclk * 100;
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index a022e93a487c..d3e11d81c0ad 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1213,22 +1213,93 @@ static int navi10_force_clk_levels(struct smu_context *smu,
static int navi10_populate_umd_state_clk(struct smu_context *smu)
{
- int ret = 0;
- uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
-
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
- if (ret)
- return ret;
-
- smu->pstate_sclk = min_sclk_freq * 100;
-
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
- if (ret)
- return ret;
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ &dpm_context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ &dpm_context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ &dpm_context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t sclk_freq;
- smu->pstate_mclk = min_mclk_freq * 100;
+ pstate_table->gfxclk_pstate.min = gfx_table->min;
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ switch (adev->pdev->revision) {
+ case 0xf0: /* XTX */
+ case 0xc0:
+ sclk_freq = NAVI10_PEAK_SCLK_XTX;
+ break;
+ case 0xf1: /* XT */
+ case 0xc1:
+ sclk_freq = NAVI10_PEAK_SCLK_XT;
+ break;
+ default: /* XL */
+ sclk_freq = NAVI10_PEAK_SCLK_XL;
+ break;
+ }
+ break;
+ case CHIP_NAVI14:
+ switch (adev->pdev->revision) {
+ case 0xc7: /* XT */
+ case 0xf4:
+ sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
+ break;
+ case 0xc1: /* XTM */
+ case 0xf2:
+ sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
+ break;
+ case 0xc3: /* XLM */
+ case 0xf3:
+ sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
+ break;
+ case 0xc5: /* XTX */
+ case 0xf6:
+ sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
+ break;
+ default: /* XL */
+ sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
+ break;
+ }
+ break;
+ case CHIP_NAVI12:
+ sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
+ break;
+ default:
+ sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
+ break;
+ }
+ pstate_table->gfxclk_pstate.peak = sclk_freq;
+
+ pstate_table->uclk_pstate.min = mem_table->min;
+ pstate_table->uclk_pstate.peak = mem_table->max;
+
+ pstate_table->socclk_pstate.min = soc_table->min;
+ pstate_table->socclk_pstate.peak = soc_table->max;
+
+ if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
+ mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
+ soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
+ pstate_table->gfxclk_pstate.standard =
+ NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
+ pstate_table->uclk_pstate.standard =
+ NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
+ pstate_table->socclk_pstate.standard =
+ NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
+ } else {
+ pstate_table->gfxclk_pstate.standard =
+ pstate_table->gfxclk_pstate.min;
+ pstate_table->uclk_pstate.standard =
+ pstate_table->uclk_pstate.min;
+ pstate_table->socclk_pstate.standard =
+ pstate_table->socclk_pstate.min;
+ }
- return ret;
+ return 0;
}
static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index d750d06378e9..8fae7dd982c7 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1114,22 +1114,27 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
{
- int ret = 0;
- uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
-
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
- if (ret)
- return ret;
-
- smu->pstate_sclk = min_sclk_freq * 100;
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ &dpm_context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ &dpm_context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ &dpm_context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
+
+ pstate_table->gfxclk_pstate.min = gfx_table->min;
+ pstate_table->gfxclk_pstate.peak = gfx_table->max;
+
+ pstate_table->uclk_pstate.min = mem_table->min;
+ pstate_table->uclk_pstate.peak = mem_table->max;
+
+ pstate_table->socclk_pstate.min = soc_table->min;
+ pstate_table->socclk_pstate.peak = soc_table->max;
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
- if (ret)
- return ret;
-
- smu->pstate_mclk = min_mclk_freq * 100;
-
- return ret;
+ return 0;
}
static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
--
2.27.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 08/16] drm/amd/powerplay: update the common API for performance level setting
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (5 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 07/16] drm/amd/powerplay: update UMD pstate clock settings Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 09/16] drm/amd/powerplay: drop unnecessary Arcturus specific APIs Evan Quan
` (7 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
So that it can be more widely shared around SMU v11 ASICs.
Change-Id: Ie110edf2ec519699448d3ff3215188ba243d2415
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 91 +++++++++++++++++++----
1 file changed, 77 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 7206b9f76042..f96ff062eb64 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1855,38 +1855,101 @@ int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
int smu_v11_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{
+ struct smu_11_0_dpm_context *dpm_context =
+ smu->smu_dpm.dpm_context;
+ struct smu_11_0_dpm_table *gfx_table =
+ &dpm_context->dpm_tables.gfx_table;
+ struct smu_11_0_dpm_table *mem_table =
+ &dpm_context->dpm_tables.uclk_table;
+ struct smu_11_0_dpm_table *soc_table =
+ &dpm_context->dpm_tables.soc_table;
+ struct smu_umd_pstate_table *pstate_table =
+ &smu->pstate_table;
+ struct amdgpu_device *adev = smu->adev;
+ uint32_t sclk_min = 0, sclk_max = 0;
+ uint32_t mclk_min = 0, mclk_max = 0;
+ uint32_t socclk_min = 0, socclk_max = 0;
int ret = 0;
- uint32_t sclk_mask, mclk_mask, soc_mask;
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
+ sclk_min = sclk_max = gfx_table->max;
+ mclk_min = mclk_max = mem_table->max;
+ socclk_min = socclk_max = soc_table->max;
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
+ sclk_min = sclk_max = gfx_table->min;
+ mclk_min = mclk_max = mem_table->min;
+ socclk_min = socclk_max = soc_table->min;
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
+ sclk_min = gfx_table->min;
+ sclk_max = gfx_table->max;
+ mclk_min = mem_table->min;
+ mclk_max = mem_table->max;
+ socclk_min = soc_table->min;
+ socclk_max = soc_table->max;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = smu_unforce_dpm_levels(smu);
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
+ mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
+ socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ mclk_min = mclk_max = pstate_table->uclk_pstate.min;
+ break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = smu_get_profiling_clk_mask(smu, level,
- &sclk_mask,
- &mclk_mask,
- &soc_mask);
- if (ret)
- return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
+ mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
+ socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ return 0;
default:
- break;
+ dev_err(adev->dev, "Invalid performance level %d\n", level);
+ return -EINVAL;
+ }
+
+ /*
+ * Separate MCLK and SOCCLK soft min/max settings are not allowed
+ * on Arcturus.
+ */
+ if (adev->asic_type == CHIP_ARCTURUS) {
+ mclk_min = mclk_max = 0;
+ socclk_min = socclk_max = 0;
}
+
+ if (sclk_min && sclk_max) {
+ ret = smu_v11_0_set_soft_freq_limited_range(smu,
+ SMU_GFXCLK,
+ sclk_min,
+ sclk_max);
+ if (ret)
+ return ret;
+ }
+
+ if (mclk_min && mclk_max) {
+ ret = smu_v11_0_set_soft_freq_limited_range(smu,
+ SMU_MCLK,
+ mclk_min,
+ mclk_max);
+ if (ret)
+ return ret;
+ }
+
+ if (socclk_min && socclk_max) {
+ ret = smu_v11_0_set_soft_freq_limited_range(smu,
+ SMU_SOCCLK,
+ socclk_min,
+ socclk_max);
+ if (ret)
+ return ret;
+ }
+
return ret;
}
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 09/16] drm/amd/powerplay: drop unnecessary Arcturus specific APIs
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (6 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 08/16] drm/amd/powerplay: update the common API for performance level setting Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 10/16] drm/amd/powerplay: drop unnecessary Navi1x " Evan Quan
` (6 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: Icd96ce42218d78d670dd0c1f88663fd42108b311
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 170 -------------------
1 file changed, 170 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 33d472ffb2be..afd07c497205 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1218,173 +1218,6 @@ static int arcturus_get_fan_speed_percent(struct smu_context *smu,
return ret;
}
-static uint32_t arcturus_find_lowest_dpm_level(struct smu_11_0_dpm_table *table)
-{
- uint32_t i;
-
- for (i = 0; i < table->count; i++) {
- if (table->dpm_levels[i].enabled)
- break;
- }
- if (i >= table->count) {
- i = 0;
- table->dpm_levels[i].enabled = true;
- }
-
- return i;
-}
-
-static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
- struct smu_11_0_dpm_table *table)
-{
- int i = 0;
-
- if (table->count <= 0) {
- dev_err(smu->adev->dev, "[%s] DPM Table has no entry!", __func__);
- return 0;
- }
- if (table->count > MAX_DPM_NUMBER) {
- dev_err(smu->adev->dev, "[%s] DPM Table has too many entries!", __func__);
- return MAX_DPM_NUMBER - 1;
- }
-
- for (i = table->count - 1; i >= 0; i--) {
- if (table->dpm_levels[i].enabled)
- break;
- }
- if (i < 0) {
- i = 0;
- table->dpm_levels[i].enabled = true;
- }
-
- return i;
-}
-
-static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
-{
- struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
- struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
- uint32_t soft_level;
- int ret = 0;
-
- /* gfxclk */
- if (highest)
- soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
- else
- soft_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
-
- ret = arcturus_upload_dpm_level(smu,
- false,
- FEATURE_DPM_GFXCLK_MASK,
- soft_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload boot level to %s!\n",
- highest ? "highest" : "lowest");
- return ret;
- }
-
- ret = arcturus_upload_dpm_level(smu,
- true,
- FEATURE_DPM_GFXCLK_MASK,
- soft_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload dpm max level to %s!\n!",
- highest ? "highest" : "lowest");
- return ret;
- }
-
- if (hive)
- /*
- * Force XGMI Pstate to highest or lowest
- * TODO: revise this when xgmi dpm is functional
- */
- ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
-
- return ret;
-}
-
-static int arcturus_unforce_dpm_levels(struct smu_context *smu)
-{
- struct smu_11_0_dpm_context *dpm_context =
- (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
- struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
- uint32_t soft_min_level, soft_max_level;
- int ret = 0;
-
- /* gfxclk */
- soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
- soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
-
- ret = arcturus_upload_dpm_level(smu,
- false,
- FEATURE_DPM_GFXCLK_MASK,
- soft_min_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload DPM Bootup Levels!");
- return ret;
- }
-
- ret = arcturus_upload_dpm_level(smu,
- true,
- FEATURE_DPM_GFXCLK_MASK,
- soft_max_level);
- if (ret) {
- dev_err(smu->adev->dev, "Failed to upload DPM Max Levels!");
- return ret;
- }
-
- if (hive)
- /*
- * Reset XGMI Pstate back to default
- * TODO: revise this when xgmi dpm is functional
- */
- ret = smu_v11_0_set_xgmi_pstate(smu, 0);
-
- return ret;
-}
-
-static int
-arcturus_get_profiling_clk_mask(struct smu_context *smu,
- enum amd_dpm_forced_level level,
- uint32_t *sclk_mask,
- uint32_t *mclk_mask,
- uint32_t *soc_mask)
-{
- struct smu_11_0_dpm_context *dpm_context =
- (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
- struct smu_11_0_dpm_table *gfx_dpm_table;
- struct smu_11_0_dpm_table *mem_dpm_table;
- struct smu_11_0_dpm_table *soc_dpm_table;
-
- gfx_dpm_table = &dpm_context->dpm_tables.gfx_table;
- mem_dpm_table = &dpm_context->dpm_tables.uclk_table;
- soc_dpm_table = &dpm_context->dpm_tables.soc_table;
-
- *sclk_mask = 0;
- *mclk_mask = 0;
- *soc_mask = 0;
-
- if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
- mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
- soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
- *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
- *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
- *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
- }
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- *sclk_mask = gfx_dpm_table->count - 1;
- *mclk_mask = mem_dpm_table->count - 1;
- *soc_mask = soc_dpm_table->count - 1;
- }
-
- return 0;
-}
-
static int arcturus_get_power_limit(struct smu_context *smu)
{
struct smu_11_0_powerplay_table *powerplay_table =
@@ -2534,9 +2367,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.read_sensor = arcturus_read_sensor,
.get_fan_speed_percent = arcturus_get_fan_speed_percent,
.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
- .force_dpm_limit_value = arcturus_force_dpm_limit_value,
- .unforce_dpm_levels = arcturus_unforce_dpm_levels,
- .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
.get_power_profile_mode = arcturus_get_power_profile_mode,
.set_power_profile_mode = arcturus_set_power_profile_mode,
.set_performance_level = arcturus_set_performance_level,
--
2.27.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 10/16] drm/amd/powerplay: drop unnecessary Navi1x specific APIs
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (7 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 09/16] drm/amd/powerplay: drop unnecessary Arcturus specific APIs Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 11/16] drm/amd/powerplay: drop unnecessary Sienna Cichlid " Evan Quan
` (5 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I2c8831b9d00618c6578ee42b34e26892c5dba515
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 248 +--------------------
1 file changed, 1 insertion(+), 247 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d3e11d81c0ad..6d638a67bc4d 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1376,59 +1376,6 @@ static int navi10_display_config_changed(struct smu_context *smu)
return ret;
}
-static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq, force_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
- if (ret)
- return ret;
-
- force_freq = highest ? max_freq : min_freq;
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-static int navi10_unforce_dpm_levels(struct smu_context *smu)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
- if (ret)
- return ret;
-
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
{
if (!value)
@@ -1681,47 +1628,6 @@ static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, u
return ret;
}
-static int navi10_get_profiling_clk_mask(struct smu_context *smu,
- enum amd_dpm_forced_level level,
- uint32_t *sclk_mask,
- uint32_t *mclk_mask,
- uint32_t *soc_mask)
-{
- int ret = 0;
- uint32_t level_count = 0;
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- if (sclk_mask)
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- if (mclk_mask)
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK, &level_count);
- if (ret)
- return ret;
- *sclk_mask = level_count - 1;
- }
-
- if(mclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK, &level_count);
- if (ret)
- return ret;
- *mclk_mask = level_count - 1;
- }
-
- if(soc_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
- if (ret)
- return ret;
- *soc_mask = level_count - 1;
- }
- }
-
- return ret;
-}
-
static int navi10_notify_smc_display_config(struct smu_context *smu)
{
struct smu_clocks min_clocks = {0};
@@ -1954,155 +1860,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
return 0;
}
-static int navi10_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level);
-
-static int navi10_set_standard_performance_level(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t sclk_freq = 0, uclk_freq = 0;
-
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
- uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
- break;
- case CHIP_NAVI14:
- sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
- uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
- break;
- default:
- /* by default, this is same as auto performance level */
- return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
- }
-
- ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
- if (ret)
- return ret;
- ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static int navi10_set_peak_performance_level(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t sclk_freq = 0, uclk_freq = 0;
-
- switch (adev->asic_type) {
- case CHIP_NAVI10:
- switch (adev->pdev->revision) {
- case 0xf0: /* XTX */
- case 0xc0:
- sclk_freq = NAVI10_PEAK_SCLK_XTX;
- break;
- case 0xf1: /* XT */
- case 0xc1:
- sclk_freq = NAVI10_PEAK_SCLK_XT;
- break;
- default: /* XL */
- sclk_freq = NAVI10_PEAK_SCLK_XL;
- break;
- }
- break;
- case CHIP_NAVI14:
- switch (adev->pdev->revision) {
- case 0xc7: /* XT */
- case 0xf4:
- sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
- break;
- case 0xc1: /* XTM */
- case 0xf2:
- sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
- break;
- case 0xc3: /* XLM */
- case 0xf3:
- sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
- break;
- case 0xc5: /* XTX */
- case 0xf6:
- sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
- break;
- default: /* XL */
- sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
- break;
- }
- break;
- case CHIP_NAVI12:
- sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
- break;
- default:
- ret = smu_v11_0_get_dpm_level_range(smu,
- SMU_SCLK,
- NULL,
- &sclk_freq);
- if (ret)
- return ret;
- }
-
- ret = smu_v11_0_get_dpm_level_range(smu,
- SMU_UCLK,
- NULL,
- &uclk_freq);
- if (ret)
- return ret;
-
- ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
- if (ret)
- return ret;
- ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static int navi10_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level)
-{
- int ret = 0;
- uint32_t sclk_mask, mclk_mask, soc_mask;
-
- switch (level) {
- case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
- break;
- case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
- break;
- case AMD_DPM_FORCED_LEVEL_AUTO:
- ret = smu_unforce_dpm_levels(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = navi10_set_standard_performance_level(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- ret = smu_get_profiling_clk_mask(smu, level,
- &sclk_mask,
- &mclk_mask,
- &soc_mask);
- if (ret)
- return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = navi10_set_peak_performance_level(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_MANUAL:
- case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- default:
- break;
- }
- return ret;
-}
-
static int navi10_get_thermal_temperature_range(struct smu_context *smu,
struct smu_temperature_range *range)
{
@@ -2622,18 +2379,15 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.pre_display_config_changed = navi10_pre_display_config_changed,
.display_config_changed = navi10_display_config_changed,
.notify_smc_display_config = navi10_notify_smc_display_config,
- .force_dpm_limit_value = navi10_force_dpm_limit_value,
- .unforce_dpm_levels = navi10_unforce_dpm_levels,
.is_dpm_running = navi10_is_dpm_running,
.get_fan_speed_percent = navi10_get_fan_speed_percent,
.get_fan_speed_rpm = navi10_get_fan_speed_rpm,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
- .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
.set_watermarks_table = navi10_set_watermarks_table,
.read_sensor = navi10_read_sensor,
.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
- .set_performance_level = navi10_set_performance_level,
+ .set_performance_level = smu_v11_0_set_performance_level,
.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
.get_power_limit = navi10_get_power_limit,
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 11/16] drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (8 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 10/16] drm/amd/powerplay: drop unnecessary Navi1x " Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range Evan Quan
` (4 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Change-Id: I04c810859794b07ce8905a8df797ed6b5ae116a8
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 178 +-----------------
1 file changed, 1 insertion(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 8fae7dd982c7..27f77bde184f 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1181,59 +1181,6 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
return ret;
}
-static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq, force_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
- if (ret)
- return ret;
-
- force_freq = highest ? max_freq : min_freq;
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
-static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
-{
- int ret = 0, i = 0;
- uint32_t min_freq, max_freq;
- enum smu_clk_type clk_type;
-
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
- };
-
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
- ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
- if (ret)
- return ret;
-
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
- if (ret)
- return ret;
- }
-
- return ret;
-}
-
static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
{
if (!value)
@@ -1486,50 +1433,6 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
return ret;
}
-static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
- enum amd_dpm_forced_level level,
- uint32_t *sclk_mask,
- uint32_t *mclk_mask,
- uint32_t *soc_mask)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t level_count = 0;
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- if (sclk_mask)
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- if (mclk_mask)
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask) {
- amdgpu_gfx_off_ctrl(adev, false);
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SCLK, &level_count);
- amdgpu_gfx_off_ctrl(adev, true);
- if (ret)
- return ret;
- *sclk_mask = level_count - 1;
- }
-
- if(mclk_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_MCLK, &level_count);
- if (ret)
- return ret;
- *mclk_mask = level_count - 1;
- }
-
- if(soc_mask) {
- ret = smu_v11_0_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
- if (ret)
- return ret;
- *soc_mask = level_count - 1;
- }
- }
-
- return ret;
-}
-
static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
{
struct smu_clocks min_clocks = {0};
@@ -1761,82 +1664,6 @@ static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t
return 0;
}
-static int sienna_cichlid_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level);
-
-static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret = 0;
- uint32_t sclk_freq = 0, uclk_freq = 0;
-
- switch (adev->asic_type) {
- /* TODO: need to set specify clk value by asic type, not support yet*/
- default:
- /* by default, this is same as auto performance level */
- return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
- }
-
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
- if (ret)
- return ret;
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
- if (ret)
- return ret;
-
- return ret;
-}
-
-static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
-{
- int ret = 0;
-
- /* TODO: not support yet*/
- return ret;
-}
-
-static int sienna_cichlid_set_performance_level(struct smu_context *smu,
- enum amd_dpm_forced_level level)
-{
- int ret = 0;
- uint32_t sclk_mask, mclk_mask, soc_mask;
-
- switch (level) {
- case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
- break;
- case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
- break;
- case AMD_DPM_FORCED_LEVEL_AUTO:
- ret = smu_unforce_dpm_levels(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = sienna_cichlid_set_standard_performance_level(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- ret = smu_get_profiling_clk_mask(smu, level,
- &sclk_mask,
- &mclk_mask,
- &soc_mask);
- if (ret)
- return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
- break;
- case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
- ret = sienna_cichlid_set_peak_performance_level(smu);
- break;
- case AMD_DPM_FORCED_LEVEL_MANUAL:
- case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
- default:
- break;
- }
- return ret;
-}
-
static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
struct smu_temperature_range *range)
{
@@ -2684,18 +2511,15 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
.display_config_changed = sienna_cichlid_display_config_changed,
.notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
- .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
- .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
.is_dpm_running = sienna_cichlid_is_dpm_running,
.get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
.get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
.get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
.set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
- .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
.set_watermarks_table = sienna_cichlid_set_watermarks_table,
.read_sensor = sienna_cichlid_read_sensor,
.get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
- .set_performance_level = sienna_cichlid_set_performance_level,
+ .set_performance_level = smu_v11_0_set_performance_level,
.get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
.display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
.get_power_limit = sienna_cichlid_get_power_limit,
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (9 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 11/16] drm/amd/powerplay: drop unnecessary Sienna Cichlid " Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-13 14:53 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs Evan Quan
` (3 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Use the common smu_v11_0_set_soft_freq_limited_range.
Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 20 ++-----------------
drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++++++++++++++----
3 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 27f77bde184f..141944df97b0 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
return size;
}
-int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
- enum smu_clk_type clk_type,
- uint32_t min, uint32_t max)
-{
- struct amdgpu_device *adev = smu->adev;
- int ret;
-
- if (clk_type == SMU_GFXCLK)
- amdgpu_gfx_off_ctrl(adev, false);
- ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
- if (clk_type == SMU_GFXCLK)
- amdgpu_gfx_off_ctrl(adev, true);
-
- return ret;
-}
-
static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, uint32_t mask)
{
@@ -1097,7 +1081,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
if (ret)
goto forec_level_out;
- ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
+ ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
if (ret)
goto forec_level_out;
break;
@@ -2566,7 +2550,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.baco_enter = smu_v11_0_baco_enter,
.baco_exit = smu_v11_0_baco_exit,
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
- .set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,
+ .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,
.set_thermal_range = sienna_cichlid_set_thermal_range,
};
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 1c808ffe3ab1..91d3965bbe80 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -93,7 +93,6 @@
#define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
#define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu)
#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
-#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
#define smu_override_pcie_parameters(smu) smu_ppt_funcs(override_pcie_parameters, 0, smu)
#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
#define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index f96ff062eb64..c2779d0b51f6 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
return ret;
}
-int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t min, uint32_t max)
+int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t min,
+ uint32_t max)
{
+ struct amdgpu_device *adev = smu->adev;
int ret = 0, clk_id = 0;
uint32_t param;
@@ -1755,12 +1758,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
if (clk_id < 0)
return clk_id;
+ if (clk_type == SMU_GFXCLK &&
+ adev->asic_type == CHIP_SIENNA_CICHLID)
+ amdgpu_gfx_off_ctrl(adev, false);
+
if (max > 0) {
param = (uint32_t)((clk_id << 16) | (max & 0xffff));
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
param, NULL);
if (ret)
- return ret;
+ goto out;
}
if (min > 0) {
@@ -1768,9 +1775,14 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
param, NULL);
if (ret)
- return ret;
+ goto out;
}
+out:
+ if (clk_type == SMU_GFXCLK &&
+ adev->asic_type == CHIP_SIENNA_CICHLID)
+ amdgpu_gfx_off_ctrl(adev, true);
+
return ret;
}
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (10 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-13 3:44 ` Quan, Evan
2020-07-10 4:47 ` [PATCH 14/16] drm/amd/powerplay: drop unnecessary wrappers Evan Quan
` (2 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
if (clk_id < 0)
return clk_id;
- if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, false);
if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
}
out:
- if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+ if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, true);
return ret;
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 14/16] drm/amd/powerplay: drop unnecessary wrappers
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (11 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 15/16] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper Evan Quan
2020-07-10 4:47 ` [PATCH 16/16] drm/amd/powerplay: drop unused APIs and parameters Evan Quan
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
By calling the target APIs directly.
Change-Id: I0f24f603d2fcb94d2078a35c405a1406093ba5e3
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index d4aa01a05c54..49a8d636ef4d 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -743,26 +743,26 @@ static int renoir_set_performance_level(struct smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- ret = smu_force_dpm_limit_value(smu, true);
+ ret = renoir_force_dpm_limit_value(smu, true);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- ret = smu_force_dpm_limit_value(smu, false);
+ ret = renoir_force_dpm_limit_value(smu, false);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
- ret = smu_unforce_dpm_levels(smu);
+ ret = renoir_unforce_dpm_levels(smu);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
- ret = smu_get_profiling_clk_mask(smu, level,
- &sclk_mask,
- &mclk_mask,
- &soc_mask);
+ ret = renoir_get_profiling_clk_mask(smu, level,
+ &sclk_mask,
+ &mclk_mask,
+ &soc_mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
- smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
- smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+ renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
+ renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+ renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
ret = renoir_set_peak_clock_by_device(smu);
@@ -942,8 +942,6 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
- .force_dpm_limit_value = renoir_force_dpm_limit_value,
- .unforce_dpm_levels = renoir_unforce_dpm_levels,
.get_workload_type = renoir_get_workload_type,
.get_profiling_clk_mask = renoir_get_profiling_clk_mask,
.force_clk_levels = renoir_force_clk_levels,
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 15/16] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (12 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 14/16] drm/amd/powerplay: drop unnecessary wrappers Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
2020-07-10 4:47 ` [PATCH 16/16] drm/amd/powerplay: drop unused APIs and parameters Evan Quan
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.
Change-Id: I6f7a594235dffdf75b56d1de5b9dc6d49833d7e8
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h | 3 -
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 172 ++++++++++++++----
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 100 ----------
3 files changed, 138 insertions(+), 137 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 0c1e1455c68f..fd83a723f32c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -73,9 +73,6 @@ int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
int smu_v12_0_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num);
-int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max);
-
int smu_v12_0_mode2_reset(struct smu_context *smu);
int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 49a8d636ef4d..5b76d67d03d7 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -241,6 +241,137 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type
return 0;
}
+static int renoir_get_profiling_clk_mask(struct smu_context *smu,
+ enum amd_dpm_forced_level level,
+ uint32_t *sclk_mask,
+ uint32_t *mclk_mask,
+ uint32_t *soc_mask)
+{
+
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ if (sclk_mask)
+ *sclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ if (mclk_mask)
+ *mclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ if(sclk_mask)
+ /* The sclk as gfxclk and has three level about max/min/current */
+ *sclk_mask = 3 - 1;
+
+ if(mclk_mask)
+ *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
+
+ if(soc_mask)
+ *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
+ }
+
+ return 0;
+}
+
+static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *min,
+ uint32_t *max)
+{
+ int ret = 0;
+ uint32_t mclk_mask, soc_mask;
+ uint32_t clock_limit;
+
+ if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
+ switch (clk_type) {
+ case SMU_MCLK:
+ case SMU_UCLK:
+ clock_limit = smu->smu_table.boot_values.uclk;
+ break;
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ clock_limit = smu->smu_table.boot_values.gfxclk;
+ break;
+ case SMU_SOCCLK:
+ clock_limit = smu->smu_table.boot_values.socclk;
+ break;
+ default:
+ clock_limit = 0;
+ break;
+ }
+
+ /* clock in Mhz unit */
+ if (min)
+ *min = clock_limit / 100;
+ if (max)
+ *max = clock_limit / 100;
+
+ return 0;
+ }
+
+ if (max) {
+ ret = renoir_get_profiling_clk_mask(smu,
+ AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
+ NULL,
+ &mclk_mask,
+ &soc_mask);
+ if (ret)
+ goto failed;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
+ if (ret) {
+ dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
+ goto failed;
+ }
+ break;
+ case SMU_UCLK:
+ case SMU_FCLK:
+ case SMU_MCLK:
+ ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
+ if (ret)
+ goto failed;
+ break;
+ case SMU_SOCCLK:
+ ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
+ if (ret)
+ goto failed;
+ break;
+ default:
+ ret = -EINVAL;
+ goto failed;
+ }
+ }
+
+ if (min) {
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ case SMU_SCLK:
+ ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
+ if (ret) {
+ dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
+ goto failed;
+ }
+ break;
+ case SMU_UCLK:
+ case SMU_FCLK:
+ case SMU_MCLK:
+ ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
+ if (ret)
+ goto failed;
+ break;
+ case SMU_SOCCLK:
+ ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
+ if (ret)
+ goto failed;
+ break;
+ default:
+ ret = -EINVAL;
+ goto failed;
+ }
+ }
+failed:
+ return ret;
+}
+
static int renoir_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{
@@ -264,7 +395,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
case SMU_SCLK:
/* retirve table returned paramters unit is MHz */
cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
+ ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
if (!ret) {
/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
if (cur_value == max)
@@ -434,7 +565,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
for (i = 0; i < ARRAY_SIZE(clks); i++) {
clk_type = clks[i];
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
+ ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
if (ret)
return ret;
@@ -468,7 +599,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
clk_type = clk_feature_map[i].clk_type;
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
+ ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
if (ret)
return ret;
@@ -552,33 +683,6 @@ static int renoir_get_workload_type(struct smu_context *smu, uint32_t profile)
return pplib_workload;
}
-static int renoir_get_profiling_clk_mask(struct smu_context *smu,
- enum amd_dpm_forced_level level,
- uint32_t *sclk_mask,
- uint32_t *mclk_mask,
- uint32_t *soc_mask)
-{
-
- if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
- if (sclk_mask)
- *sclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
- if (mclk_mask)
- *mclk_mask = 0;
- } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
- if(sclk_mask)
- /* The sclk as gfxclk and has three level about max/min/current */
- *sclk_mask = 3 - 1;
-
- if(mclk_mask)
- *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
-
- if(soc_mask)
- *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
- }
-
- return 0;
-}
/**
* This interface get dpm clock table for dc
@@ -633,7 +737,7 @@ static int renoir_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
+ ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
if (ret)
return ret;
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
@@ -716,7 +820,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
int ret = 0;
uint32_t sclk_freq = 0, uclk_freq = 0;
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
+ ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
if (ret)
return ret;
@@ -724,7 +828,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
if (ret)
return ret;
- ret = smu_v12_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
+ ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
if (ret)
return ret;
@@ -961,7 +1065,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.fini_smc_tables = smu_v12_0_fini_smc_tables,
.set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
.get_enabled_mask = smu_v12_0_get_enabled_mask,
- .get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
+ .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
.mode2_reset = smu_v12_0_mode2_reset,
.set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
.set_driver_table_location = smu_v12_0_set_driver_table_location,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 6400a0acad63..4e1b11d07438 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -316,106 +316,6 @@ int smu_v12_0_get_enabled_mask(struct smu_context *smu,
return ret;
}
-int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t *min, uint32_t *max)
-{
- int ret = 0;
- uint32_t mclk_mask, soc_mask;
- uint32_t clock_limit;
-
- if (!smu_clk_dpm_is_enabled(smu, clk_type)) {
- switch (clk_type) {
- case SMU_MCLK:
- case SMU_UCLK:
- clock_limit = smu->smu_table.boot_values.uclk;
- break;
- case SMU_GFXCLK:
- case SMU_SCLK:
- clock_limit = smu->smu_table.boot_values.gfxclk;
- break;
- case SMU_SOCCLK:
- clock_limit = smu->smu_table.boot_values.socclk;
- break;
- default:
- clock_limit = 0;
- break;
- }
-
- /* clock in Mhz unit */
- if (min)
- *min = clock_limit / 100;
- if (max)
- *max = clock_limit / 100;
-
- return 0;
- }
-
- if (max) {
- ret = smu_get_profiling_clk_mask(smu, AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
- NULL,
- &mclk_mask,
- &soc_mask);
- if (ret)
- goto failed;
-
- switch (clk_type) {
- case SMU_GFXCLK:
- case SMU_SCLK:
- ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
- if (ret) {
- dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
- goto failed;
- }
- break;
- case SMU_UCLK:
- case SMU_FCLK:
- case SMU_MCLK:
- ret = smu_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
- if (ret)
- goto failed;
- break;
- case SMU_SOCCLK:
- ret = smu_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
- if (ret)
- goto failed;
- break;
- default:
- ret = -EINVAL;
- goto failed;
- }
- }
-
- if (min) {
- switch (clk_type) {
- case SMU_GFXCLK:
- case SMU_SCLK:
- ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
- if (ret) {
- dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
- goto failed;
- }
- break;
- case SMU_UCLK:
- case SMU_FCLK:
- case SMU_MCLK:
- ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
- if (ret)
- goto failed;
- break;
- case SMU_SOCCLK:
- ret = smu_get_dpm_clk_limited(smu, clk_type, 0, min);
- if (ret)
- goto failed;
- break;
- default:
- ret = -EINVAL;
- goto failed;
- }
- }
-failed:
- return ret;
-}
-
int smu_v12_0_mode2_reset(struct smu_context *smu){
return smu_v12_0_send_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
}
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 16/16] drm/amd/powerplay: drop unused APIs and parameters
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
` (13 preceding siblings ...)
2020-07-10 4:47 ` [PATCH 15/16] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper Evan Quan
@ 2020-07-10 4:47 ` Evan Quan
14 siblings, 0 replies; 22+ messages in thread
From: Evan Quan @ 2020-07-10 4:47 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Leftover of previous performance level setting cleanups.
Change-Id: Idddc4adce365b34eacbc13f75cc0629859c6d412
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 12 ++++++------
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++------
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 12 +-----------
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 --
drivers/gpu/drm/amd/powerplay/smu_internal.h | 5 -----
5 files changed, 10 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index d2401379bd33..20f39aa04fb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1105,7 +1105,7 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -1173,7 +1173,7 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -1241,7 +1241,7 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
else
@@ -1311,7 +1311,7 @@ static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
else
@@ -1381,7 +1381,7 @@ static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
else
@@ -1451,7 +1451,7 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
}
if (is_support_sw_smu(adev))
- ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask, true);
+ ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
else if (adev->powerplay.pp_funcs->force_clock_level)
ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
else
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4080b3c792ac..38b3b47d12b7 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1764,8 +1764,7 @@ int smu_set_display_count(struct smu_context *smu, uint32_t count)
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask,
- bool lock_needed)
+ uint32_t mask)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
@@ -1778,14 +1777,12 @@ int smu_force_clk_levels(struct smu_context *smu,
return -EINVAL;
}
- if (lock_needed)
- mutex_lock(&smu->mutex);
+ mutex_lock(&smu->mutex);
if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
- if (lock_needed)
- mutex_unlock(&smu->mutex);
+ mutex_unlock(&smu->mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 91c8b69da026..470b0377a860 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -476,13 +476,6 @@ struct pptable_funcs {
int (*display_config_changed)(struct smu_context *smu);
int (*apply_clocks_adjust_rules)(struct smu_context *smu);
int (*notify_smc_display_config)(struct smu_context *smu);
- int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
- int (*unforce_dpm_levels)(struct smu_context *smu);
- int (*get_profiling_clk_mask)(struct smu_context *smu,
- enum amd_dpm_forced_level level,
- uint32_t *sclk_mask,
- uint32_t *mclk_mask,
- uint32_t *soc_mask);
int (*set_cpu_power_state)(struct smu_context *smu);
bool (*is_dpm_running)(struct smu_context *smu);
int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
@@ -498,8 +491,6 @@ struct pptable_funcs {
int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
void (*dump_pptable)(struct smu_context *smu);
int (*get_power_limit)(struct smu_context *smu);
- int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type clk_type,
- uint32_t dpm_level, uint32_t *freq);
int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
@@ -745,8 +736,7 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
- uint32_t mask,
- bool lock_needed);
+ uint32_t mask);
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
int smu_set_df_cstate(struct smu_context *smu,
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 5b76d67d03d7..866ae014eda2 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -1041,13 +1041,11 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.get_smu_table_index = renoir_get_smu_table_index,
.tables_init = renoir_tables_init,
.set_power_state = NULL,
- .get_dpm_clk_limited = renoir_get_dpm_clk_limited,
.print_clk_levels = renoir_print_clk_levels,
.get_current_power_state = renoir_get_current_power_state,
.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
.get_workload_type = renoir_get_workload_type,
- .get_profiling_clk_mask = renoir_get_profiling_clk_mask,
.force_clk_levels = renoir_force_clk_levels,
.set_power_profile_mode = renoir_set_power_profile_mode,
.set_performance_level = renoir_set_performance_level,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 91d3965bbe80..727498a6e76d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -68,8 +68,6 @@
#define smu_display_config_changed(smu) smu_ppt_funcs(display_config_changed, 0 , smu)
#define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu)
#define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu)
-#define smu_force_dpm_limit_value(smu, highest) smu_ppt_funcs(force_dpm_limit_value, 0, smu, highest)
-#define smu_unforce_dpm_levels(smu) smu_ppt_funcs(unforce_dpm_levels, 0, smu)
#define smu_set_cpu_power_state(smu) smu_ppt_funcs(set_cpu_power_state, 0, smu)
#define smu_msg_get_index(smu, msg) smu_ppt_funcs(get_smu_msg_index, -EINVAL, smu, msg)
#define smu_clk_get_index(smu, clk) smu_ppt_funcs(get_smu_clk_index, -EINVAL, smu, clk)
@@ -92,7 +90,6 @@
#define smu_get_dpm_ultimate_freq(smu, param, min, max) smu_ppt_funcs(get_dpm_ultimate_freq, 0, smu, param, min, max)
#define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
#define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu)
-#define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
#define smu_override_pcie_parameters(smu) smu_ppt_funcs(override_pcie_parameters, 0, smu)
#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
#define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range)
@@ -103,7 +100,5 @@
#define smu_get_unique_id(smu) smu_ppt_funcs(get_unique_id, 0, smu)
#define smu_log_thermal_throttling(smu) smu_ppt_funcs(log_thermal_throttling_event, 0, smu)
#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu)
-#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
- smu_ppt_funcs(get_profiling_clk_mask, 0, smu, level, sclk_mask, mclk_mask, soc_mask)
#endif
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
2020-07-10 4:47 ` [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs Evan Quan
@ 2020-07-13 3:44 ` Quan, Evan
2020-07-14 6:55 ` Quan, Evan
0 siblings, 1 reply; 22+ messages in thread
From: Quan, Evan @ 2020-07-13 3:44 UTC (permalink / raw)
To: amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
Ping for this one and patch12, patch2 and patch3
BR
Evan
-----Original Message-----
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Friday, July 10, 2020 12:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
if (clk_id < 0)
return clk_id;
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, false);
if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
}
out:
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, true);
return ret;
--
2.27.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11
2020-07-10 4:47 ` [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11 Evan Quan
@ 2020-07-13 14:49 ` Alex Deucher
0 siblings, 0 replies; 22+ messages in thread
From: Alex Deucher @ 2020-07-13 14:49 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Maximum the code sharing around smu V11.
>
> Change-Id: Ice0a874f3f70457f1012ca566f9f784ff3e9cd94
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 4 ++
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 38 +++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> index 289c571d6e4e..14d6eef8cf17 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
> @@ -285,6 +285,10 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
> enum smu_clk_type clk_type,
> uint32_t *value);
>
> +int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + struct smu_11_0_dpm_table *single_dpm_table);
> +
> int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
> enum smu_clk_type clk_type,
> uint32_t *min_value,
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 03be59492af1..7206b9f76042 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1951,6 +1951,44 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
> value);
> }
>
> +int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + struct smu_11_0_dpm_table *single_dpm_table)
> +{
> + int ret = 0;
> + uint32_t clk;
> + int i;
> +
> + ret = smu_v11_0_get_dpm_level_count(smu,
> + clk_type,
> + &single_dpm_table->count);
> + if (ret) {
> + dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
> + return ret;
> + }
> +
> + for (i = 0; i < single_dpm_table->count; i++) {
> + ret = smu_v11_0_get_dpm_freq_by_index(smu,
> + clk_type,
> + i,
> + &clk);
> + if (ret) {
> + dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
> + return ret;
> + }
> +
> + single_dpm_table->dpm_levels[i].value = clk;
> + single_dpm_table->dpm_levels[i].enabled = true;
> +
> + if (i == 0)
> + single_dpm_table->min = clk;
> + else if (i == single_dpm_table->count - 1)
> + single_dpm_table->max = clk;
> + }
> +
> + return 0;
> +}
> +
> int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
> enum smu_clk_type clk_type,
> uint32_t *min_value,
> --
> 2.27.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting
2020-07-10 4:47 ` [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting Evan Quan
@ 2020-07-13 14:49 ` Alex Deucher
0 siblings, 0 replies; 22+ messages in thread
From: Alex Deucher @ 2020-07-13 14:49 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Preparing for coming code sharing around performance level
> setting.
>
> Change-Id: Iaa77af7a272121503f09ad5fbfbe9dff2d2597b1
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 297 ++++++++-----------
> 1 file changed, 119 insertions(+), 178 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> index 5b793e354704..a3747ab4af32 100644
> --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
> @@ -291,7 +291,6 @@ static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
> return mapping.map_to;
> }
>
> -
> static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
> {
> struct smu_11_0_cmn2aisc_mapping mapping;
> @@ -338,23 +337,11 @@ static int arcturus_allocate_dpm_context(struct smu_context *smu)
> {
> struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
>
> - if (smu_dpm->dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
> + smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
> GFP_KERNEL);
> if (!smu_dpm->dpm_context)
> return -ENOMEM;
> -
> - if (smu_dpm->golden_dpm_context)
> - return -EINVAL;
> -
> - smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
> - GFP_KERNEL);
> - if (!smu_dpm->golden_dpm_context)
> - return -ENOMEM;
> -
> - smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
> + smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
>
> smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
> GFP_KERNEL);
> @@ -382,119 +369,84 @@ arcturus_get_allowed_feature_mask(struct smu_context *smu,
> return 0;
> }
>
> -static int
> -arcturus_set_single_dpm_table(struct smu_context *smu,
> - struct arcturus_single_dpm_table *single_dpm_table,
> - PPCLK_e clk_id)
> -{
> - int ret = 0;
> - uint32_t i, num_of_levels = 0, clk;
> -
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | 0xFF),
> - &num_of_levels);
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
> - return ret;
> - }
> -
> - single_dpm_table->count = num_of_levels;
> - for (i = 0; i < num_of_levels; i++) {
> - ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_GetDpmFreqByIndex,
> - (clk_id << 16 | i),
> - &clk);
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
> - return ret;
> - }
> - single_dpm_table->dpm_levels[i].value = clk;
> - single_dpm_table->dpm_levels[i].enabled = true;
> - }
> - return 0;
> -}
> -
> -static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
> -{
> - dpm_state->soft_min_level = 0x0;
> - dpm_state->soft_max_level = 0xffff;
> - dpm_state->hard_min_level = 0x0;
> - dpm_state->hard_max_level = 0xffff;
> -}
> -
> static int arcturus_set_default_dpm_table(struct smu_context *smu)
> {
> - int ret;
> -
> - struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> - struct arcturus_dpm_table *dpm_table = NULL;
> - struct arcturus_single_dpm_table *single_dpm_table;
> -
> - dpm_table = smu_dpm->dpm_context;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
> + struct smu_11_0_dpm_table *dpm_table = NULL;
> + int ret = 0;
>
> - /* socclk */
> - single_dpm_table = &(dpm_table->soc_table);
> + /* socclk dpm table setup */
> + dpm_table = &dpm_context->dpm_tables.soc_table;
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
> - ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
> - PPCLK_SOCCLK);
> - if (ret) {
> - dev_err(smu->adev->dev, "[%s] failed to get socclk dpm levels!\n", __func__);
> + ret = smu_v11_0_set_single_dpm_table(smu,
> + SMU_SOCCLK,
> + dpm_table);
> + if (ret)
> return ret;
> - }
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
> } else {
> - single_dpm_table->count = 1;
> - single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> }
> - arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>
> - /* gfxclk */
> - single_dpm_table = &(dpm_table->gfx_table);
> + /* gfxclk dpm table setup */
> + dpm_table = &dpm_context->dpm_tables.gfx_table;
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
> - ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
> - PPCLK_GFXCLK);
> - if (ret) {
> - dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
> + ret = smu_v11_0_set_single_dpm_table(smu,
> + SMU_GFXCLK,
> + dpm_table);
> + if (ret)
> return ret;
> - }
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
> } else {
> - single_dpm_table->count = 1;
> - single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> }
> - arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>
> - /* memclk */
> - single_dpm_table = &(dpm_table->mem_table);
> + /* memclk dpm table setup */
> + dpm_table = &dpm_context->dpm_tables.uclk_table;
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
> - ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
> - PPCLK_UCLK);
> - if (ret) {
> - dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get memclk dpm levels!");
> + ret = smu_v11_0_set_single_dpm_table(smu,
> + SMU_UCLK,
> + dpm_table);
> + if (ret)
> return ret;
> - }
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
> } else {
> - single_dpm_table->count = 1;
> - single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> }
> - arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>
> - /* fclk */
> - single_dpm_table = &(dpm_table->fclk_table);
> + /* fclk dpm table setup */
> + dpm_table = &dpm_context->dpm_tables.fclk_table;
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
> - ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
> - PPCLK_FCLK);
> - if (ret) {
> - dev_err(smu->adev->dev, "[SetupDefaultDpmTable] failed to get fclk dpm levels!");
> + ret = smu_v11_0_set_single_dpm_table(smu,
> + SMU_FCLK,
> + dpm_table);
> + if (ret)
> return ret;
> - }
> + dpm_table->is_fine_grained =
> + !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
> } else {
> - single_dpm_table->count = 1;
> - single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
> + dpm_table->count = 1;
> + dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
> + dpm_table->dpm_levels[0].enabled = true;
> + dpm_table->min = dpm_table->dpm_levels[0].value;
> + dpm_table->max = dpm_table->dpm_levels[0].value;
> }
> - arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
> -
> - memcpy(smu_dpm->golden_dpm_context, dpm_table,
> - sizeof(struct arcturus_dpm_table));
>
> return 0;
> }
> @@ -622,7 +574,7 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu)
>
> static int arcturus_get_clk_table(struct smu_context *smu,
> struct pp_clock_levels_with_latency *clocks,
> - struct arcturus_single_dpm_table *dpm_table)
> + struct smu_11_0_dpm_table *dpm_table)
> {
> int i, count;
>
> @@ -824,14 +776,14 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> int i, now, size = 0;
> int ret = 0;
> struct pp_clock_levels_with_latency clocks;
> - struct arcturus_single_dpm_table *single_dpm_table;
> + struct smu_11_0_dpm_table *single_dpm_table;
> struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
> - struct arcturus_dpm_table *dpm_table = NULL;
> + struct smu_11_0_dpm_context *dpm_context = NULL;
>
> if (amdgpu_ras_intr_triggered())
> return snprintf(buf, PAGE_SIZE, "unavailable\n");
>
> - dpm_table = smu_dpm->dpm_context;
> + dpm_context = smu_dpm->dpm_context;
>
> switch (type) {
> case SMU_SCLK:
> @@ -841,7 +793,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> return ret;
> }
>
> - single_dpm_table = &(dpm_table->gfx_table);
> + single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
> ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
> if (ret) {
> dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
> @@ -868,7 +820,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> return ret;
> }
>
> - single_dpm_table = &(dpm_table->mem_table);
> + single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
> ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
> if (ret) {
> dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
> @@ -891,7 +843,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> return ret;
> }
>
> - single_dpm_table = &(dpm_table->soc_table);
> + single_dpm_table = &(dpm_context->dpm_tables.soc_table);
> ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
> if (ret) {
> dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
> @@ -914,7 +866,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> return ret;
> }
>
> - single_dpm_table = &(dpm_table->fclk_table);
> + single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
> ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
> if (ret) {
> dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
> @@ -937,20 +889,19 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
> return size;
> }
>
> -static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
> - uint32_t feature_mask)
> +static int arcturus_upload_dpm_level(struct smu_context *smu,
> + bool max,
> + uint32_t feature_mask,
> + uint32_t level)
> {
> - struct arcturus_single_dpm_table *single_dpm_table;
> - struct arcturus_dpm_table *dpm_table =
> + struct smu_11_0_dpm_context *dpm_context =
> smu->smu_dpm.dpm_context;
> uint32_t freq;
> int ret = 0;
>
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
> (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
> - single_dpm_table = &(dpm_table->gfx_table);
> - freq = max ? single_dpm_table->dpm_state.soft_max_level :
> - single_dpm_table->dpm_state.soft_min_level;
> + freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
> ret = smu_send_smc_msg_with_param(smu,
> (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
> (PPCLK_GFXCLK << 16) | (freq & 0xffff),
> @@ -964,9 +915,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
>
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
> (feature_mask & FEATURE_DPM_UCLK_MASK)) {
> - single_dpm_table = &(dpm_table->mem_table);
> - freq = max ? single_dpm_table->dpm_state.soft_max_level :
> - single_dpm_table->dpm_state.soft_min_level;
> + freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
> ret = smu_send_smc_msg_with_param(smu,
> (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
> (PPCLK_UCLK << 16) | (freq & 0xffff),
> @@ -980,9 +929,7 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
>
> if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
> (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
> - single_dpm_table = &(dpm_table->soc_table);
> - freq = max ? single_dpm_table->dpm_state.soft_max_level :
> - single_dpm_table->dpm_state.soft_min_level;
> + freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
> ret = smu_send_smc_msg_with_param(smu,
> (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
> (PPCLK_SOCCLK << 16) | (freq & 0xffff),
> @@ -1000,8 +947,8 @@ static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
> static int arcturus_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type type, uint32_t mask)
> {
> - struct arcturus_dpm_table *dpm_table;
> - struct arcturus_single_dpm_table *single_dpm_table;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> + struct smu_11_0_dpm_table *single_dpm_table = NULL;
> uint32_t soft_min_level, soft_max_level;
> uint32_t smu_version;
> int ret = 0;
> @@ -1021,12 +968,9 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
> soft_min_level = mask ? (ffs(mask) - 1) : 0;
> soft_max_level = mask ? (fls(mask) - 1) : 0;
>
> - dpm_table = smu->smu_dpm.dpm_context;
> -
> switch (type) {
> case SMU_SCLK:
> - single_dpm_table = &(dpm_table->gfx_table);
> -
> + single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
> if (soft_max_level >= single_dpm_table->count) {
> dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
> soft_max_level, single_dpm_table->count - 1);
> @@ -1034,18 +978,19 @@ static int arcturus_force_clk_levels(struct smu_context *smu,
> break;
> }
>
> - single_dpm_table->dpm_state.soft_min_level =
> - single_dpm_table->dpm_levels[soft_min_level].value;
> - single_dpm_table->dpm_state.soft_max_level =
> - single_dpm_table->dpm_levels[soft_max_level].value;
> -
> - ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
> + ret = arcturus_upload_dpm_level(smu,
> + false,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_min_level);
> if (ret) {
> dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
> break;
> }
>
> - ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
> + ret = arcturus_upload_dpm_level(smu,
> + true,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_max_level);
> if (ret)
> dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
>
> @@ -1256,8 +1201,7 @@ static int arcturus_get_fan_speed_percent(struct smu_context *smu,
> return ret;
> }
>
> -
> -static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
> +static uint32_t arcturus_find_lowest_dpm_level(struct smu_11_0_dpm_table *table)
> {
> uint32_t i;
>
> @@ -1274,7 +1218,7 @@ static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table
> }
>
> static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
> - struct arcturus_single_dpm_table *table)
> + struct smu_11_0_dpm_table *table)
> {
> int i = 0;
>
> @@ -1299,34 +1243,33 @@ static uint32_t arcturus_find_highest_dpm_level(struct smu_context *smu,
> return i;
> }
>
> -
> -
> static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
> {
> - struct arcturus_dpm_table *dpm_table =
> - (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
> + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
> struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
> uint32_t soft_level;
> int ret = 0;
>
> /* gfxclk */
> if (highest)
> - soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
> + soft_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
> else
> - soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
> + soft_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
>
> - dpm_table->gfx_table.dpm_state.soft_min_level =
> - dpm_table->gfx_table.dpm_state.soft_max_level =
> - dpm_table->gfx_table.dpm_levels[soft_level].value;
> -
> - ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
> + ret = arcturus_upload_dpm_level(smu,
> + false,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_level);
> if (ret) {
> dev_err(smu->adev->dev, "Failed to upload boot level to %s!\n",
> highest ? "highest" : "lowest");
> return ret;
> }
>
> - ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
> + ret = arcturus_upload_dpm_level(smu,
> + true,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_level);
> if (ret) {
> dev_err(smu->adev->dev, "Failed to upload dpm max level to %s!\n!",
> highest ? "highest" : "lowest");
> @@ -1345,27 +1288,29 @@ static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
>
> static int arcturus_unforce_dpm_levels(struct smu_context *smu)
> {
> - struct arcturus_dpm_table *dpm_table =
> - (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
> + struct smu_11_0_dpm_context *dpm_context =
> + (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
> struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
> uint32_t soft_min_level, soft_max_level;
> int ret = 0;
>
> /* gfxclk */
> - soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
> - soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_table->gfx_table));
> - dpm_table->gfx_table.dpm_state.soft_min_level =
> - dpm_table->gfx_table.dpm_levels[soft_min_level].value;
> - dpm_table->gfx_table.dpm_state.soft_max_level =
> - dpm_table->gfx_table.dpm_levels[soft_max_level].value;
> -
> - ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
> + soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_context->dpm_tables.gfx_table));
> + soft_max_level = arcturus_find_highest_dpm_level(smu, &(dpm_context->dpm_tables.gfx_table));
> +
> + ret = arcturus_upload_dpm_level(smu,
> + false,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_min_level);
> if (ret) {
> dev_err(smu->adev->dev, "Failed to upload DPM Bootup Levels!");
> return ret;
> }
>
> - ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
> + ret = arcturus_upload_dpm_level(smu,
> + true,
> + FEATURE_DPM_GFXCLK_MASK,
> + soft_max_level);
> if (ret) {
> dev_err(smu->adev->dev, "Failed to upload DPM Max Levels!");
> return ret;
> @@ -1388,18 +1333,15 @@ arcturus_get_profiling_clk_mask(struct smu_context *smu,
> uint32_t *mclk_mask,
> uint32_t *soc_mask)
> {
> - struct arcturus_dpm_table *dpm_table =
> - (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
> - struct arcturus_single_dpm_table *gfx_dpm_table;
> - struct arcturus_single_dpm_table *mem_dpm_table;
> - struct arcturus_single_dpm_table *soc_dpm_table;
> + struct smu_11_0_dpm_context *dpm_context =
> + (struct smu_11_0_dpm_context *)smu->smu_dpm.dpm_context;
> + struct smu_11_0_dpm_table *gfx_dpm_table;
> + struct smu_11_0_dpm_table *mem_dpm_table;
> + struct smu_11_0_dpm_table *soc_dpm_table;
>
> - if (!smu->smu_dpm.dpm_context)
> - return -EINVAL;
> -
> - gfx_dpm_table = &dpm_table->gfx_table;
> - mem_dpm_table = &dpm_table->mem_table;
> - soc_dpm_table = &dpm_table->soc_table;
> + gfx_dpm_table = &dpm_context->dpm_tables.gfx_table;
> + mem_dpm_table = &dpm_context->dpm_tables.uclk_table;
> + soc_dpm_table = &dpm_context->dpm_tables.soc_table;
>
> *sclk_mask = 0;
> *mclk_mask = 0;
> @@ -2153,7 +2095,6 @@ static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
> return ret;
> }
>
> -
> static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t *req, bool write,
> uint8_t address, uint32_t numbytes,
> uint8_t *data)
> --
> 2.27.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
2020-07-10 4:47 ` [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range Evan Quan
@ 2020-07-13 14:53 ` Alex Deucher
0 siblings, 0 replies; 22+ messages in thread
From: Alex Deucher @ 2020-07-13 14:53 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Fri, Jul 10, 2020 at 12:48 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Use the common smu_v11_0_set_soft_freq_limited_range.
>
> Change-Id: I9f8772880b324ce9e741291751bb1b8ff4c36ea3
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../drm/amd/powerplay/sienna_cichlid_ppt.c | 20 ++-----------------
> drivers/gpu/drm/amd/powerplay/smu_internal.h | 1 -
> drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++++++++++++++----
> 3 files changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> index 27f77bde184f..141944df97b0 100644
> --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
> @@ -1046,22 +1046,6 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
> return size;
> }
>
> -int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
> - enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> -{
> - struct amdgpu_device *adev = smu->adev;
> - int ret;
> -
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, false);
> - ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
> - if (clk_type == SMU_GFXCLK)
> - amdgpu_gfx_off_ctrl(adev, true);
> -
> - return ret;
> -}
> -
> static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
> enum smu_clk_type clk_type, uint32_t mask)
> {
> @@ -1097,7 +1081,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
> if (ret)
> goto forec_level_out;
>
> - ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
> + ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
> if (ret)
> goto forec_level_out;
> break;
> @@ -2566,7 +2550,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
> .baco_enter = smu_v11_0_baco_enter,
> .baco_exit = smu_v11_0_baco_exit,
> .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
> - .set_soft_freq_limited_range = sienna_cichlid_set_soft_freq_limited_range,
> + .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
> .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
> .set_thermal_range = sienna_cichlid_set_thermal_range,
> };
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> index 1c808ffe3ab1..91d3965bbe80 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
> +++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
> @@ -93,7 +93,6 @@
> #define smu_asic_set_performance_level(smu, level) smu_ppt_funcs(set_performance_level, -EINVAL, smu, level)
> #define smu_dump_pptable(smu) smu_ppt_funcs(dump_pptable, 0, smu)
> #define smu_get_dpm_clk_limited(smu, clk_type, dpm_level, freq) smu_ppt_funcs(get_dpm_clk_limited, -EINVAL, smu, clk_type, dpm_level, freq)
> -#define smu_set_soft_freq_limited_range(smu, clk_type, min, max) smu_ppt_funcs(set_soft_freq_limited_range, -EINVAL, smu, clk_type, min, max)
> #define smu_override_pcie_parameters(smu) smu_ppt_funcs(override_pcie_parameters, 0, smu)
> #define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) smu_ppt_funcs(update_pcie_parameters, 0, smu, pcie_gen_cap, pcie_width_cap)
> #define smu_set_thermal_range(smu, range) smu_ppt_funcs(set_thermal_range, 0, smu, range)
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index f96ff062eb64..c2779d0b51f6 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1745,9 +1745,12 @@ int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type c
> return ret;
> }
>
> -int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
> - uint32_t min, uint32_t max)
> +int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
> + enum smu_clk_type clk_type,
> + uint32_t min,
> + uint32_t max)
> {
> + struct amdgpu_device *adev = smu->adev;
> int ret = 0, clk_id = 0;
> uint32_t param;
>
> @@ -1755,12 +1758,16 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
> if (clk_id < 0)
> return clk_id;
>
> + if (clk_type == SMU_GFXCLK &&
> + adev->asic_type == CHIP_SIENNA_CICHLID)
> + amdgpu_gfx_off_ctrl(adev, false);
> +
> if (max > 0) {
> param = (uint32_t)((clk_id << 16) | (max & 0xffff));
> ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
> param, NULL);
> if (ret)
> - return ret;
> + goto out;
> }
>
> if (min > 0) {
> @@ -1768,9 +1775,14 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
> ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
> param, NULL);
> if (ret)
> - return ret;
> + goto out;
> }
>
> +out:
> + if (clk_type == SMU_GFXCLK &&
> + adev->asic_type == CHIP_SIENNA_CICHLID)
> + amdgpu_gfx_off_ctrl(adev, true);
> +
> return ret;
> }
>
> --
> 2.27.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
2020-07-13 3:44 ` Quan, Evan
@ 2020-07-14 6:55 ` Quan, Evan
2020-07-14 13:48 ` Deucher, Alexander
0 siblings, 1 reply; 22+ messages in thread
From: Quan, Evan @ 2020-07-14 6:55 UTC (permalink / raw)
To: amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
Can I have a RB for this patch also?
BR
Evan
-----Original Message-----
From: Quan, Evan
Sent: Monday, July 13, 2020 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Ping for this one and patch12, patch2 and patch3
BR
Evan
-----Original Message-----
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Friday, July 10, 2020 12:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
if (clk_id < 0)
return clk_id;
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, false);
if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
}
out:
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, true);
return ret;
--
2.27.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
2020-07-14 6:55 ` Quan, Evan
@ 2020-07-14 13:48 ` Deucher, Alexander
0 siblings, 0 replies; 22+ messages in thread
From: Deucher, Alexander @ 2020-07-14 13:48 UTC (permalink / raw)
To: Quan, Evan, amd-gfx@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 2268 bytes --]
[AMD Public Use]
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Tuesday, July 14, 2020 2:55 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
[AMD Official Use Only - Internal Distribution Only]
Hi Alex,
Can I have a RB for this patch also?
BR
Evan
-----Original Message-----
From: Quan, Evan
Sent: Monday, July 13, 2020 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: RE: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Ping for this one and patch12, patch2 and patch3
BR
Evan
-----Original Message-----
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Friday, July 10, 2020 12:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Change-Id: I6f828da8de096ebc0ae27eaa89f988def2d547ec
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c2779d0b51f6..33e0718f2635 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1758,8 +1758,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
if (clk_id < 0)
return clk_id;
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, false);
if (max > 0) {
@@ -1779,8 +1778,7 @@ int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
}
out:
-if (clk_type == SMU_GFXCLK &&
- adev->asic_type == CHIP_SIENNA_CICHLID)
+if (clk_type == SMU_GFXCLK)
amdgpu_gfx_off_ctrl(adev, true);
return ret;
--
2.27.0
[-- Attachment #1.2: Type: text/html, Size: 3627 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-07-14 13:48 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-07-10 4:47 [PATCH 01/16] drm/amd/powerplay: add more members for dpm table Evan Quan
2020-07-10 4:47 ` [PATCH 02/16] drm/amd/powerplay: implement a common set dpm table API for smu V11 Evan Quan
2020-07-13 14:49 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 03/16] drm/amd/powerplay: update Arcturus default dpm table setting Evan Quan
2020-07-13 14:49 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 04/16] drm/amd/powerplay: update Navi10 default dpm table setup Evan Quan
2020-07-10 4:47 ` [PATCH 05/16] drm/amd/powerplay: update Sienna Cichlid " Evan Quan
2020-07-10 4:47 ` [PATCH 06/16] drm/amd/powerplay: add new UMD pstate data structure Evan Quan
2020-07-10 4:47 ` [PATCH 07/16] drm/amd/powerplay: update UMD pstate clock settings Evan Quan
2020-07-10 4:47 ` [PATCH 08/16] drm/amd/powerplay: update the common API for performance level setting Evan Quan
2020-07-10 4:47 ` [PATCH 09/16] drm/amd/powerplay: drop unnecessary Arcturus specific APIs Evan Quan
2020-07-10 4:47 ` [PATCH 10/16] drm/amd/powerplay: drop unnecessary Navi1x " Evan Quan
2020-07-10 4:47 ` [PATCH 11/16] drm/amd/powerplay: drop unnecessary Sienna Cichlid " Evan Quan
2020-07-10 4:47 ` [PATCH 12/16] drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range Evan Quan
2020-07-13 14:53 ` Alex Deucher
2020-07-10 4:47 ` [PATCH 13/16] drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs Evan Quan
2020-07-13 3:44 ` Quan, Evan
2020-07-14 6:55 ` Quan, Evan
2020-07-14 13:48 ` Deucher, Alexander
2020-07-10 4:47 ` [PATCH 14/16] drm/amd/powerplay: drop unnecessary wrappers Evan Quan
2020-07-10 4:47 ` [PATCH 15/16] drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper Evan Quan
2020-07-10 4:47 ` [PATCH 16/16] drm/amd/powerplay: drop unused APIs and parameters Evan Quan
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