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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Jacky Liao <ziyu.liao@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 09/17] drm/amd/display: Add I2C memory low power support
Date: Fri, 13 Nov 2020 15:56:37 -0500	[thread overview]
Message-ID: <20201113205645.640981-10-bindu.r@amd.com> (raw)
In-Reply-To: <20201113205645.640981-1-bindu.r@amd.com>

From: Jacky Liao <ziyu.liao@amd.com>

[Why]
The I2C memory blocks should be powered down when they are not in use.
This will reduce power consumption.

[How]
1. Write to I2C_LIGHT_SLEEP_FORCE to put memory in light sleep when
   released
2. Added a debug option to allow this behaviour to be turned off

Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h              |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c  | 12 ++++++++++++
 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h  | 16 ++++++++++++++++
 .../drm/amd/display/dc/dcn30/dcn30_resource.c    |  6 +++---
 4 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 52e819678ecd..e282c2211f42 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -419,6 +419,7 @@ struct dc_bw_validation_profile {
 
 union mem_low_power_enable_options {
 	struct {
+		bool i2c: 1;
 		bool mpc: 1;
 		bool optc: 1;
 	} bits;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 3e34afe8c504..7fbd92fbc63a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -293,6 +293,14 @@ static bool setup_engine(
 {
 	uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
 	uint32_t  reset_length = 0;
+
+        if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+	     if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL) {
+		     REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0);
+		     REG_WAIT(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, 0, 0, 5);
+		     }
+	     }
+
 	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
 
@@ -369,6 +377,10 @@ static void release_engine(
 	REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
 		DC_I2C_SW_USE_I2C_REG_REQ, 0);
 
+	if (dce_i2c_hw->ctx->dc->debug.enable_mem_low_power.bits.i2c) {
+		if (dce_i2c_hw->regs->DIO_MEM_PWR_CTRL)
+			REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
+	}
 }
 
 struct dce_i2c_hw *acquire_i2c_hw_engine(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index fb055e6883c0..2309f2bb162c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -95,6 +95,11 @@ enum {
 	SR(DC_I2C_DATA),\
 	SR(MICROSECOND_TIME_BASE_DIV)
 
+#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\
+	I2C_HW_ENGINE_COMMON_REG_LIST(id),\
+	SR(DIO_MEM_PWR_CTRL),\
+	SR(DIO_MEM_PWR_STATUS)
+
 #define I2C_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
 
@@ -179,6 +184,8 @@ struct dce_i2c_shift {
 	uint8_t XTAL_REF_DIV;
 	uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 	uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+	uint8_t I2C_LIGHT_SLEEP_FORCE;
+	uint8_t I2C_MEM_PWR_STATE;
 };
 
 struct dce_i2c_mask {
@@ -220,12 +227,19 @@ struct dce_i2c_mask {
 	uint32_t XTAL_REF_DIV;
 	uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
 	uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+	uint32_t I2C_LIGHT_SLEEP_FORCE;
+	uint32_t I2C_MEM_PWR_STATE;
 };
 
 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
 	I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
 
+#define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
+	I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\
+	I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
+	I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
+
 struct dce_i2c_registers {
 	uint32_t SETUP;
 	uint32_t SPEED;
@@ -239,6 +253,8 @@ struct dce_i2c_registers {
 	uint32_t DC_I2C_TRANSACTION3;
 	uint32_t DC_I2C_DATA;
 	uint32_t MICROSECOND_TIME_BASE_DIV;
+	uint32_t DIO_MEM_PWR_CTRL;
+	uint32_t DIO_MEM_PWR_STATUS;
 };
 
 enum dce_i2c_transaction_address_space {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index b379057e669c..eb067034ad45 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -933,7 +933,7 @@ static struct dce_aux *dcn30_aux_engine_create(
 	return &aux_engine->base;
 }
 
-#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 
 static const struct dce_i2c_registers i2c_hw_regs[] = {
 		i2c_inst_regs(1),
@@ -945,11 +945,11 @@ static const struct dce_i2c_registers i2c_hw_regs[] = {
 };
 
 static const struct dce_i2c_shift i2c_shifts = {
-		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 };
 
 static const struct dce_i2c_mask i2c_masks = {
-		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 };
 
 static struct dce_i2c_hw *dcn30_i2c_hw_create(
-- 
2.25.1

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  parent reply	other threads:[~2020-11-13 20:58 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 05/17] drm/amd/display: remove unused dml variables Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink Bindu Ramamurthy
2020-11-13 20:56 ` Bindu Ramamurthy [this message]
2020-11-13 20:56 ` [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 11/17] drm/amd/display: Add dual edp optimization flag Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
2020-12-16 22:43   ` Daniel Vetter
2020-11-13 20:56 ` [PATCH 14/17] drm/amd/display: correct data type Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 15/17] drm/amd/display: 3.2.112 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 17/17] drm/amd/display: update vgh bounding box Bindu Ramamurthy

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