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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Yongqiang Sun <yongqiang.sun@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 11/17] drm/amd/display: Add dual edp optimization flag.
Date: Fri, 13 Nov 2020 15:56:39 -0500	[thread overview]
Message-ID: <20201113205645.640981-12-bindu.r@amd.com> (raw)
In-Reply-To: <20201113205645.640981-1-bindu.r@amd.com>

From: Yongqiang Sun <yongqiang.sun@amd.com>

[Why & How]
Add a dual edp power optimization flag, so driver will
notify this flag to dmub FW to determine if apply the
power optimization.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c   | 1 +
 drivers/gpu/drm/amd/display/dc/dc_types.h       | 2 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c   | 1 +
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++-
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 165fd2f3c80b..f522b664d3c6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2757,6 +2757,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	 *  (Always set for DAL2, did not check ASIC)
 	 */
 	psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
+	psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
 
 	/* Complete PSR entry before aborting to prevent intermittent
 	 * freezes on certain eDPs
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 86406b42572c..80757a0ea7c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -697,6 +697,7 @@ struct psr_config {
 	bool psr_frame_capture_indication_req;
 	unsigned int psr_sdp_transmit_line_num_deadline;
 	bool allow_smu_optimizations;
+	bool allow_multi_disp_optimizations;
 };
 
 union dmcu_psr_level {
@@ -799,6 +800,7 @@ struct psr_context {
 	 */
 	unsigned int frame_delay;
 	bool allow_smu_optimizations;
+	bool allow_multi_disp_optimizations;
 };
 
 struct colorspace_transform {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 0d6fe7c29c20..17e84f34ceba 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -261,6 +261,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	// Misc
 	copy_settings_data->psr_level				= psr_context->psr_level.u32all;
 	copy_settings_data->smu_optimizations_en		= psr_context->allow_smu_optimizations;
+	copy_settings_data->multi_disp_optimizations_en	= psr_context->allow_multi_disp_optimizations;
 	copy_settings_data->frame_delay				= psr_context->frame_delay;
 	copy_settings_data->frame_cap_ind			= psr_context->psrFrameCaptureIndicationReq;
 	copy_settings_data->init_sdp_deadline			= psr_context->sdpTransmitLineNumDeadline;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9e6a4b4f2f1f 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -612,7 +612,8 @@ struct dmub_cmd_psr_copy_settings_data {
 	uint8_t smu_optimizations_en;
 	uint8_t frame_delay;
 	uint8_t frame_cap_ind;
-	uint8_t pad[3];
+	uint8_t pad[2];
+	uint8_t multi_disp_optimizations_en;
 	uint16_t init_sdp_deadline;
 	uint16_t pad2;
 };
-- 
2.25.1

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  parent reply	other threads:[~2020-11-13 20:58 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 05/17] drm/amd/display: remove unused dml variables Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 09/17] drm/amd/display: Add I2C memory low power support Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case Bindu Ramamurthy
2020-11-13 20:56 ` Bindu Ramamurthy [this message]
2020-11-13 20:56 ` [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
2020-12-16 22:43   ` Daniel Vetter
2020-11-13 20:56 ` [PATCH 14/17] drm/amd/display: correct data type Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 15/17] drm/amd/display: 3.2.112 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 17/17] drm/amd/display: update vgh bounding box Bindu Ramamurthy

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