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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Yongqiang Sun <yongqiang.sun@amd.com>,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 17/17] drm/amd/display: update vgh bounding box
Date: Fri, 13 Nov 2020 15:56:45 -0500	[thread overview]
Message-ID: <20201113205645.640981-18-bindu.r@amd.com> (raw)
In-Reply-To: <20201113205645.640981-1-bindu.r@amd.com>

From: Yongqiang Sun <yongqiang.sun@amd.com>

[Why & How]
Update bounding box as per spread sheet.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
---
 .../amd/display/dc/dcn301/dcn301_resource.c   | 60 +++++++++++++++----
 1 file changed, 47 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 8824dbce6f4a..0006d805b3b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -164,29 +164,63 @@ struct _vcs_dpi_ip_params_st dcn3_01_ip = {
 
 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
 	.clock_limits = {
-			/*TODO: fill out defaults once wm plociy is settled*/
 			{
 				.state = 0,
-				.dcfclk_mhz = 810.0,
-				.fabricclk_mhz = 1200.0,
+				.dram_speed_mts = 2400.0,
+				.fabricclk_mhz = 600,
+				.socclk_mhz = 278.0,
+				.dcfclk_mhz = 400.0,
+				.dscclk_mhz = 206.0,
+				.dppclk_mhz = 1015.0,
+				.dispclk_mhz = 1015.0,
+				.phyclk_mhz = 600.0,
+			},
+			{
+				.state = 1,
+				.dram_speed_mts = 2400.0,
+				.fabricclk_mhz = 688,
+				.socclk_mhz = 278.0,
+				.dcfclk_mhz = 400.0,
+				.dscclk_mhz = 206.0,
+				.dppclk_mhz = 1015.0,
 				.dispclk_mhz = 1015.0,
+				.phyclk_mhz = 600.0,
+			},
+			{
+				.state = 2,
+				.dram_speed_mts = 4267.0,
+				.fabricclk_mhz = 1067,
+				.socclk_mhz = 278.0,
+				.dcfclk_mhz = 608.0,
+				.dscclk_mhz = 296.0,
 				.dppclk_mhz = 1015.0,
+				.dispclk_mhz = 1015.0,
 				.phyclk_mhz = 810.0,
-				.socclk_mhz = 1000.0,
+			},
+
+			{
+				.state = 3,
+				.dram_speed_mts = 4267.0,
+				.fabricclk_mhz = 1067,
+				.socclk_mhz = 715.0,
+				.dcfclk_mhz = 676.0,
 				.dscclk_mhz = 338.0,
-				.dram_speed_mts = 4266.0,
+				.dppclk_mhz = 1015.0,
+				.dispclk_mhz = 1015.0,
+				.phyclk_mhz = 810.0,
 			},
+
 			{
-				.state = 1,
+				.state = 4,
+				.dram_speed_mts = 4267.0,
+				.fabricclk_mhz = 1067,
+				.socclk_mhz = 953.0,
 				.dcfclk_mhz = 810.0,
-				.fabricclk_mhz = 1200.0,
-				.dispclk_mhz = 1015.0,
+				.dscclk_mhz = 338.0,
 				.dppclk_mhz = 1015.0,
+				.dispclk_mhz = 1015.0,
 				.phyclk_mhz = 810.0,
-				.socclk_mhz = 1000.0,
-				.dscclk_mhz = 338.0,
-				.dram_speed_mts = 4266.0,
-			}
+			},
 		},
 
 	.sr_exit_time_us = 9.0,
@@ -226,7 +260,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
 	.xfc_bus_transport_time_us = 20,      // ?
 	.xfc_xbuf_latency_tolerance_us = 4,  // ?
 	.use_urgent_burst_bw = 1,            // ?
-	.num_states = 2,
+	.num_states = 5,
 	.do_urgent_latency_adjustment = false,
 	.urgent_latency_adjustment_fabric_clock_component_us = 0,
 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
-- 
2.25.1

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      parent reply	other threads:[~2020-11-13 20:58 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-13 20:56 [PATCH 00/17] DC Patches November 16, 2020 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 01/17] drm/amd/display: Program dpp dto based on actual dpp clk Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 02/17] drm/amd/display: Hook up PSR residency command to DSAT Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 03/17] drm/amd/display: Populate hostvm parameter before DML calculation Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 04/17] drm/amd/display: Handle Unknown Result for SMU Periodic Retraining on DCN2.1 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 05/17] drm/amd/display: remove unused dml variables Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 06/17] drm/amd/display: fix cursor calculation for 1xnY rotated display groups Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 07/17] drm/amd/display: minor restructuring of pbn calculation functions Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 08/17] drm/amd/display: Detect dynamic backlight support in eDP sink Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 09/17] drm/amd/display: Add I2C memory low power support Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 10/17] drm/amd/display: set dpp dto as per requested clk for lower case Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 11/17] drm/amd/display: Add dual edp optimization flag Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 12/17] drm/amd/display: [FW Promotion] Release 0.0.42 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 13/17] drm/amd/display: Expose new CRC window property Bindu Ramamurthy
2020-12-16 22:43   ` Daniel Vetter
2020-11-13 20:56 ` [PATCH 14/17] drm/amd/display: correct data type Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 15/17] drm/amd/display: 3.2.112 Bindu Ramamurthy
2020-11-13 20:56 ` [PATCH 16/17] drm/amd/display: Increase sr enter/exit in rn ddr4 watermark table Bindu Ramamurthy
2020-11-13 20:56 ` Bindu Ramamurthy [this message]

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