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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Aric Cyr <aric.cyr@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Aurabindo.Pillai@amd.com, Bhawanpreet.Lakha@amd.com,
	bindu.r@amd.com
Subject: [PATCH 09/14] drm/amd/display: Multi-display underflow observed
Date: Fri, 18 Dec 2020 17:28:59 -0500	[thread overview]
Message-ID: <20201218222904.393785-10-bindu.r@amd.com> (raw)
In-Reply-To: <20201218222904.393785-1-bindu.r@amd.com>

From: Aric Cyr <aric.cyr@amd.com>

[Why]
FP2 programming not happening when topology changes occur with multiple
displays.

[How]
Ensure FP2 is programmed whenever global sync changes occur but wait for
VACTIVE first to avoid underflow.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c      | 20 -------------------
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 12 ++++++++---
 2 files changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 7339d9855ec8..58eb0d69873a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2625,26 +2625,6 @@ static void commit_planes_for_stream(struct dc *dc,
 		}
 	}
 
-	if (update_type != UPDATE_TYPE_FAST) {
-		// If changing VTG FP2: wait until back in vactive to program FP2
-		// Need to ensure that pipe unlock happens soon after to minimize race condition
-		for (i = 0; i < dc->res_pool->pipe_count; i++) {
-			struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
-			if (pipe_ctx->top_pipe || pipe_ctx->stream != stream)
-				continue;
-
-			if (!pipe_ctx->update_flags.bits.global_sync)
-				continue;
-
-			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
-			pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
-
-			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
-					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
-		}
-	}
-
 	if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
 		dc->hwss.interdependent_update_lock(dc, context, false);
 	else
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 31a477194d3b..cb822df21b7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1586,7 +1586,10 @@ static void dcn20_program_pipe(
 			&& !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
 		hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
 
-	if (pipe_ctx->update_flags.bits.global_sync) {
+	/* Only update TG on top pipe */
+	if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe
+			&& !pipe_ctx->prev_odm_pipe) {
+
 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
 				pipe_ctx->stream_res.tg,
 				pipe_ctx->pipe_dlg_param.vready_offset,
@@ -1594,8 +1597,11 @@ static void dcn20_program_pipe(
 				pipe_ctx->pipe_dlg_param.vupdate_offset,
 				pipe_ctx->pipe_dlg_param.vupdate_width);
 
+		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK);
+		pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE);
+
 		pipe_ctx->stream_res.tg->funcs->set_vtg_params(
-				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false);
+				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true);
 
 		if (hws->funcs.setup_vupdate_interrupt)
 			hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
@@ -2570,4 +2576,4 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
 {
 	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
 			color_space, color_depth, solid_color, width, height, offset);
-}
\ No newline at end of file
+}
-- 
2.25.1

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  parent reply	other threads:[~2020-12-18 22:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-18 22:28 [PATCH 00/14] DC Patches December 21, 2020 Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 01/14] drm/amd/display: handler not correctly checked at remove_irq_handler Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 02/14] drm/amd/display: Interfaces for hubp blank and soft reset Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 03/14] drm/amd/display: Modify the hdcp device count check condition Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 04/14] drm/amd/display: To modify the condition in indicating branch device Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 05/14] drm/amd/display: gradually ramp ABM intensity Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 06/14] drm/amd/display: change SMU repsonse timeout to 2s Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 07/14] drm/amd/display: Update RN/VGH active display count workaround Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 08/14] drm/amd/display: Remove unnecessary NULL check Bindu Ramamurthy
2020-12-18 22:28 ` Bindu Ramamurthy [this message]
2020-12-18 22:29 ` [PATCH 10/14] drm/amd/display: Acquire DSC during split stream for ODM only if top_pipe Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 11/14] drm/amd/display: updated wm table for Renoir Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 12/14] drm/amd/display: [FW Promotion] Release 0.0.47 Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 13/14] drm/amd/display: always program DPPDTO unless not safe to lower Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 14/14] drm/amd/display: add getter routine to retrieve mpcc mux Bindu Ramamurthy

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