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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Josip Pavic <Josip.Pavic@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Aurabindo.Pillai@amd.com, Bhawanpreet.Lakha@amd.com,
	bindu.r@amd.com
Subject: [PATCH 14/14] drm/amd/display: add getter routine to retrieve mpcc mux
Date: Fri, 18 Dec 2020 17:29:04 -0500	[thread overview]
Message-ID: <20201218222904.393785-15-bindu.r@amd.com> (raw)
In-Reply-To: <20201218222904.393785-1-bindu.r@amd.com>

From: Josip Pavic <Josip.Pavic@amd.com>

[Why & How]
Add function to identify which MPCC is providing input to a specified OPP

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 12 ++++++++++++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h |  1 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c |  1 +
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c |  1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h      |  4 ++++
 5 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 3fcd408e9103..a46cb20596fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -467,6 +467,17 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock)
 	REG_SET(CUR[opp_id], 0, CUR_VUPDATE_LOCK_SET, lock ? 1 : 0);
 }
 
+unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
+{
+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
+	uint32_t val;
+
+	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
+		REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);
+
+	return val;
+}
+
 static const struct mpc_funcs dcn10_mpc_funcs = {
 	.read_mpcc_state = mpc1_read_mpcc_state,
 	.insert_plane = mpc1_insert_plane,
@@ -483,6 +494,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
 	.set_denorm_clamp = NULL,
 	.set_output_csc = NULL,
 	.set_output_gamma = NULL,
+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index 66a4719c22a0..dbfffc6383dc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -200,4 +200,5 @@ void mpc1_read_mpcc_state(
 
 void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
 
+unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 99cc095dc33c..6a99fdd55e8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -556,6 +556,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
 	.set_ocsc_default = mpc2_set_ocsc_default,
 	.set_output_gamma = mpc2_set_output_gamma,
 	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
 };
 
 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index d7d053fc6e91..3e6f76096119 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -1428,6 +1428,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
 	.program_3dlut = mpc3_program_3dlut,
 	.release_rmu = mpcc3_release_rmu,
 	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
+	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
 
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 879f502ae530..75c77ad9cbfe 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -359,6 +359,10 @@ struct mpc_funcs {
 
 	int (*release_rmu)(struct mpc *mpc, int mpcc_id);
 
+	unsigned int (*get_mpc_out_mux)(
+			struct mpc *mpc,
+			int opp_id);
+
 };
 
 #endif
-- 
2.25.1

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      parent reply	other threads:[~2020-12-18 22:30 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-18 22:28 [PATCH 00/14] DC Patches December 21, 2020 Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 01/14] drm/amd/display: handler not correctly checked at remove_irq_handler Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 02/14] drm/amd/display: Interfaces for hubp blank and soft reset Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 03/14] drm/amd/display: Modify the hdcp device count check condition Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 04/14] drm/amd/display: To modify the condition in indicating branch device Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 05/14] drm/amd/display: gradually ramp ABM intensity Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 06/14] drm/amd/display: change SMU repsonse timeout to 2s Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 07/14] drm/amd/display: Update RN/VGH active display count workaround Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 08/14] drm/amd/display: Remove unnecessary NULL check Bindu Ramamurthy
2020-12-18 22:28 ` [PATCH 09/14] drm/amd/display: Multi-display underflow observed Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 10/14] drm/amd/display: Acquire DSC during split stream for ODM only if top_pipe Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 11/14] drm/amd/display: updated wm table for Renoir Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 12/14] drm/amd/display: [FW Promotion] Release 0.0.47 Bindu Ramamurthy
2020-12-18 22:29 ` [PATCH 13/14] drm/amd/display: always program DPPDTO unless not safe to lower Bindu Ramamurthy
2020-12-18 22:29 ` Bindu Ramamurthy [this message]

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