From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Aric Cyr <Aric.Cyr@amd.com>,
Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
roman.li@amd.com, Aurabindo.Pillai@amd.com,
Jun Lei <jun.lei@amd.com>,
Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 12/21] drm/amd/display: implement T12 compliance
Date: Fri, 8 Jan 2021 16:49:58 -0500 [thread overview]
Message-ID: <20210108215007.851249-13-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20210108215007.851249-1-Rodrigo.Siqueira@amd.com>
From: Jun Lei <jun.lei@amd.com>
[why]
When OS reboots, and panel is turned off, T12 may not be maintained.
T12 is defined as the interval between VDDC off (occurs at shutdown) and
the next VDDC on (occurs when eDP is POST-ed)
[how]
DC already tracks panel power off time. Add a DC interface which DM can
call during shutdown. Ideally this should be as late as possible during
the shutdown sequence so the extra delay is minimal.
Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +++++++
drivers/gpu/drm/amd/display/dc/dc_link.h | 7 +++++
.../display/dc/dce110/dce110_hw_sequencer.c | 31 +++++++++++++++++++
.../amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 ++
.../gpu/drm/amd/display/dc/dcn30/dcn30_init.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 1 +
6 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 59ef1eacc6e1..4f58a5c43548 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -203,6 +203,17 @@ static bool program_hpd_filter(const struct dc_link *link)
return result;
}
+bool dc_link_wait_for_t12(struct dc_link *link)
+{
+ if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
+ link->dc->hwss.edp_wait_for_T12(link);
+
+ return true;
+ }
+
+ return false;
+}
+
/**
* dc_link_detect_sink() - Determine if there is a sink connected
*
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index d8d659b2bc34..d5d8f0ad9233 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -259,6 +259,13 @@ enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link);
bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss);
+/*
+ * On eDP links this function call will stall until T12 has elapsed.
+ * If the panel is not in power off state, this function will return
+ * immediately.
+ */
+bool dc_link_wait_for_t12(struct dc_link *link);
+
enum dc_status read_hpd_rx_irq_data(
struct dc_link *link,
union hpd_irq_data *irq_data);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4c230f1de9a3..3e9abb1b8e14 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -921,6 +921,37 @@ void dce110_edp_power_control(
}
}
+void dce110_edp_wait_for_T12(
+ struct dc_link *link)
+{
+ struct dc_context *ctx = link->ctx;
+
+ if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
+ != CONNECTOR_ID_EDP) {
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+
+ if (!link->panel_cntl)
+ return;
+
+ if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
+ link->link_trace.time_stamp.edp_poweroff != 0) {
+ unsigned int t12_duration = 500; // Default T12 as per spec
+ unsigned long long current_ts = dm_get_timestamp(ctx);
+ unsigned long long time_since_edp_poweroff_ms =
+ div64_u64(dm_get_elapse_time_in_ns(
+ ctx,
+ current_ts,
+ link->link_trace.time_stamp.edp_poweroff), 1000000);
+
+ t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
+
+ if (time_since_edp_poweroff_ms < t12_duration)
+ msleep(t12_duration - time_since_edp_poweroff_ms);
+ }
+}
+
/*todo: cloned in stream enc, fix*/
/*
* @brief
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index e5691e499023..dee8ad1ebaa4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -163,6 +163,8 @@ void dcn10_wait_for_mpcc_disconnect(
void dce110_edp_backlight_control(
struct dc_link *link,
bool enable);
+void dce110_edp_wait_for_T12(
+ struct dc_link *link);
void dce110_edp_power_control(
struct dc_link *link,
bool power_up);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 87c74aa84406..c4c14e9c1309 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -71,6 +71,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
.edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+ .edp_wait_for_T12 = dce110_edp_wait_for_T12,
.set_cursor_position = dcn10_set_cursor_position,
.set_cursor_attribute = dcn10_set_cursor_attribute,
.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 7b12ffcdd4ec..7a19ff5d4214 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -54,6 +54,7 @@ struct hw_sequencer_funcs {
/* Embedded Display Related */
void (*edp_power_control)(struct dc_link *link, bool enable);
void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up);
+ void (*edp_wait_for_T12)(struct dc_link *link);
/* Pipe Programming Related */
void (*init_hw)(struct dc *dc);
--
2.25.1
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next prev parent reply other threads:[~2021-01-08 21:50 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-08 21:49 [PATCH 00/21] DC Patches January 08, 2021 Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 01/21] drm/amd/display: 3.2.117 Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 02/21] drm/amd/display: NULL pointer hang Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 03/21] drm/amd/display: Initialize stack variable Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 04/21] drm/amd/display: Separate fec debug flag and monitor patch Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 05/21] drm/amd/display: HUBP_IN_BLANK for DCN30 Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 06/21] drm/amd/display: Remove HUBP_DISABLE from default Rodrigo Siqueira
2021-01-10 23:12 ` Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 07/21] drm/amd/display: Unblank hubp based on plane visibility Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 08/21] drm/amd/display: New path for enabling DPG Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 09/21] drm/amd/display: removed unnecessary check when dpp clock increasing Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 10/21] drm/amd/display: doesn't reprogram AMD OUI Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 11/21] drm/amd/display: Remove unused P010 debug flag Rodrigo Siqueira
2021-01-08 21:49 ` Rodrigo Siqueira [this message]
2021-01-08 21:49 ` [PATCH 13/21] drm/amd/display: fix seamless boot stream adding algorithm Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 14/21] drm/amd/display: Fix assert being hit with GAMCOR memory shut down Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 15/21] drm/amd/display: New sequence for HUBP blank Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 16/21] drm/amd/display: enable HUBP blank behaviour Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 17/21] drm/amd/display: Add a missing DCN3.01 API mapping Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 18/21] drm/amd/display: 3.2.118 Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 19/21] drm/amd/display: Revert patch causing black screen Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 20/21] drm/amd/display: disable dcn10 pipe split by default Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 21/21] drm/amd/display: change SMU repsonse timeout to 2s Rodrigo Siqueira
2021-01-08 22:12 ` [PATCH 00/21] DC Patches January 08, 2021 Rodrigo Siqueira
2021-01-08 22:52 ` Wheeler, Daniel
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