AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Aric Cyr <Aric.Cyr@amd.com>,
	Wesley Chalmers <Wesley.Chalmers@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 06/21] drm/amd/display: Remove HUBP_DISABLE from default
Date: Fri,  8 Jan 2021 16:49:52 -0500	[thread overview]
Message-ID: <20210108215007.851249-7-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20210108215007.851249-1-Rodrigo.Siqueira@amd.com>

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
HW team plans to rename HUBP_DISABLE to HUBP_SOFT_RESET in future HW
revisions. Those future revisions should not inherit the HUBP_DISABLE
name.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h |  2 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 22 ++++++++++++++-----
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index a9a6ed7f4f99..80794fed6e20 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -450,7 +450,6 @@
 
 #define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
 	type HUBP_BLANK_EN;\
-	type HUBP_DISABLE;\
 	type HUBP_TTU_DISABLE;\
 	type HUBP_NO_OUTSTANDING_REQ;\
 	type HUBP_VTG_SEL;\
@@ -644,6 +643,7 @@
 
 #define DCN_HUBP_REG_FIELD_LIST(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
+	type HUBP_DISABLE;\
 	type ALPHA_PLANE_EN
 
 struct dcn_mi_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index f501c02c244b..98ec1f9171b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -161,7 +161,7 @@
 	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
 	uint32_t DCN_DMDATA_VM_CNTL
 
-#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
 	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
 	type DMDATA_ADDRESS_HIGH;\
 	type DMDATA_MODE;\
@@ -186,8 +186,12 @@
 	type SURFACE_TRIPLE_BUFFER_ENABLE;\
 	type VMID
 
-#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
-	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+#define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type); \
+	type HUBP_DISABLE
+
+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
+	DCN2_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
 	type REFCYC_PER_VM_GROUP_FLIP;\
 	type REFCYC_PER_VM_REQ_FLIP;\
 	type REFCYC_PER_VM_GROUP_VBLANK;\
@@ -196,8 +200,12 @@
 	type REFCYC_PER_META_CHUNK_FLIP_C; \
 	type VM_GROUP_SIZE
 
-#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
-	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
+	type HUBP_DISABLE
+
+#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type) \
+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
 	type PRIMARY_SURFACE_DCC_IND_BLK;\
 	type SECONDARY_SURFACE_DCC_IND_BLK;\
 	type PRIMARY_SURFACE_DCC_IND_BLK_C;\
@@ -216,6 +224,10 @@
 	type ROW_TTU_MODE; \
 	type NUM_PKRS
 
+#define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN30_HUBP_REG_FIELD_VARIABLE_LIST_COMMON(type);\
+	type HUBP_DISABLE
+
 struct dcn_hubp2_registers {
 	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
 };
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2021-01-08 21:50 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-08 21:49 [PATCH 00/21] DC Patches January 08, 2021 Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 01/21] drm/amd/display: 3.2.117 Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 02/21] drm/amd/display: NULL pointer hang Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 03/21] drm/amd/display: Initialize stack variable Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 04/21] drm/amd/display: Separate fec debug flag and monitor patch Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 05/21] drm/amd/display: HUBP_IN_BLANK for DCN30 Rodrigo Siqueira
2021-01-08 21:49 ` Rodrigo Siqueira [this message]
2021-01-10 23:12   ` [PATCH 06/21] drm/amd/display: Remove HUBP_DISABLE from default Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 07/21] drm/amd/display: Unblank hubp based on plane visibility Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 08/21] drm/amd/display: New path for enabling DPG Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 09/21] drm/amd/display: removed unnecessary check when dpp clock increasing Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 10/21] drm/amd/display: doesn't reprogram AMD OUI Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 11/21] drm/amd/display: Remove unused P010 debug flag Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 12/21] drm/amd/display: implement T12 compliance Rodrigo Siqueira
2021-01-08 21:49 ` [PATCH 13/21] drm/amd/display: fix seamless boot stream adding algorithm Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 14/21] drm/amd/display: Fix assert being hit with GAMCOR memory shut down Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 15/21] drm/amd/display: New sequence for HUBP blank Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 16/21] drm/amd/display: enable HUBP blank behaviour Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 17/21] drm/amd/display: Add a missing DCN3.01 API mapping Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 18/21] drm/amd/display: 3.2.118 Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 19/21] drm/amd/display: Revert patch causing black screen Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 20/21] drm/amd/display: disable dcn10 pipe split by default Rodrigo Siqueira
2021-01-08 21:50 ` [PATCH 21/21] drm/amd/display: change SMU repsonse timeout to 2s Rodrigo Siqueira
2021-01-08 22:12 ` [PATCH 00/21] DC Patches January 08, 2021 Rodrigo Siqueira
2021-01-08 22:52   ` Wheeler, Daniel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210108215007.851249-7-Rodrigo.Siqueira@amd.com \
    --to=rodrigo.siqueira@amd.com \
    --cc=Aric.Cyr@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Eryk.Brol@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=Wesley.Chalmers@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=bindu.r@amd.com \
    --cc=qingqing.zhuo@amd.com \
    --cc=roman.li@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox