From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 38/66] drm/amdgpu/sdma4.0: convert to IP version checking
Date: Tue, 21 Sep 2021 14:06:57 -0400 [thread overview]
Message-ID: <20210921180725.1985552-39-alexander.deucher@amd.com> (raw)
In-Reply-To: <20210921180725.1985552-1-alexander.deucher@amd.com>
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 107 ++++++++++++++-----------
1 file changed, 60 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 8931000dcd41..3219dca3e44f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -469,8 +469,8 @@ static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_4,
ARRAY_SIZE(golden_settings_sdma_4));
@@ -478,7 +478,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_vg10,
ARRAY_SIZE(golden_settings_sdma_vg10));
break;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
soc15_program_register_sequence(adev,
golden_settings_sdma_4,
ARRAY_SIZE(golden_settings_sdma_4));
@@ -486,7 +486,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_vg12,
ARRAY_SIZE(golden_settings_sdma_vg12));
break;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma0_4_2_init,
ARRAY_SIZE(golden_settings_sdma0_4_2_init));
@@ -497,17 +497,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma1_4_2,
ARRAY_SIZE(golden_settings_sdma1_4_2));
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(4, 2, 2):
soc15_program_register_sequence(adev,
golden_settings_sdma_arct,
ARRAY_SIZE(golden_settings_sdma_arct));
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
soc15_program_register_sequence(adev,
golden_settings_sdma_aldebaran,
ARRAY_SIZE(golden_settings_sdma_aldebaran));
break;
- case CHIP_RAVEN:
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
soc15_program_register_sequence(adev,
golden_settings_sdma_4_1,
ARRAY_SIZE(golden_settings_sdma_4_1));
@@ -520,7 +521,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_sdma_rv1,
ARRAY_SIZE(golden_settings_sdma_rv1));
break;
- case CHIP_RENOIR:
+ case IP_VERSION(4, 1, 2):
soc15_program_register_sequence(adev,
golden_settings_sdma_4_3,
ARRAY_SIZE(golden_settings_sdma_4_3));
@@ -538,12 +539,12 @@ static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
* The only chips with SDMAv4 and ULV are VG10 and VG20.
* Server SKUs take a different hysteresis setting from other SKUs.
*/
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
if (adev->pdev->device == 0x6860)
break;
return;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
if (adev->pdev->device == 0x66a1)
break;
return;
@@ -589,8 +590,8 @@ static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
/* arcturus shares the same FW memory across
all SDMA isntances */
- if (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_ALDEBARAN)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0))
break;
}
@@ -620,17 +621,18 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
DRM_DEBUG("\n");
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
chip_name = "vega10";
break;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
chip_name = "vega12";
break;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
chip_name = "vega20";
break;
- case CHIP_RAVEN:
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
chip_name = "raven2";
else if (adev->apu_flags & AMD_APU_IS_PICASSO)
@@ -638,16 +640,16 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
else
chip_name = "raven";
break;
- case CHIP_ARCTURUS:
+ case IP_VERSION(4, 2, 2):
chip_name = "arcturus";
break;
- case CHIP_RENOIR:
+ case IP_VERSION(4, 1, 2):
if (adev->apu_flags & AMD_APU_IS_RENOIR)
chip_name = "renoir";
else
chip_name = "green_sardine";
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
chip_name = "aldebaran";
break;
default:
@@ -665,8 +667,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
goto out;
for (i = 1; i < adev->sdma.num_instances; i++) {
- if (adev->asic_type == CHIP_ARCTURUS ||
- adev->asic_type == CHIP_ALDEBARAN) {
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) ||
+ adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 4, 0)) {
/* Acturus & Aldebaran will leverage the same FW memory
for every SDMA instance */
memcpy((void *)&adev->sdma.instance[i],
@@ -1106,7 +1108,7 @@ static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
* Arcturus for the moment and firmware version 14
* and above.
*/
- if (adev->asic_type == CHIP_ARCTURUS &&
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) &&
adev->sdma.instance[i].fw_version >= 14)
WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
/* Extend page fault timeout to avoid interrupt storm */
@@ -1393,9 +1395,10 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
return;
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
sdma_v4_1_init_power_gating(adev);
sdma_v4_1_update_power_gating(adev, true);
break;
@@ -1835,13 +1838,13 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
{
uint fw_version = adev->sdma.instance[0].fw_version;
- switch (adev->asic_type) {
- case CHIP_VEGA10:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 0, 0):
return fw_version >= 430;
- case CHIP_VEGA12:
+ case IP_VERSION(4, 0, 1):
/*return fw_version >= 31;*/
return false;
- case CHIP_VEGA20:
+ case IP_VERSION(4, 2, 0):
return fw_version >= 123;
default:
return false;
@@ -1853,14 +1856,22 @@ static int sdma_v4_0_early_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
- if (adev->flags & AMD_IS_APU)
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
adev->sdma.num_instances = 1;
- else if (adev->asic_type == CHIP_ARCTURUS)
+ break;
+ case IP_VERSION(4, 2, 2):
adev->sdma.num_instances = 8;
- else if (adev->asic_type == CHIP_ALDEBARAN)
+ break;
+ case IP_VERSION(4, 4, 0):
adev->sdma.num_instances = 5;
- else
+ break;
+ default:
adev->sdma.num_instances = 2;
+ break;
+ }
r = sdma_v4_0_init_microcode(adev);
if (r) {
@@ -1869,7 +1880,8 @@ static int sdma_v4_0_early_init(void *handle)
}
/* TODO: Page queue breaks driver reload under SRIOV */
- if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
+ if ((adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 0, 0)) &&
+ amdgpu_sriov_vf((adev)))
adev->sdma.has_page_queue = false;
else if (sdma_v4_0_fw_support_paging_queue(adev))
adev->sdma.has_page_queue = true;
@@ -2141,14 +2153,14 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
amdgpu_fence_process(&adev->sdma.instance[instance].ring);
break;
case 1:
- if (adev->asic_type == CHIP_VEGA20)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
case 2:
/* XXX compute */
break;
case 3:
- if (adev->asic_type != CHIP_VEGA20)
+ if (adev->ip_versions[SDMA0_HWIP] != IP_VERSION(4, 2, 0))
amdgpu_fence_process(&adev->sdma.instance[instance].page);
break;
}
@@ -2364,9 +2376,10 @@ static int sdma_v4_0_set_powergating_state(void *handle,
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- switch (adev->asic_type) {
- case CHIP_RAVEN:
- case CHIP_RENOIR:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 1, 0):
+ case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 1, 2):
sdma_v4_1_update_power_gating(adev,
state == AMD_PG_STATE_GATE);
break;
@@ -2551,7 +2564,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].ring.funcs =
&sdma_v4_0_ring_funcs_2nd_mmhub;
else
@@ -2559,7 +2572,7 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
&sdma_v4_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
if (adev->sdma.has_page_queue) {
- if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
+ if (adev->ip_versions[SDMA0_HWIP] == IP_VERSION(4, 2, 2) && i >= 5)
adev->sdma.instance[i].page.funcs =
&sdma_v4_0_page_ring_funcs_2nd_mmhub;
else
@@ -2786,12 +2799,12 @@ static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
{
- switch (adev->asic_type) {
- case CHIP_VEGA20:
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[SDMA0_HWIP]) {
+ case IP_VERSION(4, 2, 0):
+ case IP_VERSION(4, 2, 2):
adev->sdma.funcs = &sdma_v4_0_ras_funcs;
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(4, 4, 0):
adev->sdma.funcs = &sdma_v4_4_ras_funcs;
break;
default:
--
2.31.1
next prev parent reply other threads:[~2021-09-21 18:08 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
2021-09-21 18:06 ` [PATCH 01/66] drm/amdgpu: move headless sku check into harvest function Alex Deucher
2021-09-21 18:06 ` [PATCH 02/66] drm/amdgpu: add debugfs access to the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 03/66] drm/amdgpu: store HW IP versions in the driver structure Alex Deucher
2021-09-21 18:06 ` [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table Alex Deucher
2021-09-22 16:58 ` Felix Kuehling
2021-09-22 20:43 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 05/66] drm/amdgpu: add XGMI HWIP Alex Deucher
2021-09-21 18:06 ` [PATCH 06/66] drm/amdgpu/nv: export common IP functions Alex Deucher
2021-09-21 18:06 ` [PATCH 07/66] drm/amdgpu: add initial IP enumeration via IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 08/66] drm/amdgpu/sdma5.0: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 09/66] drm/amdgpu/sdma5.2: " Alex Deucher
2021-09-22 5:55 ` Lazar, Lijo
2021-09-22 6:08 ` Chen, Guchun
2021-09-22 9:18 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 10/66] drm/amdgpu/gfx10: " Alex Deucher
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
2021-09-22 4:41 ` Lazar, Lijo
2021-09-22 15:19 ` Deucher, Alexander
2021-09-22 16:16 ` Felix Kuehling
2021-09-22 17:07 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 12/66] drm/amdgpu: bind to any 0x1002 PCI diplay class device Alex Deucher
2021-09-21 18:06 ` [PATCH 13/66] drm/amdgpu/gmc10.0: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 14/66] drm/amdgpu: Use IP discovery to drive setting IP blocks by default Alex Deucher
2021-09-21 18:06 ` [PATCH 15/66] drm/amdgpu: drive nav10 from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 16/66] drm/amdgpu/gfxhub2.1: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 17/66] drm/amdgpu/mmhub2.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 18/66] drm/amdgpu/mmhub2.1: " Alex Deucher
2021-09-21 18:06 ` [PATCH 19/66] drm/amdgpu/vcn3.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 20/66] drm/amdgpu/athub2.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 21/66] drm/amdgpu/athub2.1: " Alex Deucher
2021-09-21 18:06 ` [PATCH 22/66] drm/amdgpu/navi10_ih: " Alex Deucher
2021-09-21 18:06 ` [PATCH 23/66] drm/amdgpu/amdgpu_smu: " Alex Deucher
2021-09-22 7:32 ` Lazar, Lijo
2021-09-22 15:40 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 24/66] drm/amdgpu/smu11.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 25/66] drm/amdgpu/navi10_ppt: " Alex Deucher
2021-09-21 18:06 ` [PATCH 26/66] drm/amdgpu/sienna_cichlid_ppt: " Alex Deucher
2021-09-21 18:06 ` [PATCH 27/66] drm/amdgpu: drive all navi asics from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking Alex Deucher
2021-09-22 7:31 ` Lazar, Lijo
2021-09-22 15:21 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 29/66] drm/amdgpu/display/dm: " Alex Deucher
2021-09-22 7:37 ` Lazar, Lijo
2021-09-22 15:53 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 30/66] drm/amdgpu: add DCI HWIP Alex Deucher
2021-09-23 15:43 ` Harry Wentland
2021-09-24 19:58 ` Alex Deucher
2021-09-24 20:40 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 31/66] drm/amdgpu: make soc15_common_ip_funcs static Alex Deucher
2021-09-21 18:06 ` [PATCH 32/66] drm/amdgpu/soc15: export common IP functions Alex Deucher
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
2021-09-22 7:48 ` Lazar, Lijo
2021-09-22 7:54 ` Lazar, Lijo
2021-09-22 15:58 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 34/66] drm/amdgpu/soc15: get rev_id in soc15_common_early_init Alex Deucher
2021-09-21 18:06 ` [PATCH 35/66] drm/amdgpu: drive all vega asics from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support Alex Deucher
2021-09-23 15:58 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 37/66] drm/amdgpu/display/dm: convert RAVEN to IP version checking Alex Deucher
2021-09-21 18:06 ` Alex Deucher [this message]
2021-09-21 18:06 ` [PATCH 39/66] drm/amdgpu/hdp4.0: convert " Alex Deucher
2021-09-21 18:06 ` [PATCH 40/66] drm/amdgpu/gfx9.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 41/66] drm/amdgpu/amdgpu_psp: " Alex Deucher
2021-09-21 18:07 ` [PATCH 42/66] drm/amdgpu/psp_v11.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 43/66] drm/amdgpu/psp_v13.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 44/66] drm/amdgpu/pm/smu_v11.0: update " Alex Deucher
2021-09-21 18:07 ` [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert " Alex Deucher
2021-09-22 8:18 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more " Alex Deucher
2021-09-22 8:16 ` Lazar, Lijo
2021-09-22 16:06 ` Deucher, Alexander
2021-09-21 18:07 ` [PATCH 47/66] drm/amdgpu/amdgpu_vcn: convert to " Alex Deucher
2021-09-21 18:07 ` [PATCH 48/66] drm/amdgpu/vcn2.5: " Alex Deucher
2021-09-21 18:07 ` [PATCH 49/66] drm/amdgpu/soc15: " Alex Deucher
2021-09-21 18:07 ` [PATCH 50/66] drm/amd/display: fix error case handling Alex Deucher
2021-09-21 18:07 ` [PATCH 51/66] drm/amdgpu: add VCN1 hardware IP Alex Deucher
2021-09-21 18:07 ` [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table Alex Deucher
2021-09-22 8:36 ` Lazar, Lijo
2021-09-22 8:45 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 53/66] drm/amdgpu: add HWID of SDMA instance 2 and 3 Alex Deucher
2021-09-21 18:07 ` [PATCH 54/66] drm/amdgpu: get VCN and SDMA instances from IP discovery table Alex Deucher
2021-09-21 18:07 ` [PATCH 55/66] drm/amdgpu/sdma: remove manual instance setting Alex Deucher
2021-09-21 18:07 ` [PATCH 56/66] drm/amdgpu/vcn: " Alex Deucher
2021-09-21 18:07 ` [PATCH 57/66] drm/amdgpu: get VCN harvest information from IP discovery table Alex Deucher
2021-09-21 18:07 ` [PATCH 58/66] drm/amdgpu/ucode: add default behavior Alex Deucher
2021-09-21 18:07 ` [PATCH 59/66] drm/amdgpu: add new asic_type for IP discovery Alex Deucher
2021-09-21 18:07 ` [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default Alex Deucher
2021-09-23 6:47 ` Lazar, Lijo
2021-09-23 21:46 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 61/66] drm/amdgpu: convert IP version array to include instances Alex Deucher
2021-09-22 9:08 ` Lazar, Lijo
2021-09-22 16:17 ` Alex Deucher
2021-09-23 4:58 ` Lazar, Lijo
2021-09-23 21:42 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 62/66] drm/amdgpu: clean up set IP function Alex Deucher
2021-09-21 18:07 ` [PATCH 63/66] drm/amdgpu: add support for SRIOV in IP discovery path Alex Deucher
2021-09-21 18:07 ` [PATCH 64/66] drm/amdkfd: clean up parameters in kgd2kfd_probe Alex Deucher
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
2021-09-21 21:00 ` ernstp
2021-09-22 1:44 ` Alex Deucher
2021-09-22 16:55 ` Felix Kuehling
2021-09-21 18:07 ` [PATCH 66/66] drm/amdgpu: add an option to override IP discovery table from a file Alex Deucher
2021-09-22 7:54 ` [PATCH 00/66] Move to IP driven device enumeration Christian König
2021-09-22 20:25 ` Alex Deucher
2021-09-23 6:43 ` Christian König
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210921180725.1985552-39-alexander.deucher@amd.com \
--to=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox