From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 62/66] drm/amdgpu: clean up set IP function
Date: Tue, 21 Sep 2021 14:07:21 -0400 [thread overview]
Message-ID: <20210921180725.1985552-63-alexander.deucher@amd.com> (raw)
In-Reply-To: <20210921180725.1985552-1-alexander.deucher@amd.com>
Split into several smaller per IP functions to make it
easier to handle ordering issues for things like
SR-IOV in a follow up patch.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1028 +++++++++--------
1 file changed, 540 insertions(+), 488 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index eff348dee9e9..44ab3d6739e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -517,336 +517,218 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
return 0;
}
-int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
+static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
{
- int r;
-
- switch (adev->asic_type) {
- case CHIP_VEGA10:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
- break;
- case CHIP_VEGA12:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
- break;
- case CHIP_RAVEN:
- vega10_reg_base_init(adev);
- adev->sdma.num_instances = 1;
- adev->vcn.num_vcn_inst = 1;
- if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
- adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
- } else {
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
- adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
- }
- break;
- case CHIP_VEGA20:
- vega20_reg_base_init(adev);
- adev->sdma.num_instances = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
- adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
- adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
- break;
- case CHIP_ARCTURUS:
- arct_reg_base_init(adev);
- adev->sdma.num_instances = 8;
- adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
- break;
- case CHIP_ALDEBARAN:
- aldebaran_reg_base_init(adev);
- adev->sdma.num_instances = 5;
- adev->vcn.num_vcn_inst = 2;
- adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
- adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
- adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
- adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
- adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
- adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
- adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
- adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
- break;
- default:
- r = amdgpu_discovery_reg_base_init(adev);
- if (r)
- return -EINVAL;
-
- amdgpu_discovery_harvest_ip(adev);
-
- if (!adev->mman.discovery_bin) {
- DRM_ERROR("ip discovery uninitialized\n");
- return -EINVAL;
- }
- break;
- }
-
+ /* what IP to use for this? */
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- adev->family = AMDGPU_FAMILY_AI;
- break;
- case IP_VERSION(9, 1, 0):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
- adev->family = AMDGPU_FAMILY_RV;
+ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
break;
case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
- adev->family = AMDGPU_FAMILY_NV;
- break;
- case IP_VERSION(10, 3, 1):
- adev->family = AMDGPU_FAMILY_VGH;
- break;
- case IP_VERSION(10, 3, 3):
- adev->family = AMDGPU_FAMILY_YC;
+ amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
- adev->gmc.xgmi.supported = true;
-
- /* set NBIO version */
- switch (adev->ip_versions[NBIO_HWIP][0]) {
- case IP_VERSION(6, 1, 0):
- case IP_VERSION(6, 2, 0):
- adev->nbio.funcs = &nbio_v6_1_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
- break;
- case IP_VERSION(7, 0, 0):
- case IP_VERSION(7, 0, 1):
- case IP_VERSION(2, 5, 0):
- adev->nbio.funcs = &nbio_v7_0_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
- break;
- case IP_VERSION(7, 4, 0):
- case IP_VERSION(7, 4, 1):
- case IP_VERSION(7, 4, 4):
- adev->nbio.funcs = &nbio_v7_4_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
- break;
- case IP_VERSION(7, 2, 0):
- case IP_VERSION(7, 2, 1):
- case IP_VERSION(7, 5, 0):
- adev->nbio.funcs = &nbio_v7_2_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
+{
+ /* use GC or MMHUB IP version */
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
break;
- case IP_VERSION(2, 1, 1):
- case IP_VERSION(2, 3, 0):
- case IP_VERSION(2, 3, 1):
- case IP_VERSION(2, 3, 2):
- case IP_VERSION(3, 3, 0):
- case IP_VERSION(3, 3, 1):
- case IP_VERSION(3, 3, 2):
- case IP_VERSION(3, 3, 3):
- adev->nbio.funcs = &nbio_v2_3_funcs;
- adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[HDP_HWIP][0]) {
+static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[OSSSYS_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
+ case IP_VERSION(4, 3, 0):
+ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+ break;
case IP_VERSION(4, 2, 0):
case IP_VERSION(4, 2, 1):
case IP_VERSION(4, 4, 0):
- adev->hdp.funcs = &hdp_v4_0_funcs;
+ amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
case IP_VERSION(5, 0, 3):
- case IP_VERSION(5, 0, 4):
case IP_VERSION(5, 2, 0):
- adev->hdp.funcs = &hdp_v5_0_funcs;
- break;
- default:
- break;
- }
-
- switch (adev->ip_versions[DF_HWIP][0]) {
- case IP_VERSION(3, 6, 0):
- case IP_VERSION(3, 6, 1):
- case IP_VERSION(3, 6, 2):
- adev->df.funcs = &df_v3_6_funcs;
- break;
- case IP_VERSION(2, 1, 0):
- case IP_VERSION(2, 1, 1):
- case IP_VERSION(2, 5, 0):
- case IP_VERSION(3, 5, 1):
- case IP_VERSION(3, 5, 2):
- adev->df.funcs = &df_v1_7_funcs;
+ case IP_VERSION(5, 2, 1):
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[SMUIO_HWIP][0]) {
+static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(9, 0, 0):
- case IP_VERSION(9, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ break;
case IP_VERSION(10, 0, 0):
case IP_VERSION(10, 0, 1):
- case IP_VERSION(10, 0, 2):
- adev->smuio.funcs = &smuio_v9_0_funcs;
+ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
break;
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 2):
- case IP_VERSION(11, 0, 3):
case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 5):
+ case IP_VERSION(11, 0, 9):
case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- adev->smuio.funcs = &smuio_v11_0_funcs;
- break;
- case IP_VERSION(11, 0, 6):
- case IP_VERSION(11, 0, 10):
case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
case IP_VERSION(11, 5, 0):
- case IP_VERSION(13, 0, 1):
- adev->smuio.funcs = &smuio_v11_0_6_funcs;
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ break;
+ case IP_VERSION(11, 0, 8):
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
break;
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
- adev->smuio.funcs = &smuio_v13_0_funcs;
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
default:
- break;
+ return -EINVAL;
}
+ return 0;
+}
- /* what IP to use for this? */
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(9, 0, 1):
- case IP_VERSION(9, 1, 0):
- case IP_VERSION(9, 2, 1):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
- case IP_VERSION(9, 4, 0):
- case IP_VERSION(9, 4, 1):
- case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[MP1_HWIP][0]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(11, 0, 2):
+ if (adev->asic_type == CHIP_ARCTURUS)
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
break;
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 9):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 0, 12):
+ case IP_VERSION(11, 0, 13):
+ case IP_VERSION(11, 5, 0):
+ amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+ break;
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
+ break;
+ case IP_VERSION(13, 0, 1):
+ case IP_VERSION(13, 0, 2):
+ case IP_VERSION(13, 0, 3):
+ amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
+
+static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
+{
+ if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
+ amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+ } else if (adev->ip_versions[DCE_HWIP][0]) {
+ switch (adev->ip_versions[DCE_HWIP][0]) {
+ case IP_VERSION(1, 0, 0):
+ case IP_VERSION(1, 0, 1):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 0, 0):
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 3):
+ case IP_VERSION(3, 0, 1):
+ case IP_VERSION(3, 1, 2):
+ case IP_VERSION(3, 1, 3):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ default:
+ return -EINVAL;
+ }
+ } else if (adev->ip_versions[DCI_HWIP][0]) {
+ switch (adev->ip_versions[DCI_HWIP][0]) {
+ case IP_VERSION(12, 0, 0):
+ case IP_VERSION(12, 0, 1):
+ case IP_VERSION(12, 1, 0):
+ amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ break;
+ default:
+ return -EINVAL;
+ }
+#endif
+ }
+ return 0;
+}
- /* use GC or MMHUB IP version */
+static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
+{
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
case IP_VERSION(9, 1, 0):
@@ -856,319 +738,489 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
break;
case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+ case IP_VERSION(10, 3, 3):
+ amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- switch (adev->ip_versions[OSSSYS_HWIP][0]) {
+static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
- case IP_VERSION(4, 3, 0):
- amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
- break;
+ case IP_VERSION(4, 1, 2):
case IP_VERSION(4, 2, 0):
- case IP_VERSION(4, 2, 1):
+ case IP_VERSION(4, 2, 2):
case IP_VERSION(4, 4, 0):
- amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
- case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 0, 5):
+ amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
+ break;
case IP_VERSION(5, 2, 0):
+ case IP_VERSION(5, 2, 2):
+ case IP_VERSION(5, 2, 4):
+ case IP_VERSION(5, 2, 5):
+ case IP_VERSION(5, 2, 3):
case IP_VERSION(5, 2, 1):
- amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+ amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
break;
default:
return -EINVAL;
}
+ return 0;
+}
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP0_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
- break;
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 2):
- case IP_VERSION(11, 0, 4):
- case IP_VERSION(11, 0, 5):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
- break;
- case IP_VERSION(11, 0, 8):
- amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
- break;
- case IP_VERSION(11, 0, 3):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
+static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
+{
+ if (adev->ip_versions[VCE_HWIP][0]) {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 2, 0):
+ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
break;
default:
return -EINVAL;
}
- }
-
- if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
- switch (adev->ip_versions[MP1_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- case IP_VERSION(11, 0, 2):
- if (adev->asic_type == CHIP_ARCTURUS)
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- else
- amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- break;
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+ switch (adev->ip_versions[VCE_HWIP][0]) {
+ case IP_VERSION(4, 0, 0):
+ case IP_VERSION(4, 1, 0):
+ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break;
default:
return -EINVAL;
}
- }
-
- if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
- amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
-#if defined(CONFIG_DRM_AMD_DC)
- } else if (adev->ip_versions[DCE_HWIP][0]) {
- switch (adev->ip_versions[DCE_HWIP][0]) {
+ } else {
+ switch (adev->ip_versions[UVD_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
- case IP_VERSION(2, 0, 2):
+ amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
+ break;
case IP_VERSION(2, 0, 0):
- case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 0, 2):
+ case IP_VERSION(2, 2, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
+ break;
+ case IP_VERSION(2, 0, 3):
+ break;
+ case IP_VERSION(2, 5, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
+ break;
+ case IP_VERSION(2, 6, 0):
+ amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
+ break;
case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 16):
+ case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
- case IP_VERSION(3, 0, 3):
- case IP_VERSION(3, 0, 1):
- case IP_VERSION(3, 1, 2):
- case IP_VERSION(3, 1, 3):
- amdgpu_device_ip_block_add(adev, &dm_ip_block);
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
- case IP_VERSION(2, 0, 3):
+ case IP_VERSION(3, 0, 33):
+ amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
break;
default:
return -EINVAL;
- }
- } else if (adev->ip_versions[DCI_HWIP][0]) {
- switch (adev->ip_versions[DCI_HWIP][0]) {
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- case IP_VERSION(12, 1, 0):
- amdgpu_device_ip_block_add(adev, &dm_ip_block);
- break;
- default:
+ }
+ }
+ return 0;
+}
+
+static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
+{
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
+ break;
+ default:
+ break;;
+ }
+ return 0;
+}
+
+int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
+{
+ int r;
+
+ switch (adev->asic_type) {
+ case CHIP_VEGA10:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
+ break;
+ case CHIP_VEGA12:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
+ break;
+ case CHIP_RAVEN:
+ vega10_reg_base_init(adev);
+ adev->sdma.num_instances = 1;
+ adev->vcn.num_vcn_inst = 1;
+ if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
+ } else {
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
+ adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
+ }
+ break;
+ case CHIP_VEGA20:
+ vega20_reg_base_init(adev);
+ adev->sdma.num_instances = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
+ adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
+ adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
+ break;
+ case CHIP_ARCTURUS:
+ arct_reg_base_init(adev);
+ adev->sdma.num_instances = 8;
+ adev->vcn.num_vcn_inst = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
+ break;
+ case CHIP_ALDEBARAN:
+ aldebaran_reg_base_init(adev);
+ adev->sdma.num_instances = 5;
+ adev->vcn.num_vcn_inst = 2;
+ adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
+ adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
+ adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
+ adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
+ adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
+ adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
+ adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
+ adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
+ break;
+ default:
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r)
+ return -EINVAL;
+
+ amdgpu_discovery_harvest_ip(adev);
+
+ if (!adev->mman.discovery_bin) {
+ DRM_ERROR("ip discovery uninitialized\n");
return -EINVAL;
}
+ break;
}
-#endif
+
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(9, 0, 1):
- case IP_VERSION(9, 1, 0):
case IP_VERSION(9, 2, 1):
- case IP_VERSION(9, 2, 2):
- case IP_VERSION(9, 3, 0):
case IP_VERSION(9, 4, 0):
case IP_VERSION(9, 4, 1):
case IP_VERSION(9, 4, 2):
- amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+ adev->family = AMDGPU_FAMILY_AI;
+ break;
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ adev->family = AMDGPU_FAMILY_RV;
break;
case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 1, 2):
case IP_VERSION(10, 1, 3):
case IP_VERSION(10, 3, 0):
case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 1):
case IP_VERSION(10, 3, 4):
case IP_VERSION(10, 3, 5):
+ adev->family = AMDGPU_FAMILY_NV;
+ break;
+ case IP_VERSION(10, 3, 1):
+ adev->family = AMDGPU_FAMILY_VGH;
+ break;
case IP_VERSION(10, 3, 3):
- amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+ adev->family = AMDGPU_FAMILY_YC;
break;
default:
return -EINVAL;
}
- switch (adev->ip_versions[SDMA0_HWIP][0]) {
+ if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
+ adev->gmc.xgmi.supported = true;
+
+ /* set NBIO version */
+ switch (adev->ip_versions[NBIO_HWIP][0]) {
+ case IP_VERSION(6, 1, 0):
+ case IP_VERSION(6, 2, 0):
+ adev->nbio.funcs = &nbio_v6_1_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 0, 0):
+ case IP_VERSION(7, 0, 1):
+ case IP_VERSION(2, 5, 0):
+ adev->nbio.funcs = &nbio_v7_0_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 4, 0):
+ case IP_VERSION(7, 4, 1):
+ case IP_VERSION(7, 4, 4):
+ adev->nbio.funcs = &nbio_v7_4_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
+ break;
+ case IP_VERSION(7, 2, 0):
+ case IP_VERSION(7, 2, 1):
+ case IP_VERSION(7, 5, 0):
+ adev->nbio.funcs = &nbio_v7_2_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
+ break;
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 3, 0):
+ case IP_VERSION(2, 3, 1):
+ case IP_VERSION(2, 3, 2):
+ case IP_VERSION(3, 3, 0):
+ case IP_VERSION(3, 3, 1):
+ case IP_VERSION(3, 3, 2):
+ case IP_VERSION(3, 3, 3):
+ adev->nbio.funcs = &nbio_v2_3_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
+ break;
+ default:
+ break;
+ }
+
+ switch (adev->ip_versions[HDP_HWIP][0]) {
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 1):
case IP_VERSION(4, 1, 0):
case IP_VERSION(4, 1, 1):
- case IP_VERSION(4, 1, 2):
case IP_VERSION(4, 2, 0):
- case IP_VERSION(4, 2, 2):
+ case IP_VERSION(4, 2, 1):
case IP_VERSION(4, 4, 0):
- amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+ adev->hdp.funcs = &hdp_v4_0_funcs;
break;
case IP_VERSION(5, 0, 0):
case IP_VERSION(5, 0, 1):
case IP_VERSION(5, 0, 2):
- case IP_VERSION(5, 0, 5):
- amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
- break;
+ case IP_VERSION(5, 0, 3):
+ case IP_VERSION(5, 0, 4):
case IP_VERSION(5, 2, 0):
- case IP_VERSION(5, 2, 2):
- case IP_VERSION(5, 2, 4):
- case IP_VERSION(5, 2, 5):
- case IP_VERSION(5, 2, 3):
- case IP_VERSION(5, 2, 1):
- amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+ adev->hdp.funcs = &hdp_v5_0_funcs;
break;
default:
- return -EINVAL;
+ break;
}
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- switch (adev->ip_versions[MP1_HWIP][0]) {
- case IP_VERSION(9, 0, 0):
- case IP_VERSION(10, 0, 0):
- case IP_VERSION(10, 0, 1):
- case IP_VERSION(11, 0, 2):
- if (adev->asic_type == CHIP_ARCTURUS)
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- else
- amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
- break;
- case IP_VERSION(11, 0, 0):
- case IP_VERSION(11, 0, 9):
- case IP_VERSION(11, 0, 7):
- case IP_VERSION(11, 0, 8):
- case IP_VERSION(11, 0, 11):
- case IP_VERSION(11, 0, 12):
- case IP_VERSION(11, 0, 13):
- case IP_VERSION(11, 5, 0):
- amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- break;
- case IP_VERSION(12, 0, 0):
- case IP_VERSION(12, 0, 1):
- amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
- break;
- case IP_VERSION(13, 0, 1):
- case IP_VERSION(13, 0, 2):
- case IP_VERSION(13, 0, 3):
- amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
+ switch (adev->ip_versions[DF_HWIP][0]) {
+ case IP_VERSION(3, 6, 0):
+ case IP_VERSION(3, 6, 1):
+ case IP_VERSION(3, 6, 2):
+ adev->df.funcs = &df_v3_6_funcs;
+ break;
+ case IP_VERSION(2, 1, 0):
+ case IP_VERSION(2, 1, 1):
+ case IP_VERSION(2, 5, 0):
+ case IP_VERSION(3, 5, 1):
+ case IP_VERSION(3, 5, 2):
+ adev->df.funcs = &df_v1_7_funcs;
+ break;
+ default:
+ break;
}
- if (adev->ip_versions[VCE_HWIP][0]) {
- switch (adev->ip_versions[UVD_HWIP][0]) {
- case IP_VERSION(7, 0, 0):
- case IP_VERSION(7, 2, 0):
- amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
- switch (adev->ip_versions[VCE_HWIP][0]) {
- case IP_VERSION(4, 0, 0):
- case IP_VERSION(4, 1, 0):
- amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
- } else {
- switch (adev->ip_versions[UVD_HWIP][0]) {
- case IP_VERSION(1, 0, 0):
- case IP_VERSION(1, 0, 1):
- amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
- break;
- case IP_VERSION(2, 0, 0):
- case IP_VERSION(2, 0, 2):
- case IP_VERSION(2, 2, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
- break;
- case IP_VERSION(2, 0, 3):
- break;
- case IP_VERSION(2, 5, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
- break;
- case IP_VERSION(2, 6, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
- break;
- case IP_VERSION(3, 0, 0):
- case IP_VERSION(3, 0, 16):
- case IP_VERSION(3, 1, 1):
- case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
- break;
- case IP_VERSION(3, 0, 33):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
- break;
- default:
- return -EINVAL;
- }
+ switch (adev->ip_versions[SMUIO_HWIP][0]) {
+ case IP_VERSION(9, 0, 0):
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(10, 0, 0):
+ case IP_VERSION(10, 0, 1):
+ case IP_VERSION(10, 0, 2):
+ adev->smuio.funcs = &smuio_v9_0_funcs;
+ break;
+ case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
+ case IP_VERSION(11, 0, 3):
+ case IP_VERSION(11, 0, 4):
+ case IP_VERSION(11, 0, 7):
+ case IP_VERSION(11, 0, 8):
+ adev->smuio.funcs = &smuio_v11_0_funcs;
+ break;
+ case IP_VERSION(11, 0, 6):
+ case IP_VERSION(11, 0, 10):
+ case IP_VERSION(11, 0, 11):
+ case IP_VERSION(11, 5, 0):
+ case IP_VERSION(13, 0, 1):
+ adev->smuio.funcs = &smuio_v11_0_6_funcs;
+ break;
+ case IP_VERSION(13, 0, 2):
+ adev->smuio.funcs = &smuio_v13_0_funcs;
+ break;
+ default:
+ break;
+ }
+
+ r = amdgpu_discovery_set_common_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_gmc_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_ih_ip_blocks(adev);
+ if (r)
+ return r;
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ r = amdgpu_discovery_set_psp_ip_blocks(adev);
+ if (r)
+ return r;
+ }
+
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ r = amdgpu_discovery_set_smu_ip_blocks(adev);
+ if (r)
+ return r;
}
+ r = amdgpu_discovery_set_display_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_gc_ip_blocks(adev);
+ if (r)
+ return r;
+
+ r = amdgpu_discovery_set_sdma_ip_blocks(adev);
+ if (r)
+ return r;
+
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
+ r = amdgpu_discovery_set_smu_ip_blocks(adev);
+ if (r)
+ return r;
+ }
+
+ r = amdgpu_discovery_set_mm_ip_blocks(adev);
+ if (r)
+ return r;
+
if (adev->enable_mes) {
- switch (adev->ip_versions[GC_HWIP][0]) {
- case IP_VERSION(10, 1, 10):
- case IP_VERSION(10, 1, 1):
- case IP_VERSION(10, 1, 2):
- case IP_VERSION(10, 1, 3):
- case IP_VERSION(10, 3, 0):
- case IP_VERSION(10, 3, 1):
- case IP_VERSION(10, 3, 2):
- case IP_VERSION(10, 3, 3):
- case IP_VERSION(10, 3, 4):
- case IP_VERSION(10, 3, 5):
- amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
- break;
- default:
- break;;
- }
+ r = amdgpu_discovery_set_mes_ip_blocks(adev);
+ if (r)
+ return r;
}
return 0;
--
2.31.1
next prev parent reply other threads:[~2021-09-21 18:08 UTC|newest]
Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 18:06 [PATCH 00/66] Move to IP driven device enumeration Alex Deucher
2021-09-21 18:06 ` [PATCH 01/66] drm/amdgpu: move headless sku check into harvest function Alex Deucher
2021-09-21 18:06 ` [PATCH 02/66] drm/amdgpu: add debugfs access to the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 03/66] drm/amdgpu: store HW IP versions in the driver structure Alex Deucher
2021-09-21 18:06 ` [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table Alex Deucher
2021-09-22 16:58 ` Felix Kuehling
2021-09-22 20:43 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 05/66] drm/amdgpu: add XGMI HWIP Alex Deucher
2021-09-21 18:06 ` [PATCH 06/66] drm/amdgpu/nv: export common IP functions Alex Deucher
2021-09-21 18:06 ` [PATCH 07/66] drm/amdgpu: add initial IP enumeration via IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 08/66] drm/amdgpu/sdma5.0: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 09/66] drm/amdgpu/sdma5.2: " Alex Deucher
2021-09-22 5:55 ` Lazar, Lijo
2021-09-22 6:08 ` Chen, Guchun
2021-09-22 9:18 ` Lazar, Lijo
2021-09-21 18:06 ` [PATCH 10/66] drm/amdgpu/gfx10: " Alex Deucher
2021-09-21 18:06 ` [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs Alex Deucher
2021-09-22 4:41 ` Lazar, Lijo
2021-09-22 15:19 ` Deucher, Alexander
2021-09-22 16:16 ` Felix Kuehling
2021-09-22 17:07 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 12/66] drm/amdgpu: bind to any 0x1002 PCI diplay class device Alex Deucher
2021-09-21 18:06 ` [PATCH 13/66] drm/amdgpu/gmc10.0: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 14/66] drm/amdgpu: Use IP discovery to drive setting IP blocks by default Alex Deucher
2021-09-21 18:06 ` [PATCH 15/66] drm/amdgpu: drive nav10 from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 16/66] drm/amdgpu/gfxhub2.1: convert to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 17/66] drm/amdgpu/mmhub2.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 18/66] drm/amdgpu/mmhub2.1: " Alex Deucher
2021-09-21 18:06 ` [PATCH 19/66] drm/amdgpu/vcn3.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 20/66] drm/amdgpu/athub2.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 21/66] drm/amdgpu/athub2.1: " Alex Deucher
2021-09-21 18:06 ` [PATCH 22/66] drm/amdgpu/navi10_ih: " Alex Deucher
2021-09-21 18:06 ` [PATCH 23/66] drm/amdgpu/amdgpu_smu: " Alex Deucher
2021-09-22 7:32 ` Lazar, Lijo
2021-09-22 15:40 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 24/66] drm/amdgpu/smu11.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 25/66] drm/amdgpu/navi10_ppt: " Alex Deucher
2021-09-21 18:06 ` [PATCH 26/66] drm/amdgpu/sienna_cichlid_ppt: " Alex Deucher
2021-09-21 18:06 ` [PATCH 27/66] drm/amdgpu: drive all navi asics from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 28/66] drm/amdgpu/nv: convert to IP version checking Alex Deucher
2021-09-22 7:31 ` Lazar, Lijo
2021-09-22 15:21 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 29/66] drm/amdgpu/display/dm: " Alex Deucher
2021-09-22 7:37 ` Lazar, Lijo
2021-09-22 15:53 ` Deucher, Alexander
2021-09-21 18:06 ` [PATCH 30/66] drm/amdgpu: add DCI HWIP Alex Deucher
2021-09-23 15:43 ` Harry Wentland
2021-09-24 19:58 ` Alex Deucher
2021-09-24 20:40 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 31/66] drm/amdgpu: make soc15_common_ip_funcs static Alex Deucher
2021-09-21 18:06 ` [PATCH 32/66] drm/amdgpu/soc15: export common IP functions Alex Deucher
2021-09-21 18:06 ` [PATCH 33/66] drm/amdgpu: add initial IP discovery support for vega based parts Alex Deucher
2021-09-22 7:48 ` Lazar, Lijo
2021-09-22 7:54 ` Lazar, Lijo
2021-09-22 15:58 ` Alex Deucher
2021-09-21 18:06 ` [PATCH 34/66] drm/amdgpu/soc15: get rev_id in soc15_common_early_init Alex Deucher
2021-09-21 18:06 ` [PATCH 35/66] drm/amdgpu: drive all vega asics from the IP discovery table Alex Deucher
2021-09-21 18:06 ` [PATCH 36/66] drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support Alex Deucher
2021-09-23 15:58 ` Harry Wentland
2021-09-21 18:06 ` [PATCH 37/66] drm/amdgpu/display/dm: convert RAVEN to IP version checking Alex Deucher
2021-09-21 18:06 ` [PATCH 38/66] drm/amdgpu/sdma4.0: convert " Alex Deucher
2021-09-21 18:06 ` [PATCH 39/66] drm/amdgpu/hdp4.0: " Alex Deucher
2021-09-21 18:06 ` [PATCH 40/66] drm/amdgpu/gfx9.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 41/66] drm/amdgpu/amdgpu_psp: " Alex Deucher
2021-09-21 18:07 ` [PATCH 42/66] drm/amdgpu/psp_v11.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 43/66] drm/amdgpu/psp_v13.0: " Alex Deucher
2021-09-21 18:07 ` [PATCH 44/66] drm/amdgpu/pm/smu_v11.0: update " Alex Deucher
2021-09-21 18:07 ` [PATCH 45/66] drm/amdgpu/pm/smu_v13.0: convert " Alex Deucher
2021-09-22 8:18 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more " Alex Deucher
2021-09-22 8:16 ` Lazar, Lijo
2021-09-22 16:06 ` Deucher, Alexander
2021-09-21 18:07 ` [PATCH 47/66] drm/amdgpu/amdgpu_vcn: convert to " Alex Deucher
2021-09-21 18:07 ` [PATCH 48/66] drm/amdgpu/vcn2.5: " Alex Deucher
2021-09-21 18:07 ` [PATCH 49/66] drm/amdgpu/soc15: " Alex Deucher
2021-09-21 18:07 ` [PATCH 50/66] drm/amd/display: fix error case handling Alex Deucher
2021-09-21 18:07 ` [PATCH 51/66] drm/amdgpu: add VCN1 hardware IP Alex Deucher
2021-09-21 18:07 ` [PATCH 52/66] drm/amdgpu: store all instances of IPs in the IP version table Alex Deucher
2021-09-22 8:36 ` Lazar, Lijo
2021-09-22 8:45 ` Lazar, Lijo
2021-09-21 18:07 ` [PATCH 53/66] drm/amdgpu: add HWID of SDMA instance 2 and 3 Alex Deucher
2021-09-21 18:07 ` [PATCH 54/66] drm/amdgpu: get VCN and SDMA instances from IP discovery table Alex Deucher
2021-09-21 18:07 ` [PATCH 55/66] drm/amdgpu/sdma: remove manual instance setting Alex Deucher
2021-09-21 18:07 ` [PATCH 56/66] drm/amdgpu/vcn: " Alex Deucher
2021-09-21 18:07 ` [PATCH 57/66] drm/amdgpu: get VCN harvest information from IP discovery table Alex Deucher
2021-09-21 18:07 ` [PATCH 58/66] drm/amdgpu/ucode: add default behavior Alex Deucher
2021-09-21 18:07 ` [PATCH 59/66] drm/amdgpu: add new asic_type for IP discovery Alex Deucher
2021-09-21 18:07 ` [PATCH 60/66] drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default Alex Deucher
2021-09-23 6:47 ` Lazar, Lijo
2021-09-23 21:46 ` Alex Deucher
2021-09-21 18:07 ` [PATCH 61/66] drm/amdgpu: convert IP version array to include instances Alex Deucher
2021-09-22 9:08 ` Lazar, Lijo
2021-09-22 16:17 ` Alex Deucher
2021-09-23 4:58 ` Lazar, Lijo
2021-09-23 21:42 ` Alex Deucher
2021-09-21 18:07 ` Alex Deucher [this message]
2021-09-21 18:07 ` [PATCH 63/66] drm/amdgpu: add support for SRIOV in IP discovery path Alex Deucher
2021-09-21 18:07 ` [PATCH 64/66] drm/amdkfd: clean up parameters in kgd2kfd_probe Alex Deucher
2021-09-21 18:07 ` [PATCH 65/66] drm/amdkfd: convert kfd_device.c to use GC IP version Alex Deucher
2021-09-21 21:00 ` ernstp
2021-09-22 1:44 ` Alex Deucher
2021-09-22 16:55 ` Felix Kuehling
2021-09-21 18:07 ` [PATCH 66/66] drm/amdgpu: add an option to override IP discovery table from a file Alex Deucher
2021-09-22 7:54 ` [PATCH 00/66] Move to IP driven device enumeration Christian König
2021-09-22 20:25 ` Alex Deucher
2021-09-23 6:43 ` Christian König
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