* [PATCH 2/2] drm/amdgpu: update shader array golden setting for cyan_skillfish
2021-09-23 5:42 [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask Huang Rui
@ 2021-09-23 5:42 ` Huang Rui
2021-09-23 5:47 ` [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask Keely, Sean
1 sibling, 0 replies; 3+ messages in thread
From: Huang Rui @ 2021-09-23 5:42 UTC (permalink / raw)
To: amd-gfx
Cc: Felix Kuehling, Sean Keely, Alex Deucher, Lang Yu, Chen Gong,
Huang Rui
Update golden setting to enable full compute units for cyan_skillfish.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 16dbe593cba2..5f9382d61234 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3573,7 +3573,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
- SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG, 0xffff0000, 0xffe00000)
};
#define DEFAULT_SH_MEM_CONFIG \
--
2.25.1
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* Re: [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask
2021-09-23 5:42 [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask Huang Rui
2021-09-23 5:42 ` [PATCH 2/2] drm/amdgpu: update shader array golden setting for cyan_skillfish Huang Rui
@ 2021-09-23 5:47 ` Keely, Sean
1 sibling, 0 replies; 3+ messages in thread
From: Keely, Sean @ 2021-09-23 5:47 UTC (permalink / raw)
To: Huang, Ray, amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix, Deucher, Alexander, Yu, Lang, Gong, Curry,
Huang, Ray
[-- Attachment #1: Type: text/plain, Size: 2019 bytes --]
[AMD Official Use Only]
That is not how the register works. The *16 has nothing to do with cu counts. This is to address the upper and lower 16 bits in the register as each half of the register programs a separate SH.
________________________________
From: Huang, Ray <Ray.Huang@amd.com>
Sent: Thursday, September 23, 2021, 12:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix; Keely, Sean; Deucher, Alexander; Yu, Lang; Gong, Curry; Huang, Ray
Subject: [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask
We should use the real compute unit number for shader array mask. Some
asic doesn't have 16 compute units per shader array.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
index c021519af810..0891c937f4da 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
@@ -159,12 +159,12 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
se_mask[i] = 0;
i = 0;
- for (cu = 0; cu < 16; cu++) {
+ for (cu = 0; cu < cu_info.num_cu_per_sh; cu++) {
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
for (se = 0; se < cu_info.num_shader_engines; se++) {
if (cu_per_sh[se][sh] > cu) {
if (cu_mask[i / 32] & (1 << (i % 32)))
- se_mask[se] |= 1 << (cu + sh * 16);
+ se_mask[se] |= 1 << (cu + sh * cu_info.num_cu_per_sh);
i++;
if (i == cu_mask_count)
return;
--
2.25.1
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