From: Philip Yang <Philip.Yang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: alex.sierra@amd.com, Philip Yang <Philip.Yang@amd.com>,
Felix.Kuehling@amd.com
Subject: [PATCH 1/2] drm/amdgpu: enable Navi 48-bit IH timestamp counter
Date: Tue, 23 Nov 2021 11:03:51 -0500 [thread overview]
Message-ID: <20211123160352.21228-1-Philip.Yang@amd.com> (raw)
By default this timestamp is 32 bit counter. It gets overflowed in
around 10 minutes.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 1d8414c3fadb..dafad6030947 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -160,6 +160,7 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
tmp = RREG32(ih_regs->ih_rb_cntl);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
+ tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
/* enable_intr field is only valid in ring0 */
if (ih == &adev->irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
--
2.17.1
next reply other threads:[~2021-11-23 16:04 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-23 16:03 Philip Yang [this message]
2021-11-23 16:03 ` [PATCH 2/2] drm/amdgpu: enable Navi retry fault wptr overflow Philip Yang
2021-11-23 16:58 ` Felix Kuehling
2021-11-24 7:08 ` [PATCH 1/2] drm/amdgpu: enable Navi 48-bit IH timestamp counter Christian König
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