AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Solomon Chiu <solomon.chiu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	Nevenko Stupar <Nevenko.Stupar@amd.com>,
	wayne.lin@amd.com, Jun Lei <jun.lei@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 11/21] drm/amd/display: update DML1 logic for unbounded req handling
Date: Sat, 9 Jul 2022 00:35:19 +0800	[thread overview]
Message-ID: <20220708163529.3534276-12-solomon.chiu@amd.com> (raw)
In-Reply-To: <20220708163529.3534276-1-solomon.chiu@amd.com>

From: "Lei, Jun" <Jun.Lei@amd.com>

[why]
Unbounded request logic in resource/DML has some issues where
unbounded request is being enabled incorrectly.  SW today enables
unbounded request unconditionally in hardware, on the assumption
that HW can always support it in single pipe scenarios.

This worked until now because the same assumption is made in DML.
A new DML update is needed to fix a bug, where there are single
pipe scenarios where unbounded cannot be enabled, and this change
in DML needs to be ported in, and dcn32 resource logic fixed.

[how]
First, dcn32_resource should program unbounded req in HW according
to unbounded req enablement output from DML, as opposed to DML input

Second, port in DML1 update which disables unbounded req in some
scenarios to fix an issue with poor stutter performance

Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jun Lei <jun.lei@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 9 +++++++++
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 9 +++++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 95edca4c085b..607172542242 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -110,6 +110,7 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
 dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
 dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth);
 dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
+
 dml_get_attr_func(cstate_max_cap_mode, mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
 dml_get_attr_func(comp_buffer_size_kbytes, mode_lib->vba.CompressedBufferSizeInkByte);
 dml_get_attr_func(pixel_chunk_size_in_kbyte, mode_lib->vba.PixelChunkSizeInKByte);
@@ -120,6 +121,11 @@ dml_get_attr_func(min_meta_chunk_size_in_byte, mode_lib->vba.MinMetaChunkSizeByt
 dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
 dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark);
 
+dml_get_attr_func(comp_buffer_reserved_space_kbytes, mode_lib->vba.CompBufReservedSpaceKBytes);
+dml_get_attr_func(comp_buffer_reserved_space_64bytes, mode_lib->vba.CompBufReservedSpace64B);
+dml_get_attr_func(comp_buffer_reserved_space_zs, mode_lib->vba.CompBufReservedSpaceZs);
+dml_get_attr_func(unbounded_request_enabled, mode_lib->vba.UnboundedRequestEnabled);
+
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
 {\
 	unsigned int which_plane; \
@@ -842,6 +848,9 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 
 	mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings;
 	mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
+
+	mode_lib->vba.DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment = 0;
+
 	mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
 	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
 		if (pipes[k].pipe.src.unbounded_req_mode == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 10ff536ef2a4..acb9434fb955 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -67,6 +67,10 @@ dml_get_attr_decl(min_pixel_chunk_size_in_byte);
 dml_get_attr_decl(min_meta_chunk_size_in_byte);
 dml_get_attr_decl(fclk_watermark);
 dml_get_attr_decl(usr_retraining_watermark);
+dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
+dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
+dml_get_attr_decl(comp_buffer_reserved_space_zs);
+dml_get_attr_decl(unbounded_request_enabled);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
 
@@ -470,6 +474,7 @@ struct vba_vars_st {
 	bool XFCEnabled[DC__NUM_DPP__MAX];
 	bool ScalerEnabled[DC__NUM_DPP__MAX];
 	unsigned int VBlankNom[DC__NUM_DPP__MAX];
+	bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
 
 	// Intermediates/Informational
 	bool ImmediateFlipSupport;
@@ -513,6 +518,10 @@ struct vba_vars_st {
 	double StutterPeriodBestCase;
 	Watermarks      Watermark;
 	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
+	unsigned int CompBufReservedSpaceKBytes;
+	unsigned int CompBufReservedSpace64B;
+	unsigned int CompBufReservedSpaceZs;
+	bool CompBufReservedSpaceNeedAdjustment;
 
 	// These are the clocks calcuated by the library but they are not actually
 	// used explicitly. They are fetched by tests and then possibly used. The
-- 
2.25.1


  parent reply	other threads:[~2022-07-08 16:36 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-08 16:35 [PATCH 00/21] DC Patches July 11, 2022 Solomon Chiu
2022-07-08 16:35 ` [PATCH 01/21] drm/amd/display: Exit SubVP if MPO in use Solomon Chiu
2022-07-08 16:35 ` [PATCH 02/21] drm/amd/display: Check for DP2.0 when checking ODM combine Solomon Chiu
2022-07-08 16:35 ` [PATCH 03/21] drm/amd/display: Helper function for ALPM initialization Solomon Chiu
2022-07-08 16:35 ` [PATCH 04/21] drm/amd/display: Removing assert statements for Linux Solomon Chiu
2022-07-08 16:35 ` [PATCH 05/21] drm/amd/display: Fix windowed MPO video with ODM combine for DCN32 Solomon Chiu
2022-07-08 16:35 ` [PATCH 06/21] drm/amd/display: Clear edid when unplug mst connector Solomon Chiu
2022-07-08 16:35 ` [PATCH 07/21] drm/amd/display: Disable PSRSU when DSC enabled on the specific sink Solomon Chiu
2022-07-08 16:35 ` [PATCH 08/21] drm/amd/display: Fix black screen when disabling Freesync in OSD Solomon Chiu
2022-07-08 16:35 ` [PATCH 09/21] drm/amd/display: make enable link independent from verified link caps Solomon Chiu
2022-07-08 16:35 ` [PATCH 10/21] drm/amd/display: Reduce SCDC Status Flags Definition Solomon Chiu
2022-07-08 16:35 ` Solomon Chiu [this message]
2022-07-08 16:35 ` [PATCH 12/21] drm/amd/display: 3.2.193 Solomon Chiu
2022-07-11 15:38 ` [PATCH 00/21] DC Patches July 11, 2022 Wheeler, Daniel
2022-07-12 15:37 ` [PATCH 13/21] drm/amd/display: Re-implementing ARGB16161616 pixel format as 22 Solomon Chiu
2022-07-12 15:38 ` [PATCH 14/21] drm/amd/display: Grab dc_lock before detecting link Solomon Chiu
2022-07-12 15:39 ` [PATCH 15/21] drm/amd/display: add system info table log Solomon Chiu
2022-07-12 15:40 ` [PATCH 16/21] drm/amd/display: Add DCN reg offsets to DC Solomon Chiu
2022-07-12 15:40 ` [PATCH 17/21] drm/amd/display: Add NBIO " Solomon Chiu
2022-07-12 15:41 ` [PATCH 18/21] drm/amd/display: Fix lag when moving windowed MPO across display using ODM 2:1 combine Solomon Chiu
2022-07-12 15:41 ` [PATCH 19/21] drm/amd/display: Fix wrong reference Solomon Chiu
2022-07-12 15:42 ` [PATCH 20/21] drm/amd/display: 3.2.194 Solomon Chiu
2022-07-12 15:42 ` [PATCH 21/21] drm/amd/display: Ignore First MST Sideband Message Return Error Solomon Chiu
2022-07-12 15:47   ` [21/21] " Limonciello, Mario

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220708163529.3534276-12-solomon.chiu@amd.com \
    --to=solomon.chiu@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Dmytro.Laktyushkin@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Nevenko.Stupar@amd.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=agustin.gutierrez@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=jun.lei@amd.com \
    --cc=pavle.kotarac@amd.com \
    --cc=qingqing.zhuo@amd.com \
    --cc=roman.li@amd.com \
    --cc=stylon.wang@amd.com \
    --cc=wayne.lin@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox