[PATCH 00/14] user queue support for VCN 4.0.5

[PATCH 00/14] user queue support for VCN 4.0.5

[David (Ming Qiang) Wu]

add user queue support for VCN 4.0.5

David (Ming Qiang) Wu (10):
  amdgpu: add global aggregated doorbell bo
  drm/amdgpu: add AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL
  drm/amdgpu/userq: add doorbell size for VCN and VPE
  drm/amdgpu: use amdgpu_user_queue instead of amdgpu_umsch_mm
  amdgpu/umsch: Add VCN IP init to umsch driver
  drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to be common
  drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping
  drm/amdgpu/umsch: user queue support for vcn
  drm/amdgpu: add AMDGPU_INFO_DOORBELL
  drm/amdgpu/umsch: userq suspend and resume context

Saleemkhan Jamadar (4):
  amdgpu/umsch: Update UMSCH interface and mqd structure
  drm/amdgpu/vcn: changes when kernel queue is disabled
  drm/amdgpu/vcn: handle interrupt received from fw
  drm/amdgpu/vcn: handle the suspend context interrupt

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |   2 +-
 .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  16 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  10 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c       |   2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c       |  18 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 300 +++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h  |  43 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c     |  69 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h     |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h       |   4 +
 drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    |  90 +-----
 drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c    |  75 ++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c       | 122 +++++--
 .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h |  10 +
 .../drm/amd/include/umsch_mm_4_0_api_def.h    |  12 +-
 include/uapi/drm/amdgpu_drm.h                 |  14 +
 18 files changed, 646 insertions(+), 151 deletions(-)

-- 
2.43.0

[PATCH 01/14] amdgpu: add global aggregated doorbell bo

[David (Ming Qiang) Wu]

Allocate aggregated doorbell bo at device level so it can be
used for multiple IPs

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h              |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c | 16 ++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0f6e9cdbe7d8..aeefc13fd36b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1245,6 +1245,9 @@ struct amdgpu_device {
 	 * Must be last --ends in a flexible-array member.
 	 */
 	struct amdgpu_kfd_dev		kfd;
+
+	/* aggregated doorbell */
+	struct amdgpu_bo		*agdb_bo;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
index bc7858567321..2b0d123bc984 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c
@@ -148,6 +148,7 @@ uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev,
  */
 int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev)
 {
+	struct amdgpu_bo_param bp;
 	int r;
 	int size;
 
@@ -176,6 +177,19 @@ int amdgpu_doorbell_create_kernel_doorbells(struct amdgpu_device *adev)
 	}
 
 	adev->doorbell.num_kernel_doorbells = size / sizeof(u32);
+
+	/* allocate aggregated doorbell bo at device level */
+	if (!adev->agdb_bo) {
+		memset(&bp, 0, sizeof(bp));
+		bp.type        = ttm_bo_type_device;
+		bp.size        = AMDGPU_GPU_PAGE_SIZE;
+		bp.byte_align  = AMDGPU_GPU_PAGE_SIZE;
+		bp.domain      = AMDGPU_GEM_DOMAIN_DOORBELL;
+		bp.bo_ptr_size = sizeof(struct amdgpu_bo);
+
+		return amdgpu_bo_create(adev, &bp, &adev->agdb_bo);
+	}
+
 	return 0;
 }
 
@@ -241,4 +255,6 @@ void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 	amdgpu_bo_free_kernel(&adev->doorbell.kernel_doorbells,
 			      NULL,
 			      (void **)&adev->doorbell.cpu_addr);
+	if (adev->agdb_bo)
+		amdgpu_bo_unref(&adev->agdb_bo);
 }
-- 
2.43.0

[PATCH 02/14] drm/amdgpu: add AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL

[David (Ming Qiang) Wu]

get a global GEM bo info and aggregated doorbell handle

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++
 include/uapi/drm/amdgpu_drm.h           | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e5b7f3e34e40..b96e5b85b315 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -1007,6 +1007,8 @@ amdgpu_get_global_bo(struct amdgpu_device *adev, u32 id)
 	switch (id) {
 	case AMDGPU_GEM_GLOBAL_MMIO_REMAP:
 		return adev->rmmio_remap.bo;
+	case AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL:
+		return adev->agdb_bo;
 	default:
 		return NULL;
 	}
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 9e4692c270fe..3e7c12d5987f 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -806,6 +806,7 @@ union drm_amdgpu_wait_fences {
 #define AMDGPU_GEM_OP_OPEN_GLOBAL		3
 
 #define AMDGPU_GEM_GLOBAL_MMIO_REMAP		0
+#define AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL   1
 
 struct drm_amdgpu_gem_vm_entry {
 	/* Start of mapping (in bytes) */
-- 
2.43.0

[PATCH 03/14] drm/amdgpu/userq: add doorbell size for VCN and VPE

[David (Ming Qiang) Wu]

This is needed for VCN and VPE to get the doorbell index

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index e007f10a6c1c..dc9000b25be4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -601,6 +601,10 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr,
 	case AMDGPU_HW_IP_DMA:
 		db_size = sizeof(u64);
 		break;
+	case AMDGPU_HW_IP_VCN_ENC:
+	case AMDGPU_HW_IP_VPE:
+		db_size = sizeof(u32);
+		break;
 	default:
 		drm_file_err(uq_mgr->file, "[Usermode queues] IP %d not support\n",
 			     db_info->queue_type);
-- 
2.43.0

[PATCH 04/14] amdgpu/umsch: Update UMSCH interface and mqd structure

[David (Ming Qiang) Wu]

From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>

Add mqd configuration for VCN IP.
Update the UMSCH interface w.r.t FW change.

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h     | 16 +++++++++-------
 drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c       |  4 ++--
 .../gpu/drm/amd/include/umsch_mm_4_0_api_def.h   | 12 +++++-------
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
index 2c771a753778..af34faa5e1ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
@@ -26,10 +26,8 @@
 #define __AMDGPU_UMSCH_MM_H__
 
 enum UMSCH_SWIP_ENGINE_TYPE {
-	UMSCH_SWIP_ENGINE_TYPE_VCN0 = 0,
-	UMSCH_SWIP_ENGINE_TYPE_VCN1 = 1,
-	UMSCH_SWIP_ENGINE_TYPE_VCN = 2,
-	UMSCH_SWIP_ENGINE_TYPE_VPE = 3,
+	UMSCH_SWIP_ENGINE_TYPE_VCN = 0,
+	UMSCH_SWIP_ENGINE_TYPE_VPE = 1,
 	UMSCH_SWIP_ENGINE_TYPE_MAX
 };
 
@@ -92,8 +90,10 @@ struct umsch_mm_add_queue_input {
 	struct {
 		uint32_t is_context_suspended : 1;
 		uint32_t collaboration_mode : 1;
-		uint32_t reserved : 30;
+		uint32_t mqd_type : 2;
+		uint32_t reserved : 28;
 	};
+	u64 fence_signal_addr;
 };
 
 struct umsch_mm_remove_queue_input {
@@ -107,8 +107,10 @@ struct MQD_INFO {
 	uint32_t rb_base_hi;
 	uint32_t rb_base_lo;
 	uint32_t rb_size;
-	uint32_t wptr_val;
-	uint32_t rptr_val;
+	u32 wptr_addr_monotonic_hi;
+	u32 wptr_addr_monotonic_lo;
+	u32 rptr_addr_monotonic_hi;
+	u32 rptr_addr_monotonic_lo;
 	uint32_t unmapped;
 	uint32_t vmid;
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index ce3bb12e3572..79e1ec9933c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -282,8 +282,6 @@ static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch)
 		adev->vpe.collaborate_mode ? 0x3 : 0x0;
 	set_hw_resources.engine_mask = umsch->engine_mask;
 
-	set_hw_resources.vcn0_hqd_mask[0] = umsch->vcn0_hqd_mask;
-	set_hw_resources.vcn1_hqd_mask[0] = umsch->vcn1_hqd_mask;
 	set_hw_resources.vcn_hqd_mask[0] = umsch->vcn_hqd_mask[0];
 	set_hw_resources.vcn_hqd_mask[1] = umsch->vcn_hqd_mask[1];
 	set_hw_resources.vpe_hqd_mask[0] = umsch->vpe_hqd_mask;
@@ -356,6 +354,8 @@ static int umsch_mm_v4_0_add_queue(struct amdgpu_umsch_mm *umsch,
 	add_queue.vm_context_cntl = input_ptr->vm_context_cntl;
 	add_queue.is_context_suspended = input_ptr->is_context_suspended;
 	add_queue.collaboration_mode = adev->vpe.collaborate_mode ? 1 : 0;
+	add_queue.mqd_type = input_ptr->mqd_type;
+	add_queue.fence_signal_addr = input_ptr->fence_signal_addr;
 
 	add_queue.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
 	add_queue.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
diff --git a/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h b/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h
index ca83e9e5c3ff..735ec05859fe 100644
--- a/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h
+++ b/drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h
@@ -159,10 +159,8 @@ enum UMSCH_AMD_PRIORITY_LEVEL {
 };
 
 enum UMSCH_ENGINE_TYPE {
-	UMSCH_ENGINE_TYPE_VCN0 = 0,
-	UMSCH_ENGINE_TYPE_VCN1 = 1,
-	UMSCH_ENGINE_TYPE_VCN = 2,
-	UMSCH_ENGINE_TYPE_VPE = 3,
+	UMSCH_ENGINE_TYPE_VCN = 0,
+	UMSCH_ENGINE_TYPE_VPE = 1,
 	UMSCH_ENGINE_TYPE_MAX
 };
 
@@ -215,8 +213,6 @@ union UMSCHAPI__SET_HW_RESOURCES {
 		uint32_t collaboration_mask_vpe;
 		uint32_t engine_mask;
 		uint32_t logging_vmid;
-		uint32_t vcn0_hqd_mask[MAX_VCN0_INSTANCES];
-		uint32_t vcn1_hqd_mask[MAX_VCN1_INSTANCES];
 		uint32_t vcn_hqd_mask[MAX_VCN_INSTANCES];
 		uint32_t vpe_hqd_mask[MAX_VPE_INSTANCES];
 		uint64_t g_sch_ctx_gpu_mc_ptr;
@@ -299,11 +295,13 @@ union UMSCHAPI__ADD_QUEUE {
 		struct {
 			uint32_t is_context_suspended : 1;
 			uint32_t collaboration_mode : 1;
-			uint32_t reserved : 30;
+			uint32_t mqd_type : 2;
+			uint32_t reserved : 28;
 		};
 		struct UMSCH_API_STATUS api_status;
 		uint32_t process_csa_array_index;
 		uint32_t context_csa_array_index;
+		u64 fence_signal_addr;
 	};
 
 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
-- 
2.43.0

[PATCH 05/14] drm/amdgpu: use amdgpu_user_queue instead of amdgpu_umsch_mm

[David (Ming Qiang) Wu]

amdgpu_umsch_mm is retired and use common module parameter
amdgpu_user_queue for umsch user queue enablement

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       | 10 ----------
 4 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index aeefc13fd36b..57d0e08d829a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -256,7 +256,6 @@ extern int amdgpu_num_kcq;
 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
 extern int amdgpu_vcnfw_log;
 extern int amdgpu_sg_display;
-extern int amdgpu_umsch_mm;
 extern int amdgpu_seamless;
 extern int amdgpu_umsch_mm_fwlog;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index aeb90708f229..b23e140b12d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -2069,7 +2069,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
 		amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
 	}
 
-	if (amdgpu_umsch_mm & amdgpu_umsch_mm_fwlog)
+	if ((amdgpu_user_queue == 1 || amdgpu_user_queue == 2) & amdgpu_umsch_mm_fwlog)
 		amdgpu_debugfs_umsch_fwlog_init(adev, &adev->umsch_mm);
 
 	amdgpu_debugfs_vcn_sched_mask_init(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 41e63c286912..98ca952a8bbb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2647,7 +2647,7 @@ static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
 	case IP_VERSION(4, 0, 5):
 	case IP_VERSION(4, 0, 6):
-		if (amdgpu_umsch_mm & 0x1) {
+		if (amdgpu_user_queue == 1 || amdgpu_user_queue == 2) {
 			amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
 			adev->enable_umsch_mm = true;
 		}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 67b8c33d5ee3..442af4fd85aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -236,7 +236,6 @@ int amdgpu_use_xgmi_p2p = 1;
 int amdgpu_vcnfw_log;
 int amdgpu_sg_display = -1; /* auto */
 int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
-int amdgpu_umsch_mm;
 int amdgpu_seamless = -1; /* auto */
 uint amdgpu_debug_mask;
 int amdgpu_agp = -1; /* auto */
@@ -976,15 +975,6 @@ module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
 module_param_named(sg_display, amdgpu_sg_display, int, 0444);
 
-/**
- * DOC: umsch_mm (int)
- * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
- * (0 = disabled (default), 1 = enabled)
- */
-MODULE_PARM_DESC(umsch_mm,
-	"Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
-module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
-
 /**
  * DOC: umsch_mm_fwlog (int)
  * Enable umschfw log output for debugging, the default is disabled.
-- 
2.43.0

[PATCH 06/14] drm/amdgpu/vcn: changes when kernel queue is disabled

[David (Ming Qiang) Wu]

From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>

v4 - don't call ring test and touch the ring structure
     when it is not initialized (Christian)
     add kernel message to note kernel queues are not
     supported with user queues (Alex)
v3 - don't call amdgpu_ring_init() when kernel queue
     is disabled (David)
v2 - Add flag to enable/disable userq and kernelq (Alex)

Disable ring buffer address update to the RB register for user queues.
RB register update is handled by UMSCH.

vcn 4_0_5 cannot support both user queue and kernel
queue at same time, so disable kernel queue when
user queue is enabled. (David)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 51 ++++++++++++++++++-------
 2 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 82624b44e661..bea95307fd42 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -368,6 +368,9 @@ struct amdgpu_vcn {
 	struct mutex            workload_profile_mutex;
 	u32 reg_count;
 	const struct amdgpu_hwip_reg_entry *reg_list;
+
+	bool			disable_uq;
+	bool			disable_kq;
 };
 
 struct amdgpu_fw_shared_rb_ptrs_struct {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 1f6a22983c0d..d2744cd4c865 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -115,6 +115,24 @@ static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block)
 	struct amdgpu_device *adev = ip_block->adev;
 	int i, r;
 
+	switch (amdgpu_user_queue) {
+	case -1:
+	case 0:
+	default:
+		adev->vcn.disable_kq = false;
+		adev->vcn.disable_uq = true;
+		break;
+	case 1:
+		adev->vcn.disable_kq = true; /* does not support if userq is enabled */
+		adev->vcn.disable_uq = false;
+		dev_info_once(adev->dev, "Kernel queues are not supported with user queues.\n");
+		break;
+	case 2:
+		adev->vcn.disable_kq = true;
+		adev->vcn.disable_uq = false;
+		break;
+	}
+
 	if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 6))
 		adev->vcn.per_inst_fw = true;
 
@@ -187,13 +205,14 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 						2 + 8 * i;
 		ring->vm_hub = AMDGPU_MMHUB0(0);
-		sprintf(ring->name, "vcn_unified_%d", i);
-
-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
-				AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
-		if (r)
-			return r;
 
+		if (!adev->vcn.disable_kq) {
+			sprintf(ring->name, "vcn_unified_%d", i);
+			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
+					     AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
+			if (r)
+				return r;
+		}
 		fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 		fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 		fw_shared->sq.is_enabled = 1;
@@ -300,6 +319,8 @@ static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block)
 		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 				((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
 
+		if (adev->vcn.disable_kq)
+			continue;
 		r = amdgpu_ring_test_helper(ring);
 		if (r)
 			return r;
@@ -1005,10 +1026,11 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
 	}
 
 	ring = &adev->vcn.inst[inst_idx].ring_enc[0];
-
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-	WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
+	if (!adev->vcn.disable_kq) {
+		WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
+		WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+		WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
+	}
 
 	tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
 	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
@@ -1195,10 +1217,11 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
 	WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
 		     ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
 		     VCN_RB1_DB_CTRL__EN_MASK);
-
-	WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
-	WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-	WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
+	if (!adev->vcn.disable_kq) {
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
+		WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+		WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
+	}
 
 	tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
 	tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
-- 
2.43.0

[PATCH 07/14] amdgpu/umsch: Add VCN IP init to umsch driver

[David (Ming Qiang) Wu]

Add VCN IP init in the umsch init sequence.

v4 - set the vmid_mask_mm_vcn to be 0xff00
     keep bit 0-7 for kernel queue VPE and JPEG
v3 - use vcn.disable_kq rather than gfx.disable_kq
v2 - configure the mqd and hqd mask based on
     usermode and kernel queue enable (Alex)

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index cd707d70a0bf..760285ad028f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -272,6 +272,17 @@ static int umsch_mm_init(struct amdgpu_device *adev)
 	adev->umsch_mm.engine_mask = (1 << UMSCH_SWIP_ENGINE_TYPE_VPE);
 	adev->umsch_mm.vpe_hqd_mask = 0xfe;
 
+	/* reserve bit 0-7 for kernel queue VPE and JPEG */
+	adev->umsch_mm.vmid_mask_mm_vcn = 0xff00;
+	adev->umsch_mm.engine_mask |= (1 << UMSCH_SWIP_ENGINE_TYPE_VCN);
+	/*
+	 *  HQD mask values for VCN
+	 *  0xf - Use all the VCN HW Queues
+	 *  0xe - HWQ 1 is used for kernel submission
+	 *		0xe is just leaving the Q 1 and using the rest of Queues
+	 */
+	adev->umsch_mm.vcn_hqd_mask[0] = adev->vcn.disable_kq ? 0xf : 0xe;
+	adev->umsch_mm.vcn_hqd_mask[1] = adev->vcn.disable_kq ? 0xf : 0xe;
 	r = amdgpu_device_wb_get(adev, &adev->umsch_mm.wb_index);
 	if (r) {
 		dev_err(adev->dev, "failed to alloc wb for umsch: %d\n", r);
-- 
2.43.0

[PATCH 08/14] drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to be common

[David (Ming Qiang) Wu]

rename mes_userq_create_wptr_mapping() to common function so
it can be used by umsch as well. Also replace DRM_ERROR() with
dev_err().

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c  | 87 +++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h  |  3 +
 drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 90 +---------------------
 3 files changed, 91 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index dc9000b25be4..ebb0d8a9967f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -1572,3 +1572,90 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
 
 	return r;
 }
+
+static int
+amdgpu_userq_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
+{
+	int ret;
+
+	ret = amdgpu_bo_reserve(bo, true);
+	if (ret) {
+		dev_err(adev->dev, "Failed to reserve bo. ret %d\n", ret);
+		goto err_reserve_bo_failed;
+	}
+
+	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
+	if (ret) {
+		dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
+		goto err_map_bo_gart_failed;
+	}
+
+	amdgpu_bo_unreserve(bo);
+	bo = amdgpu_bo_ref(bo);
+
+	return 0;
+
+err_map_bo_gart_failed:
+	amdgpu_bo_unreserve(bo);
+err_reserve_bo_failed:
+	return ret;
+}
+
+int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
+			      struct amdgpu_usermode_queue *queue,
+			      uint64_t wptr)
+{
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_bo_va_mapping *wptr_mapping;
+	struct amdgpu_vm *wptr_vm;
+	struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
+	int ret;
+
+	wptr_vm = queue->vm;
+	ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
+	if (ret)
+		return ret;
+
+	wptr &= AMDGPU_GMC_HOLE_MASK;
+	wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
+	amdgpu_bo_unreserve(wptr_vm->root.bo);
+	if (!wptr_mapping) {
+		dev_err(adev->dev, "Failed to lookup wptr bo\n");
+		return -EINVAL;
+	}
+
+	wptr_obj->obj = wptr_mapping->bo_va->base.bo;
+	if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
+		dev_err(adev->dev, "Requested GART mapping for wptr bo larger than one page\n");
+		return -EINVAL;
+	}
+
+	ret = amdgpu_userq_map_gtt_bo_to_gart(adev, wptr_obj->obj);
+	if (ret) {
+		dev_err(adev->dev, "Failed to map wptr bo to GART\n");
+		return ret;
+	}
+
+	ret = amdgpu_bo_reserve(wptr_obj->obj, true);
+	if (ret) {
+		dev_err(adev->dev, "Failed to reserve wptr bo\n");
+		return ret;
+	}
+
+	/* TODO use eviction fence instead of pinning. */
+	ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
+	if (ret) {
+		drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
+		goto unresv_bo;
+	}
+
+	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
+	amdgpu_bo_unreserve(wptr_obj->obj);
+
+	return 0;
+
+unresv_bo:
+	amdgpu_bo_unreserve(wptr_obj->obj);
+	return ret;
+
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
index 4feeeaed20f9..758464203d98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
@@ -159,4 +159,7 @@ int amdgpu_userq_input_va_validate(struct amdgpu_device *adev,
 int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev,
 				       struct amdgpu_bo_va_mapping *mapping,
 				       uint64_t saddr);
+int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
+				     struct amdgpu_usermode_queue *queue,
+				     uint64_t wptr);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
index 9508709abd49..9c1a99f61472 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c
@@ -30,94 +30,6 @@
 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE
 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE
 
-static int
-mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo)
-{
-	int ret;
-
-	ret = amdgpu_bo_reserve(bo, true);
-	if (ret) {
-		DRM_ERROR("Failed to reserve bo. ret %d\n", ret);
-		goto err_reserve_bo_failed;
-	}
-
-	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
-	if (ret) {
-		DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret);
-		goto err_map_bo_gart_failed;
-	}
-
-	amdgpu_bo_unreserve(bo);
-	bo = amdgpu_bo_ref(bo);
-
-	return 0;
-
-err_map_bo_gart_failed:
-	amdgpu_bo_unreserve(bo);
-err_reserve_bo_failed:
-	return ret;
-}
-
-static int
-mes_userq_create_wptr_mapping(struct amdgpu_device *adev,
-			      struct amdgpu_userq_mgr *uq_mgr,
-			      struct amdgpu_usermode_queue *queue,
-			      uint64_t wptr)
-{
-	struct amdgpu_bo_va_mapping *wptr_mapping;
-	struct amdgpu_vm *wptr_vm;
-	struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
-	int ret;
-
-	wptr_vm = queue->vm;
-	ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
-	if (ret)
-		return ret;
-
-	wptr &= AMDGPU_GMC_HOLE_MASK;
-	wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
-	amdgpu_bo_unreserve(wptr_vm->root.bo);
-	if (!wptr_mapping) {
-		DRM_ERROR("Failed to lookup wptr bo\n");
-		return -EINVAL;
-	}
-
-	wptr_obj->obj = wptr_mapping->bo_va->base.bo;
-	if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
-		DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n");
-		return -EINVAL;
-	}
-
-	ret = mes_userq_map_gtt_bo_to_gart(wptr_obj->obj);
-	if (ret) {
-		DRM_ERROR("Failed to map wptr bo to GART\n");
-		return ret;
-	}
-
-	ret = amdgpu_bo_reserve(wptr_obj->obj, true);
-	if (ret) {
-		DRM_ERROR("Failed to reserve wptr bo\n");
-		return ret;
-	}
-
-	/* TODO use eviction fence instead of pinning. */
-	ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
-	if (ret) {
-		drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
-		goto unresv_bo;
-	}
-
-	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
-	amdgpu_bo_unreserve(wptr_obj->obj);
-
-	return 0;
-
-unresv_bo:
-	amdgpu_bo_unreserve(wptr_obj->obj);
-	return ret;
-
-}
-
 static int convert_to_mes_priority(int priority)
 {
 	switch (priority) {
@@ -413,7 +325,7 @@ static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue,
 	}
 
 	/* FW expects WPTR BOs to be mapped into GART */
-	r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr);
+	r = amdgpu_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr);
 	if (r) {
 		DRM_ERROR("Failed to create WPTR mapping\n");
 		goto free_ctx;
-- 
2.43.0

[PATCH 09/14] drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping

[David (Ming Qiang) Wu]

v3 - lock both VM and WPTR BO (Christian)
v2 - get a reference (amdgpu_bo_ref(wptr_obj->obj)) before
     amdgpu_bo_unreserve() to avoid use-after-free issue

remove amdgpu_userq_map_gtt_bo_to_gart() and move its calls
into amdgpu_userq_create_wptr_mapping() to eliminate duplicated
calls.

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 89 ++++++++---------------
 1 file changed, 32 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index ebb0d8a9967f..59e593b3bae7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -1573,34 +1573,6 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
 	return r;
 }
 
-static int
-amdgpu_userq_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
-{
-	int ret;
-
-	ret = amdgpu_bo_reserve(bo, true);
-	if (ret) {
-		dev_err(adev->dev, "Failed to reserve bo. ret %d\n", ret);
-		goto err_reserve_bo_failed;
-	}
-
-	ret = amdgpu_ttm_alloc_gart(&bo->tbo);
-	if (ret) {
-		dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
-		goto err_map_bo_gart_failed;
-	}
-
-	amdgpu_bo_unreserve(bo);
-	bo = amdgpu_bo_ref(bo);
-
-	return 0;
-
-err_map_bo_gart_failed:
-	amdgpu_bo_unreserve(bo);
-err_reserve_bo_failed:
-	return ret;
-}
-
 int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
 			      struct amdgpu_usermode_queue *queue,
 			      uint64_t wptr)
@@ -1609,53 +1581,56 @@ int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
 	struct amdgpu_bo_va_mapping *wptr_mapping;
 	struct amdgpu_vm *wptr_vm;
 	struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
+	struct drm_exec exec;
 	int ret;
 
+	wptr &= AMDGPU_GMC_HOLE_MASK;
 	wptr_vm = queue->vm;
-	ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
-	if (ret)
-		return ret;
+	drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
+	drm_exec_until_all_locked(&exec) {
+		ret = amdgpu_vm_lock_pd(wptr_vm, &exec, 0);
+		drm_exec_retry_on_contention(&exec);
+		if (unlikely(ret))
+			goto out_unlock;
 
-	wptr &= AMDGPU_GMC_HOLE_MASK;
-	wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
-	amdgpu_bo_unreserve(wptr_vm->root.bo);
-	if (!wptr_mapping) {
-		dev_err(adev->dev, "Failed to lookup wptr bo\n");
-		return -EINVAL;
+		wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
+		if (!wptr_mapping) {
+			dev_err(adev->dev, "Failed to lookup wptr bo\n");
+			goto out_unlock;
+		}
+
+		wptr_obj->obj = wptr_mapping->bo_va->base.bo;
+		ret = drm_exec_lock_obj(&exec, &wptr_obj->obj->tbo.base);
+		drm_exec_retry_on_contention(&exec);
+		if (unlikely(ret))
+			goto out_unlock;
 	}
 
-	wptr_obj->obj = wptr_mapping->bo_va->base.bo;
+	/* Now both VM and WPTR BO are locked */
 	if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
 		dev_err(adev->dev, "Requested GART mapping for wptr bo larger than one page\n");
-		return -EINVAL;
-	}
-
-	ret = amdgpu_userq_map_gtt_bo_to_gart(adev, wptr_obj->obj);
-	if (ret) {
-		dev_err(adev->dev, "Failed to map wptr bo to GART\n");
-		return ret;
-	}
-
-	ret = amdgpu_bo_reserve(wptr_obj->obj, true);
-	if (ret) {
-		dev_err(adev->dev, "Failed to reserve wptr bo\n");
-		return ret;
+		ret = -EINVAL;
+		goto out_unlock;
 	}
 
 	/* TODO use eviction fence instead of pinning. */
 	ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
 	if (ret) {
 		drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
-		goto unresv_bo;
+		goto out_unlock;
 	}
 
+	ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo);
+	if (ret) {
+		dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
+		amdgpu_bo_unpin(wptr_obj->obj);
+		goto out_unlock;
+	}
 	queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
-	amdgpu_bo_unreserve(wptr_obj->obj);
-
-	return 0;
+	amdgpu_bo_ref(wptr_obj->obj);
 
-unresv_bo:
-	amdgpu_bo_unreserve(wptr_obj->obj);
+out_unlock:
+	drm_exec_fini(&exec);
 	return ret;
 
 }
-- 
2.43.0

Re: [PATCH 09/14] drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping

[Alex Deucher]

On Tue, Feb 10, 2026 at 5:07 PM David (Ming Qiang) Wu <David.Wu3@amd.com> wrote:
>
> v3 - lock both VM and WPTR BO (Christian)
> v2 - get a reference (amdgpu_bo_ref(wptr_obj->obj)) before
>      amdgpu_bo_unreserve() to avoid use-after-free issue
>
> remove amdgpu_userq_map_gtt_bo_to_gart() and move its calls
> into amdgpu_userq_create_wptr_mapping() to eliminate duplicated
> calls.
>
> Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>

+ Jesse

This is a nice clean up regardless of the rest of the series.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I think patches 8, 9 can land now.  It would be nice to rework patch
11 to handle doorbell offsets for gfx/compute and sdma and land that
as well.  I think for the rest, we should hold off until we get
alignment with the FW team.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 89 ++++++++---------------
>  1 file changed, 32 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> index ebb0d8a9967f..59e593b3bae7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> @@ -1573,34 +1573,6 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost)
>         return r;
>  }
>
> -static int
> -amdgpu_userq_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
> -{
> -       int ret;
> -
> -       ret = amdgpu_bo_reserve(bo, true);
> -       if (ret) {
> -               dev_err(adev->dev, "Failed to reserve bo. ret %d\n", ret);
> -               goto err_reserve_bo_failed;
> -       }
> -
> -       ret = amdgpu_ttm_alloc_gart(&bo->tbo);
> -       if (ret) {
> -               dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
> -               goto err_map_bo_gart_failed;
> -       }
> -
> -       amdgpu_bo_unreserve(bo);
> -       bo = amdgpu_bo_ref(bo);
> -
> -       return 0;
> -
> -err_map_bo_gart_failed:
> -       amdgpu_bo_unreserve(bo);
> -err_reserve_bo_failed:
> -       return ret;
> -}
> -
>  int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
>                               struct amdgpu_usermode_queue *queue,
>                               uint64_t wptr)
> @@ -1609,53 +1581,56 @@ int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
>         struct amdgpu_bo_va_mapping *wptr_mapping;
>         struct amdgpu_vm *wptr_vm;
>         struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
> +       struct drm_exec exec;
>         int ret;
>
> +       wptr &= AMDGPU_GMC_HOLE_MASK;
>         wptr_vm = queue->vm;
> -       ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
> -       if (ret)
> -               return ret;
> +       drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
> +       drm_exec_until_all_locked(&exec) {
> +               ret = amdgpu_vm_lock_pd(wptr_vm, &exec, 0);
> +               drm_exec_retry_on_contention(&exec);
> +               if (unlikely(ret))
> +                       goto out_unlock;
>
> -       wptr &= AMDGPU_GMC_HOLE_MASK;
> -       wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
> -       amdgpu_bo_unreserve(wptr_vm->root.bo);
> -       if (!wptr_mapping) {
> -               dev_err(adev->dev, "Failed to lookup wptr bo\n");
> -               return -EINVAL;
> +               wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT);
> +               if (!wptr_mapping) {
> +                       dev_err(adev->dev, "Failed to lookup wptr bo\n");
> +                       goto out_unlock;
> +               }
> +
> +               wptr_obj->obj = wptr_mapping->bo_va->base.bo;
> +               ret = drm_exec_lock_obj(&exec, &wptr_obj->obj->tbo.base);
> +               drm_exec_retry_on_contention(&exec);
> +               if (unlikely(ret))
> +                       goto out_unlock;
>         }
>
> -       wptr_obj->obj = wptr_mapping->bo_va->base.bo;
> +       /* Now both VM and WPTR BO are locked */
>         if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
>                 dev_err(adev->dev, "Requested GART mapping for wptr bo larger than one page\n");
> -               return -EINVAL;
> -       }
> -
> -       ret = amdgpu_userq_map_gtt_bo_to_gart(adev, wptr_obj->obj);
> -       if (ret) {
> -               dev_err(adev->dev, "Failed to map wptr bo to GART\n");
> -               return ret;
> -       }
> -
> -       ret = amdgpu_bo_reserve(wptr_obj->obj, true);
> -       if (ret) {
> -               dev_err(adev->dev, "Failed to reserve wptr bo\n");
> -               return ret;
> +               ret = -EINVAL;
> +               goto out_unlock;
>         }
>
>         /* TODO use eviction fence instead of pinning. */
>         ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
>         if (ret) {
>                 drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
> -               goto unresv_bo;
> +               goto out_unlock;
>         }
>
> +       ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo);
> +       if (ret) {
> +               dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
> +               amdgpu_bo_unpin(wptr_obj->obj);
> +               goto out_unlock;
> +       }
>         queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
> -       amdgpu_bo_unreserve(wptr_obj->obj);
> -
> -       return 0;
> +       amdgpu_bo_ref(wptr_obj->obj);
>
> -unresv_bo:
> -       amdgpu_bo_unreserve(wptr_obj->obj);
> +out_unlock:
> +       drm_exec_fini(&exec);
>         return ret;
>
>  }
> --
> 2.43.0
>

RE: [PATCH 09/14] drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping

[Zhang, Jesse(Jie)]

AMD General

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Friday, April 24, 2026 9:38 PM
> To: Wu, David <David.Wu3@amd.com>; Zhang, Jesse(Jie)
> <Jesse.Zhang@amd.com>
> Cc: amd-gfx@lists.freedesktop.org; Koenig, Christian
> <Christian.Koenig@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Liu, Leo <Leo.Liu@amd.com>; Zhang, Boyuan
> <Boyuan.Zhang@amd.com>
> Subject: Re: [PATCH 09/14] drm/amdgpu/userq: rework on
> amdgpu_userq_create_wptr_mapping
>
> On Tue, Feb 10, 2026 at 5:07 PM David (Ming Qiang) Wu <David.Wu3@amd.com>
> wrote:
> >
> > v3 - lock both VM and WPTR BO (Christian)
> > v2 - get a reference (amdgpu_bo_ref(wptr_obj->obj)) before
> >      amdgpu_bo_unreserve() to avoid use-after-free issue
> >
> > remove amdgpu_userq_map_gtt_bo_to_gart() and move its calls into
> > amdgpu_userq_create_wptr_mapping() to eliminate duplicated calls.
> >
> > Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
>
> + Jesse
>
> This is a nice clean up regardless of the rest of the series.
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> I think patches 8, 9
> can land now.  It would be nice to rework patch
> 11 to handle doorbell offsets for gfx/compute and sdma and land that as well.  I think
> for the rest, we should hold off until we get alignment with the FW team.
Hi  David and Alex,

Is it possible to update AMDGPU_INFO_USERQ_DOORBELL like this to handle the doorbell offset for gfx/compute/sdma and vcn?https://lists.freedesktop.org/archives/amd-gfx/2026-April/143561.html

Thanks
Jesse
>
> Alex
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 89
> > ++++++++---------------
> >  1 file changed, 32 insertions(+), 57 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > index ebb0d8a9967f..59e593b3bae7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
> > @@ -1573,34 +1573,6 @@ int amdgpu_userq_post_reset(struct amdgpu_device
> *adev, bool vram_lost)
> >         return r;
> >  }
> >
> > -static int
> > -amdgpu_userq_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct
> > amdgpu_bo *bo) -{
> > -       int ret;
> > -
> > -       ret = amdgpu_bo_reserve(bo, true);
> > -       if (ret) {
> > -               dev_err(adev->dev, "Failed to reserve bo. ret %d\n", ret);
> > -               goto err_reserve_bo_failed;
> > -       }
> > -
> > -       ret = amdgpu_ttm_alloc_gart(&bo->tbo);
> > -       if (ret) {
> > -               dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
> > -               goto err_map_bo_gart_failed;
> > -       }
> > -
> > -       amdgpu_bo_unreserve(bo);
> > -       bo = amdgpu_bo_ref(bo);
> > -
> > -       return 0;
> > -
> > -err_map_bo_gart_failed:
> > -       amdgpu_bo_unreserve(bo);
> > -err_reserve_bo_failed:
> > -       return ret;
> > -}
> > -
> >  int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
> >                               struct amdgpu_usermode_queue *queue,
> >                               uint64_t wptr) @@ -1609,53 +1581,56 @@
> > int amdgpu_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr,
> >         struct amdgpu_bo_va_mapping *wptr_mapping;
> >         struct amdgpu_vm *wptr_vm;
> >         struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj;
> > +       struct drm_exec exec;
> >         int ret;
> >
> > +       wptr &= AMDGPU_GMC_HOLE_MASK;
> >         wptr_vm = queue->vm;
> > -       ret = amdgpu_bo_reserve(wptr_vm->root.bo, false);
> > -       if (ret)
> > -               return ret;
> > +       drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
> > +       drm_exec_until_all_locked(&exec) {
> > +               ret = amdgpu_vm_lock_pd(wptr_vm, &exec, 0);
> > +               drm_exec_retry_on_contention(&exec);
> > +               if (unlikely(ret))
> > +                       goto out_unlock;
> >
> > -       wptr &= AMDGPU_GMC_HOLE_MASK;
> > -       wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >>
> PAGE_SHIFT);
> > -       amdgpu_bo_unreserve(wptr_vm->root.bo);
> > -       if (!wptr_mapping) {
> > -               dev_err(adev->dev, "Failed to lookup wptr bo\n");
> > -               return -EINVAL;
> > +               wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >>
> PAGE_SHIFT);
> > +               if (!wptr_mapping) {
> > +                       dev_err(adev->dev, "Failed to lookup wptr bo\n");
> > +                       goto out_unlock;
> > +               }
> > +
> > +               wptr_obj->obj = wptr_mapping->bo_va->base.bo;
> > +               ret = drm_exec_lock_obj(&exec, &wptr_obj->obj->tbo.base);
> > +               drm_exec_retry_on_contention(&exec);
> > +               if (unlikely(ret))
> > +                       goto out_unlock;
> >         }
> >
> > -       wptr_obj->obj = wptr_mapping->bo_va->base.bo;
> > +       /* Now both VM and WPTR BO are locked */
> >         if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) {
> >                 dev_err(adev->dev, "Requested GART mapping for wptr bo larger than
> one page\n");
> > -               return -EINVAL;
> > -       }
> > -
> > -       ret = amdgpu_userq_map_gtt_bo_to_gart(adev, wptr_obj->obj);
> > -       if (ret) {
> > -               dev_err(adev->dev, "Failed to map wptr bo to GART\n");
> > -               return ret;
> > -       }
> > -
> > -       ret = amdgpu_bo_reserve(wptr_obj->obj, true);
> > -       if (ret) {
> > -               dev_err(adev->dev, "Failed to reserve wptr bo\n");
> > -               return ret;
> > +               ret = -EINVAL;
> > +               goto out_unlock;
> >         }
> >
> >         /* TODO use eviction fence instead of pinning. */
> >         ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT);
> >         if (ret) {
> >                 drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n");
> > -               goto unresv_bo;
> > +               goto out_unlock;
> >         }
> >
> > +       ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo);
> > +       if (ret) {
> > +               dev_err(adev->dev, "Failed to bind bo to GART. ret %d\n", ret);
> > +               amdgpu_bo_unpin(wptr_obj->obj);
> > +               goto out_unlock;
> > +       }
> >         queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj);
> > -       amdgpu_bo_unreserve(wptr_obj->obj);
> > -
> > -       return 0;
> > +       amdgpu_bo_ref(wptr_obj->obj);
> >
> > -unresv_bo:
> > -       amdgpu_bo_unreserve(wptr_obj->obj);
> > +out_unlock:
> > +       drm_exec_fini(&exec);
> >         return ret;
> >
> >  }
> > --
> > 2.43.0
> >

[PATCH 10/14] drm/amdgpu/umsch: user queue support for vcn

[David (Ming Qiang) Wu]

v5 - add convert_to_umsch_priority() to allow user priority setting
v4 - add vcn.agdb_offset which will be used in AMDGPU_INFO_DOORBELL
v3 - 1 use common function amdgpu_userq_create_wptr_mapping()
     2 use dev_err() instead of DRM_ERROR()
     3 don't need mqd setting from user space
     4 powergating on the last queue removal
v2 - use amdgpu_bo_gpu_offset() and reserve BO (Christian)

Implement User mode queues infrastructure api support for UMSCH.
And enable VCN user queues for vcn v4_0_5.
Drop v4_0_6 as it is not tested.

Use new amdgpu_userq_funcs structure for above functions and
convert rb_size as dword (David)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 237 ++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c    |   3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h    |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h      |   1 +
 drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c   |   5 +
 6 files changed, 242 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 760285ad028f..5a9589b56534 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -31,6 +31,7 @@
 #include "amdgpu.h"
 #include "amdgpu_umsch_mm.h"
 #include "umsch_mm_v4_0.h"
+#include "amdgpu_userq_fence.h"
 
 MODULE_FIRMWARE("amdgpu/umsch_mm_4_0_0.bin");
 
@@ -125,7 +126,6 @@ int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch)
 
 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
 	case IP_VERSION(4, 0, 5):
-	case IP_VERSION(4, 0, 6):
 		fw_name = "4_0_0";
 		break;
 	default:
@@ -253,15 +253,21 @@ int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch)
 
 static void umsch_mm_agdb_index_init(struct amdgpu_device *adev)
 {
+	struct amdgpu_bo *obj = adev->agdb_bo;
 	uint32_t umsch_mm_agdb_start;
-	int i;
+	int i, r;
 
-	umsch_mm_agdb_start = adev->doorbell_index.max_assignment + 1;
-	umsch_mm_agdb_start = roundup(umsch_mm_agdb_start, 1024);
-	umsch_mm_agdb_start += (AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1);
+	r = amdgpu_bo_reserve(obj, true);
+	if (r)
+		return;
+	adev->vcn.agdb_offset = AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1;
+	umsch_mm_agdb_start = amdgpu_doorbell_index_on_bar(adev, obj,
+				   adev->vcn.agdb_offset, sizeof(u32));
+	amdgpu_bo_unreserve(obj);
 
 	for (i = 0; i < CONTEXT_PRIORITY_NUM_LEVELS; i++)
-		adev->umsch_mm.agdb_index[i] = umsch_mm_agdb_start + i;
+		adev->umsch_mm.agdb_index[i] = umsch_mm_agdb_start +
+					       (i * DIV_ROUND_UP(sizeof(u32), 4));
 }
 
 static int umsch_mm_init(struct amdgpu_device *adev)
@@ -328,8 +334,8 @@ static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block)
 
 	switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
 	case IP_VERSION(4, 0, 5):
-	case IP_VERSION(4, 0, 6):
 		umsch_mm_v4_0_set_funcs(&adev->umsch_mm);
+		adev->userq_funcs[AMDGPU_HW_IP_VCN_ENC] = &userq_umsch_4_0_funcs;
 		break;
 	default:
 		return -EINVAL;
@@ -440,6 +446,216 @@ static int umsch_mm_resume(struct amdgpu_ip_block *ip_block)
 	return umsch_mm_hw_init(ip_block);
 }
 
+static int convert_to_umsch_priority(int priority)
+{
+	switch (priority) {
+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW:
+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW:
+	default:
+		return CONTEXT_PRIORITY_LEVEL_NORMAL;
+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH:
+		return CONTEXT_PRIORITY_LEVEL_FOCUS;
+	case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH:
+		return CONTEXT_PRIORITY_LEVEL_REALTIME;
+	}
+}
+
+static int amdgpu_umsch_userq_map(struct amdgpu_usermode_queue *queue)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
+	struct amdgpu_userq_obj *ctx = &queue->fw_obj;
+	struct umsch_mm_add_queue_input in_queue;
+	int r;
+
+	memset(&in_queue, 0, sizeof(struct umsch_mm_add_queue_input));
+	in_queue.process_id = queue->vm->pasid;
+	in_queue.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo);
+	in_queue.process_va_start = 0;
+	in_queue.process_va_end = (adev->vm_manager.max_pfn - 1);
+	in_queue.process_quantum = 100000; /* 10ms */;
+	in_queue.process_csa_addr = ctx->gpu_addr;
+
+	in_queue.context_quantum = 10000; /* 1ms */;
+	in_queue.context_csa_addr = ctx->gpu_addr + AMDGPU_GPU_PAGE_SIZE;
+	in_queue.inprocess_context_priority = CONTEXT_PRIORITY_LEVEL_NORMAL;
+	in_queue.context_global_priority_level = convert_to_umsch_priority(queue->priority);
+	if (queue->queue_type == AMDGPU_HW_IP_VCN_ENC) {
+		if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 5)) {
+			in_queue.doorbell_offset_0 = queue->doorbell_index;
+			in_queue.doorbell_offset_1 = 0;
+			in_queue.affinity = 1;
+			if (adev->vcn.num_vcn_inst == 2) {
+				in_queue.doorbell_offset_1 = (queue->doorbell_index + 2 + 8 * 1);
+				in_queue.affinity = 0x5;
+			}
+		}
+
+		in_queue.engine_type = UMSCH_SWIP_ENGINE_TYPE_VCN;
+	}
+
+	in_queue.mqd_addr = queue->mqd.gpu_addr;
+	in_queue.mqd_type = 2; /* MQD Type Linux */
+	in_queue.fence_signal_addr = queue->fence_drv->gpu_addr;
+	in_queue.vm_context_cntl = hub->vm_cntx_cntl;
+	amdgpu_umsch_mm_lock(&adev->umsch_mm);
+	r = umsch->funcs->add_queue(umsch, &in_queue);
+	amdgpu_umsch_mm_unlock(&adev->umsch_mm);
+	if (r)
+		dev_err(adev->dev, "Failed to create queue. for IP %d r %d\n", queue->queue_type, r);
+
+	return r;
+}
+
+static int amdgpu_umsch_userq_unmap(struct amdgpu_usermode_queue *queue)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_userq_obj *ctx = &queue->fw_obj;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	struct umsch_mm_remove_queue_input q_input;
+	int r;
+
+	memset(&q_input, 0, sizeof(struct umsch_mm_remove_queue_input));
+	q_input.doorbell_offset_0 = queue->doorbell_index;
+	q_input.doorbell_offset_1 = 0;
+	if (adev->vcn.num_vcn_inst == 2)
+		q_input.doorbell_offset_1 = (queue->doorbell_index + 2 + 8 * 1);
+
+	q_input.context_csa_addr = ctx->gpu_addr + AMDGPU_GPU_PAGE_SIZE;
+
+	amdgpu_umsch_mm_lock(&adev->umsch_mm);
+	r = umsch->funcs->remove_queue(umsch, &q_input);
+	amdgpu_umsch_mm_unlock(&adev->umsch_mm);
+	if (r)
+		dev_err(adev->dev, "Failed to unmap queue in HW, err (%d)\n", r);
+
+	return r;
+}
+
+static int amdgpu_umsch_mqd_create(struct amdgpu_usermode_queue *queue,
+				   struct drm_amdgpu_userq_in *args)
+{
+	struct amdgpu_userq_obj *sfence = &queue->suspend_fence_obj;
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_userq_obj *ctx = &queue->fw_obj;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	struct amdgpu_mqd_prop *userq_props;
+	struct MQD_INFO *mqd;
+	int r, size, i;
+
+	/* Structure to initialize MQD for userqueue using generic MQD init function */
+	userq_props = kzalloc(sizeof(struct amdgpu_mqd_prop), GFP_KERNEL);
+	if (!userq_props) {
+		dev_err(adev->dev, "Failed to allocate memory for userq_props\n");
+		return -ENOMEM;
+	}
+
+	/* FW expects WPTR BOs to be mapped into GART */
+	r = amdgpu_userq_create_wptr_mapping(uq_mgr, queue, args->wptr_va);
+	if (r) {
+		dev_err(adev->dev, "Failed to create WPTR mapping\n");
+		goto exit;
+	}
+
+	r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, sizeof(struct MQD_INFO));
+	if (r) {
+		dev_err(adev->dev, "Failed to create MQD object for userqueue\n");
+		goto exit;
+	}
+
+	userq_props->wptr_gpu_addr = args->wptr_va;
+	userq_props->mqd_gpu_addr = queue->mqd.gpu_addr;
+	userq_props->use_doorbell = true;
+	userq_props->doorbell_index = queue->doorbell_index; /* VCN0 doorbell*/
+	queue->userq_prop = userq_props;
+
+	/* Initialize the MQD BO with user given values */
+	mqd = (struct MQD_INFO *)queue->mqd.cpu_ptr;
+	memset(mqd, 0, sizeof(struct MQD_INFO));
+	mqd->rb_base_lo = lower_32_bits(args->queue_va);
+	mqd->rb_base_hi = upper_32_bits(args->queue_va);
+	mqd->wptr_addr_monotonic_hi = upper_32_bits(queue->wptr_obj.gpu_addr);
+	mqd->wptr_addr_monotonic_lo = lower_32_bits(queue->wptr_obj.gpu_addr);
+	mqd->rptr_addr_monotonic_hi = upper_32_bits(args->rptr_va);
+	mqd->rptr_addr_monotonic_lo = lower_32_bits(args->rptr_va);
+	mqd->rb_size = args->queue_size / 4;
+	mqd->unmapped = 1;
+
+	size = 2 * PAGE_SIZE;
+	r = amdgpu_userq_create_object(uq_mgr, ctx, size);
+	if (r) {
+		dev_err(adev->dev, "Failed to allocate ctx space bo for userqueue, err:%d\n", r);
+		goto free_mqd;
+	}
+
+	mutex_lock(&umsch->mutex_hidden);
+	atomic_inc(&umsch->userq_count);
+	for (i = 0; i < adev->num_ip_blocks; i++) {
+		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN) {
+			const struct amdgpu_ip_block_version *ip_block =
+						adev->ip_blocks[i].version;
+
+			r = ip_block->funcs->set_powergating_state(&adev->ip_blocks[i],
+						AMD_PG_STATE_UNGATE);
+			if (r) {
+				dev_err(adev->dev, "Failed to power ON VCN :err %d\n", r);
+				goto free_ctx;
+			}
+		}
+	}
+	mutex_unlock(&umsch->mutex_hidden);
+
+	r = amdgpu_userq_create_object(uq_mgr, sfence, AMDGPU_GPU_PAGE_SIZE);
+	if (r) {
+		DRM_ERROR("Failed to allocate suspend fence bo for userq, err:%d\n", r);
+		goto free_ctx;
+	}
+
+	return 0;
+
+free_ctx:
+	amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj);
+
+free_mqd:
+	amdgpu_userq_destroy_object(uq_mgr, &queue->mqd);
+
+exit:
+	kfree(userq_props);
+	return r;
+}
+
+static void amdgpu_umsch_destroy_queue(struct amdgpu_usermode_queue *queue)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	int r, i;
+
+	amdgpu_userq_destroy_object(uq_mgr, &queue->mqd);
+	amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj);
+	kfree(queue->userq_prop);
+
+	mutex_lock(&umsch->mutex_hidden);
+	if (!atomic_dec_return(&umsch->userq_count)) {
+		for (i = 0; i < adev->num_ip_blocks; i++) {
+			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN) {
+				const struct amdgpu_ip_block_version *ip_block =
+					adev->ip_blocks[i].version;
+
+				r = ip_block->funcs->set_powergating_state(&adev->ip_blocks[i],
+									   AMD_PG_STATE_GATE);
+				if (r)
+					dev_err(adev->dev, "Failed to power OFF VCN :err %d\n", r);
+			}
+		}
+	}
+	mutex_unlock(&umsch->mutex_hidden);
+}
+
 void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm)
 {
 #if defined(CONFIG_DEBUG_FS)
@@ -559,3 +775,10 @@ const struct amdgpu_ip_block_version umsch_mm_v4_0_ip_block = {
 	.rev = 0,
 	.funcs = &umsch_mm_v4_0_ip_funcs,
 };
+
+const struct amdgpu_userq_funcs userq_umsch_4_0_funcs = {
+	.mqd_create = amdgpu_umsch_mqd_create,
+	.mqd_destroy = amdgpu_umsch_destroy_queue,
+	.map = amdgpu_umsch_userq_map,
+	.unmap = amdgpu_umsch_userq_unmap,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
index af34faa5e1ef..6b827c92e817 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
@@ -25,6 +25,8 @@
 #ifndef __AMDGPU_UMSCH_MM_H__
 #define __AMDGPU_UMSCH_MM_H__
 
+extern const struct amdgpu_userq_funcs userq_umsch_4_0_funcs;
+
 enum UMSCH_SWIP_ENGINE_TYPE {
 	UMSCH_SWIP_ENGINE_TYPE_VCN = 0,
 	UMSCH_SWIP_ENGINE_TYPE_VPE = 1,
@@ -181,6 +183,7 @@ struct amdgpu_umsch_mm {
 	uint64_t			log_gpu_addr;
 	uint32_t			mem_size;
 	uint32_t			log_offset;
+	atomic_t                        userq_count;
 };
 
 int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index 59e593b3bae7..50c75acc8e94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -916,7 +916,8 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev,
 		/* Usermode queues are only supported for GFX IP as of now */
 		if (args->in.ip_type != AMDGPU_HW_IP_GFX &&
 		    args->in.ip_type != AMDGPU_HW_IP_DMA &&
-		    args->in.ip_type != AMDGPU_HW_IP_COMPUTE) {
+		    args->in.ip_type != AMDGPU_HW_IP_COMPUTE &&
+		    args->in.ip_type != AMDGPU_HW_IP_VCN_ENC) {
 			drm_file_err(filp, "Usermode queue doesn't support IP type %u\n",
 				     args->in.ip_type);
 			return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
index 758464203d98..7a5b5c204601 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
@@ -66,6 +66,7 @@ struct amdgpu_usermode_queue {
 	struct amdgpu_userq_obj	db_obj;
 	struct amdgpu_userq_obj fw_obj;
 	struct amdgpu_userq_obj wptr_obj;
+	struct amdgpu_userq_obj suspend_fence_obj;
 	struct xarray		fence_drv_xa;
 	struct amdgpu_userq_fence_driver *fence_drv;
 	struct dma_fence	*last_fence;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index bea95307fd42..ec8540fcc916 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -371,6 +371,7 @@ struct amdgpu_vcn {
 
 	bool			disable_uq;
 	bool			disable_kq;
+	uint32_t		agdb_offset;
 };
 
 struct amdgpu_fw_shared_rb_ptrs_struct {
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 79e1ec9933c5..60d1fdfb2af5 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -289,6 +289,11 @@ static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch)
 	set_hw_resources.g_sch_ctx_gpu_mc_ptr = umsch->sch_ctx_gpu_addr;
 
 	set_hw_resources.enable_level_process_quantum_check = 1;
+	if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 5)) {
+		set_hw_resources.is_vcn0_enabled = 1;
+		if (adev->vcn.num_vcn_inst == 2)
+			set_hw_resources.is_vcn1_enabled = 1;
+	}
 
 	memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0],
 	       sizeof(uint32_t) * 5);
-- 
2.43.0

[PATCH 11/14] drm/amdgpu: add AMDGPU_INFO_DOORBELL

[David (Ming Qiang) Wu]

Use it to get the doorbell range and aggregated doorbell
enablement and offset. This patch only supports VCN for now.

V2 - drop VPE and use vcn.agdb_offset saved in
     umsch_mm_agdb_index_init() (suggested by Alex)

Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 ++++++++++++++++++
 include/uapi/drm/amdgpu_drm.h           | 13 +++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f512b6ec6c53..1b935d285053 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1425,6 +1425,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 			return -EINVAL;
 		}
 	}
+	case AMDGPU_INFO_DOORBELL: {
+		struct drm_amdgpu_info_doorbell doorbell_info = {};
+		/* note: may need to check asic_type */
+		switch (info->query_hw_ip.type) {
+		case AMDGPU_HW_IP_VCN_ENC:
+			if (adev->agdb_bo) {
+				doorbell_info.agdb_enable = 1;
+				doorbell_info.agdb_offset = adev->vcn.agdb_offset;
+			}
+			doorbell_info.index_start = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
+			doorbell_info.index_end = (adev->doorbell_index.vcn.vcn_ring6_7 << 1) + 1;
+			break;
+		default:
+			return -EINVAL;
+		}
+		return copy_to_user(out, &doorbell_info,
+				    min((size_t)size, sizeof(doorbell_info))) ? -EFAULT : 0;
+	}
 	default:
 		DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 		return -EINVAL;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 3e7c12d5987f..902201303700 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1279,6 +1279,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
 #define AMDGPU_INFO_GPUVM_FAULT			0x23
 /* query FW object size and alignment */
 #define AMDGPU_INFO_UQ_FW_AREAS			0x24
+/* query doorbell info */
+#define AMDGPU_INFO_DOORBELL			0x25
 
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
@@ -1688,6 +1690,17 @@ struct drm_color_ctm_3x4 {
 	__u64 matrix[12];
 };
 
+/* for AMDGPU_INFO_DOORBELL query */
+struct drm_amdgpu_info_doorbell {
+	__u32 index_start;
+	/* could be equal to index_start */
+	__u32 index_end;
+	/* aggregated doorbell, 0 for disable */
+	__u32 agdb_enable;
+	/* if agdb_enable, it is a value in [index_start, index_end] */
+	__u32 agdb_offset;
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.43.0

[PATCH 12/14] drm/amdgpu/vcn: handle interrupt received from fw

[David (Ming Qiang) Wu]

From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>

User queue fence driver handles the interrupts received
from the VCN firmware in case of user queue submissions,
changes are done in VCN interrupt handler to process the
received interrupt and pass to appropriate fence driver.

v2 - handle the case when kernel and usermode queues are active
     to service the interrrupt. (Alex)

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 37 +++++++++++++++++--------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index d2744cd4c865..c246a932a4e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -32,6 +32,7 @@
 #include "vcn_v2_0.h"
 #include "mmsch_v4_0.h"
 #include "vcn_v4_0_5.h"
+#include "amdgpu_userq_fence.h"
 
 #include "vcn/vcn_4_0_5_offset.h"
 #include "vcn/vcn_4_0_5_sh_mask.h"
@@ -1666,6 +1667,7 @@ static int vcn_v4_0_5_set_pg_state(struct amdgpu_vcn_inst *vinst,
 static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
 		struct amdgpu_iv_entry *entry)
 {
+	u32 doorbell_offset = entry->src_data[0];
 	uint32_t ip_instance;
 
 	switch (entry->client_id) {
@@ -1682,17 +1684,30 @@ static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgp
 
 	DRM_DEBUG("IH: VCN TRAP\n");
 
-	switch (entry->src_id) {
-	case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
-		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
-		break;
-	case VCN_4_0__SRCID_UVD_POISON:
-		amdgpu_vcn_process_poison_irq(adev, source, entry);
-		break;
-	default:
-		DRM_ERROR("Unhandled interrupt: %d %d\n",
-			  entry->src_id, entry->src_data[0]);
-		break;
+	if (doorbell_offset) {
+		struct xarray *xa = &adev->userq_xa;
+		struct amdgpu_userq_fence_driver *fence_drv;
+		unsigned long flags;
+
+		xa_lock_irqsave(xa, flags);
+		fence_drv = xa_load(xa, doorbell_offset);
+		if (fence_drv)
+			amdgpu_userq_fence_driver_process(fence_drv);
+
+		xa_unlock_irqrestore(xa, flags);
+	} else {
+		switch (entry->src_id) {
+		case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+			amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
+			break;
+		case VCN_4_0__SRCID_UVD_POISON:
+			amdgpu_vcn_process_poison_irq(adev, source, entry);
+			break;
+		default:
+			DRM_ERROR("Unhandled interrupt: %d %d\n",
+				  entry->src_id, entry->src_data[0]);
+			break;
+		}
 	}
 
 	return 0;
-- 
2.43.0

[PATCH 13/14] drm/amdgpu/umsch: userq suspend and resume context

[David (Ming Qiang) Wu]

UMSCH supports context suspend and resume whenever buffer
evection and restore is initiated.

Using new function format due to api change (David)

V2 - remove powergating call as it is not needed for resume
     use drv_err() instead of DRM_ERROR()

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 52 +++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h | 24 +++++++
 drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c   | 66 ++++++++++++++++++++
 3 files changed, 142 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 5a9589b56534..20e9b81fbe06 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -656,6 +656,56 @@ static void amdgpu_umsch_destroy_queue(struct amdgpu_usermode_queue *queue)
 	mutex_unlock(&umsch->mutex_hidden);
 }
 
+static int amdgpu_umsch_queue_preempt(struct amdgpu_usermode_queue *queue)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	struct amdgpu_userq_obj *ctx = &queue->fw_obj;
+	struct amdgpu_userq_obj *sfence = &queue->suspend_fence_obj;
+	struct umsch_suspend args;
+	int r;
+
+	memset(&args, 0, sizeof(struct umsch_suspend));
+	args.context_csa_addr = ctx->gpu_addr + PAGE_SIZE;
+	args.suspend_fence_addr = sfence->gpu_addr;
+	args.suspend_fence_value = umsch->ring.fence_drv.sync_seq + 1;
+
+	amdgpu_umsch_mm_lock(&adev->umsch_mm);
+	r = umsch->funcs->suspend_queue_ctx(umsch, &args);
+	amdgpu_umsch_mm_unlock(&adev->umsch_mm);
+	if (r)
+		dev_err(adev->dev, "Failed to suspend queue for IP %d err %d.\n",
+			queue->queue_type, r);
+
+	return r;
+}
+
+static int amdgpu_umsch_queue_restore(struct amdgpu_usermode_queue *queue)
+{
+	struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
+	struct amdgpu_device *adev = uq_mgr->adev;
+	struct amdgpu_umsch_mm *umsch = &adev->umsch_mm;
+	struct amdgpu_userq_obj *ctx = &queue->fw_obj;
+	struct umsch_resume args;
+	int r;
+
+	memset(&args, 0, sizeof(struct umsch_resume));
+	args.context_csa_addr = ctx->gpu_addr + PAGE_SIZE;
+	if (queue->queue_type == AMDGPU_HW_IP_VCN_ENC)
+		args.engine_type = UMSCH_SWIP_ENGINE_TYPE_VCN;
+
+	args.resume_option = RESUME_CONTEXT;
+	amdgpu_umsch_mm_lock(&adev->umsch_mm);
+	r = umsch->funcs->resume_queue_ctx(umsch, &args);
+	amdgpu_umsch_mm_unlock(&adev->umsch_mm);
+	if (r)
+		dev_err(adev->dev, "Failed to resume queue for IP %d err %d.\n",
+			queue->queue_type, r);
+
+	return r;
+}
+
 void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm)
 {
 #if defined(CONFIG_DEBUG_FS)
@@ -781,4 +831,6 @@ const struct amdgpu_userq_funcs userq_umsch_4_0_funcs = {
 	.mqd_destroy = amdgpu_umsch_destroy_queue,
 	.map = amdgpu_umsch_userq_map,
 	.unmap = amdgpu_umsch_userq_unmap,
+	.preempt = amdgpu_umsch_queue_preempt,
+	.restore = amdgpu_umsch_queue_restore,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
index 6b827c92e817..cbe1ec7363a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
@@ -41,6 +41,11 @@ enum UMSCH_CONTEXT_PRIORITY_LEVEL {
 	CONTEXT_PRIORITY_NUM_LEVELS
 };
 
+enum UMSCH_RESUME_OPTIONS {
+	RESUME_CONTEXT = 0,
+	RESUME_ENGINE_SCHEDULE = 1,
+};
+
 struct umsch_mm_set_resource_input {
 	uint32_t vmid_mask_mm_vcn;
 	uint32_t vmid_mask_mm_vpe;
@@ -117,6 +122,20 @@ struct MQD_INFO {
 	uint32_t vmid;
 };
 
+struct umsch_suspend {
+	uint64_t context_csa_addr;
+	uint64_t suspend_fence_addr;
+	uint32_t suspend_fence_value;
+	uint32_t context_csa_array_index;
+};
+
+struct umsch_resume {
+	enum UMSCH_RESUME_OPTIONS resume_option;
+	uint64_t context_csa_addr;
+	enum UMSCH_SWIP_ENGINE_TYPE engine_type;
+	uint32_t context_csa_array_index;
+};
+
 struct amdgpu_umsch_mm;
 
 struct umsch_mm_funcs {
@@ -132,6 +151,11 @@ struct umsch_mm_funcs {
 	int (*ring_start)(struct amdgpu_umsch_mm *umsch);
 	int (*ring_stop)(struct amdgpu_umsch_mm *umsch);
 	int (*ring_fini)(struct amdgpu_umsch_mm *umsch);
+	int (*suspend_queue_ctx)(struct amdgpu_umsch_mm *umsch,
+			    struct umsch_suspend *input);
+	int (*resume_queue_ctx)(struct amdgpu_umsch_mm *umsch,
+			    struct umsch_resume *input);
+
 };
 
 struct amdgpu_umsch_mm {
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 60d1fdfb2af5..c1e47ea8e82a 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -411,6 +411,70 @@ static int umsch_mm_v4_0_remove_queue(struct amdgpu_umsch_mm *umsch,
 	return 0;
 }
 
+static int umsch_mm_v4_0_suspend_context(struct amdgpu_umsch_mm *umsch,
+				      struct umsch_suspend *input_ptr)
+{
+	union UMSCHAPI__SUSPEND suspend = { 0 };
+	struct amdgpu_device *adev = umsch->ring.adev;
+	int r;
+
+	suspend.header.type = UMSCH_API_TYPE_SCHEDULER;
+	suspend.header.opcode = UMSCH_API_SUSPEND;
+	suspend.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+	suspend.context_csa_addr = input_ptr->context_csa_addr;
+	suspend.suspend_fence_addr = input_ptr->suspend_fence_addr;
+	suspend.suspend_fence_value = input_ptr->suspend_fence_value;
+
+	suspend.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
+	suspend.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
+
+	r = amdgpu_umsch_mm_submit_pkt(umsch, &suspend.max_dwords_in_api,
+				       API_FRAME_SIZE_IN_DWORDS);
+	if (r)
+		return r;
+
+	r = amdgpu_umsch_mm_query_fence(umsch);
+	if (r) {
+		dev_err(adev->dev, "UMSCH suspend queue: Failed ret %d\n", r);
+		return r;
+	}
+
+	return r;
+}
+
+static int umsch_mm_v4_0_resume_context(struct amdgpu_umsch_mm *umsch,
+				      struct umsch_resume *input_ptr)
+{
+	union UMSCHAPI__RESUME resume = { 0 };
+	struct amdgpu_device *adev = umsch->ring.adev;
+	int r;
+
+	resume.header.type = UMSCH_API_TYPE_SCHEDULER;
+	resume.header.opcode = UMSCH_API_RESUME;
+	resume.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
+
+	resume.resume_option = (enum UMSCH_RESUME_OPTION)input_ptr->resume_option;
+	resume.context_csa_addr = input_ptr->context_csa_addr;
+	resume.engine_type = (enum UMSCH_ENGINE_TYPE)input_ptr->engine_type;
+
+	resume.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
+	resume.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
+
+	r = amdgpu_umsch_mm_submit_pkt(umsch, &resume.max_dwords_in_api,
+				       API_FRAME_SIZE_IN_DWORDS);
+	if (r)
+		return r;
+
+	r = amdgpu_umsch_mm_query_fence(umsch);
+	if (r) {
+		dev_err(adev->dev, "UMSCH resume queue: Failed ret %d\n", r);
+		return r;
+	}
+
+	return r;
+}
+
 static int umsch_mm_v4_0_set_regs(struct amdgpu_umsch_mm *umsch)
 {
 	struct amdgpu_device *adev = container_of(umsch, struct amdgpu_device, umsch_mm);
@@ -431,6 +495,8 @@ static const struct umsch_mm_funcs umsch_mm_v4_0_funcs = {
 	.ring_init = amdgpu_umsch_mm_ring_init,
 	.ring_start = umsch_mm_v4_0_ring_start,
 	.ring_stop = umsch_mm_v4_0_ring_stop,
+	.suspend_queue_ctx = umsch_mm_v4_0_suspend_context,
+	.resume_queue_ctx = umsch_mm_v4_0_resume_context,
 };
 
 void umsch_mm_v4_0_set_funcs(struct amdgpu_umsch_mm *umsch)
-- 
2.43.0

[PATCH 14/14] drm/amdgpu/vcn: handle the suspend context interrupt

[David (Ming Qiang) Wu]

From: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>

For suspend context UMSCH expects the ack from host(vcn).
Queue is suspended then interrupt is sent to driver which
acks back with register update.

note there isn't any resume context interrupt.

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c       | 50 ++++++++++++++++---
 .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h | 10 ++++
 2 files changed, 52 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index c246a932a4e6..541d8c694a65 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -197,6 +197,18 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
 		if (r)
 			return r;
 
+		/* UMSCH SUSPEND  */
+		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
+				VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT0, &adev->vcn.inst[i].irq);
+		if (r)
+			return r;
+
+		/* UMSCH RESUME */
+		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
+				VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT1, &adev->vcn.inst[i].irq);
+		if (r)
+			return r;
+
 		ring = &adev->vcn.inst[i].ring_enc[0];
 		ring->use_doorbell = true;
 		if (amdgpu_sriov_vf(adev))
@@ -1668,6 +1680,7 @@ static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgp
 		struct amdgpu_iv_entry *entry)
 {
 	u32 doorbell_offset = entry->src_data[0];
+	uint32_t reg_data = 0;
 	uint32_t ip_instance;
 
 	switch (entry->client_id) {
@@ -1685,16 +1698,37 @@ static int vcn_v4_0_5_process_interrupt(struct amdgpu_device *adev, struct amdgp
 	DRM_DEBUG("IH: VCN TRAP\n");
 
 	if (doorbell_offset) {
-		struct xarray *xa = &adev->userq_xa;
-		struct amdgpu_userq_fence_driver *fence_drv;
-		unsigned long flags;
+		switch (entry->src_id) {
+		case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
+			struct xarray *xa = &adev->userq_xa;
+			u32 doorbell_offset = entry->src_data[0];
+			struct amdgpu_userq_fence_driver *fence_drv;
+			unsigned long flags;
 
-		xa_lock_irqsave(xa, flags);
-		fence_drv = xa_load(xa, doorbell_offset);
-		if (fence_drv)
-			amdgpu_userq_fence_driver_process(fence_drv);
+			xa_lock_irqsave(xa, flags);
+			fence_drv = xa_load(xa, doorbell_offset);
+			if (fence_drv)
+				amdgpu_userq_fence_driver_process(fence_drv);
 
-		xa_unlock_irqrestore(xa, flags);
+			xa_unlock_irqrestore(xa, flags);
+			break;
+		case VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT0:
+			reg_data = RREG32_SOC15(VCN, ip_instance, regVCN_UMSCH_SYS_INT_ACK);
+			reg_data |= (VCN_UMSCH_SYS_INT_ACK__INT0_MASK <<
+						 VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT); //INT0
+			WREG32_SOC15(VCN, ip_instance, regVCN_UMSCH_SYS_INT_ACK, reg_data);
+			break;
+		case VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT1:
+			reg_data = RREG32_SOC15(VCN, ip_instance, regVCN_UMSCH_SYS_INT_ACK);
+			reg_data |= (VCN_UMSCH_SYS_INT_ACK__INT1_MASK <<
+						 VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT); //INT1
+			WREG32_SOC15(VCN, ip_instance, regVCN_UMSCH_SYS_INT_ACK, reg_data);
+			break;
+		default:
+			DRM_ERROR("Unhandled interrupt: %d %d\n", entry->src_id,
+				      entry->src_data[0]);
+			break;
+		}
 	} else {
 		switch (entry->src_id) {
 		case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
diff --git a/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h
index 03cfa0517df2..994bc39e8810 100644
--- a/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h
+++ b/drivers/gpu/drm/amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h
@@ -41,4 +41,14 @@
 #define VCN_4_0__SRCID_UVD_POISON					160
 #define VCN_4_0__SRCID_DJPEG0_POISON					161
 #define VCN_4_0__SRCID_EJPEG0_POISON					162
+
+/* 0xa3  UMSCH FW to Host interrupt also Debug interrupt for MES register read illegal response*/
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT0		163
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT1		164  // 0xa4 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT2		165  // 0xa5 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT3		166  // 0xa6 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT4		167  // 0xa7 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT5		168  // 0xa8 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT6		169  // 0xa9 UMSCH FW to Host interrupt
+#define VCN_4_0_0__SRCID__UVD_MESFW2DRV_INT7		170  // 0xaa UMSCH FW to Host interrupt
 #endif
-- 
2.43.0

Re: [PATCH 00/14] user queue support for VCN 4.0.5

[Saleemkhan]

[-- Attachment #1: Type: text/plain, Size: 2305 bytes --]

Hi David, Leo,


Thank you for the UMSCH patches.

Are the  UMSCH and  vcn firmware are upstreamed ?
I want to try this on Strix.


Regards,

Saleem



On 11 February 2026 3:17:15 am IST, "David (Ming Qiang) Wu" <David.Wu3@amd.com> wrote:
>add user queue support for VCN 4.0.5
>
>David (Ming Qiang) Wu (10):
>  amdgpu: add global aggregated doorbell bo
>  drm/amdgpu: add AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL
>  drm/amdgpu/userq: add doorbell size for VCN and VPE
>  drm/amdgpu: use amdgpu_user_queue instead of amdgpu_umsch_mm
>  amdgpu/umsch: Add VCN IP init to umsch driver
>  drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to be common
>  drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping
>  drm/amdgpu/umsch: user queue support for vcn
>  drm/amdgpu: add AMDGPU_INFO_DOORBELL
>  drm/amdgpu/umsch: userq suspend and resume context
>
>Saleemkhan Jamadar (4):
>  amdgpu/umsch: Update UMSCH interface and mqd structure
>  drm/amdgpu/vcn: changes when kernel queue is disabled
>  drm/amdgpu/vcn: handle interrupt received from fw
>  drm/amdgpu/vcn: handle the suspend context interrupt
>
> drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |   2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |   2 +-
> .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  16 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  10 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c       |   2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c       |  18 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 300 +++++++++++++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h  |  43 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c     |  69 +++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h     |   4 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h       |   4 +
> drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    |  90 +-----
> drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c    |  75 ++++-
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c       | 122 +++++--
> .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h |  10 +
> .../drm/amd/include/umsch_mm_4_0_api_def.h    |  12 +-
> include/uapi/drm/amdgpu_drm.h                 |  14 +
> 18 files changed, 646 insertions(+), 151 deletions(-)
>
>-- 
>2.43.0
>

--
Saleem

[-- Attachment #2: Type: text/html, Size: 2690 bytes --]

Re: [PATCH 00/14] user queue support for VCN 4.0.5

[Wu, David]

[-- Attachment #1: Type: text/plain, Size: 2620 bytes --]

On 2/18/2026 10:37 AM, Saleemkhan wrote:
> Hi David, Leo,
>
>
> Thank you for the UMSCH patches.
>
> Are the  UMSCH and  vcn firmware are upstreamed ?
> I want to try this on Strix.
>
not yet - we are working on it for kernel first. A few patches here need 
to be reviewed/acked, then cherry-picking one patch which is in another 
branch as dependency. I have firmwares used for testing and branches for 
mesa and libdrm to support the kernel features, but not ready for 
upstreaming.

David
>
> Regards,
>
> Saleem
>
>
>
> On 11 February 2026 3:17:15 am IST, "David (Ming Qiang) Wu" 
> <David.Wu3@amd.com> wrote:
>
>     add user queue support for VCN 4.0.5 David (Ming Qiang) Wu (10):
>     amdgpu: add global aggregated doorbell bo drm/amdgpu: add
>     AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL drm/amdgpu/userq: add
>     doorbell size for VCN and VPE drm/amdgpu: use amdgpu_user_queue
>     instead of amdgpu_umsch_mm amdgpu/umsch: Add VCN IP init to umsch
>     driver drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to
>     be common drm/amdgpu/userq: rework on
>     amdgpu_userq_create_wptr_mapping drm/amdgpu/umsch: user queue
>     support for vcn drm/amdgpu: add AMDGPU_INFO_DOORBELL
>     drm/amdgpu/umsch: userq suspend and resume context Saleemkhan
>     Jamadar (4): amdgpu/umsch: Update UMSCH interface and mqd
>     structure drm/amdgpu/vcn: changes when kernel queue is disabled
>     drm/amdgpu/vcn: handle interrupt received from fw drm/amdgpu/vcn:
>     handle the suspend context interrupt
>     drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +-
>     drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
>     drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
>     .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c | 16 +
>     drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 -
>     drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +
>     drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 ++
>     drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 300
>     +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h |
>     43 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 69 +++-
>     drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 4 +
>     drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +
>     drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 90 +-----
>     drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 75 ++++-
>     drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 122 +++++--
>     .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h | 10 +
>     .../drm/amd/include/umsch_mm_4_0_api_def.h | 12 +-
>     include/uapi/drm/amdgpu_drm.h | 14 + 18 files changed, 646
>     insertions(+), 151 deletions(-)
>
> --
> Saleem

[-- Attachment #2: Type: text/html, Size: 3657 bytes --]

Re: [PATCH 00/14] user queue support for VCN 4.0.5

[Saleemkhan]

[-- Attachment #1: Type: text/plain, Size: 2922 bytes --]

Pls share the firmwares I would like to try them with current patches.

Regards,
Saleem


On 18 February 2026 11:43:10 pm IST, "Wu, David" <davidwu2@amd.com> wrote:
>On 2/18/2026 10:37 AM, Saleemkhan wrote:
>> Hi David, Leo,
>> 
>> 
>> Thank you for the UMSCH patches.
>> 
>> Are the  UMSCH and  vcn firmware are upstreamed ?
>> I want to try this on Strix.
>> 
>not yet - we are working on it for kernel first. A few patches here need to be reviewed/acked, then cherry-picking one patch which is in another branch as dependency. I have firmwares used for testing and branches for mesa and libdrm to support the kernel features, but not ready for upstreaming.
>
>David
>> 
>> Regards,
>> 
>> Saleem
>> 
>> 
>> 
>> On 11 February 2026 3:17:15 am IST, "David (Ming Qiang) Wu" <David.Wu3@amd.com> wrote:
>> 
>>     add user queue support for VCN 4.0.5 David (Ming Qiang) Wu (10):
>>     amdgpu: add global aggregated doorbell bo drm/amdgpu: add
>>     AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL drm/amdgpu/userq: add
>>     doorbell size for VCN and VPE drm/amdgpu: use amdgpu_user_queue
>>     instead of amdgpu_umsch_mm amdgpu/umsch: Add VCN IP init to umsch
>>     driver drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to
>>     be common drm/amdgpu/userq: rework on
>>     amdgpu_userq_create_wptr_mapping drm/amdgpu/umsch: user queue
>>     support for vcn drm/amdgpu: add AMDGPU_INFO_DOORBELL
>>     drm/amdgpu/umsch: userq suspend and resume context Saleemkhan
>>     Jamadar (4): amdgpu/umsch: Update UMSCH interface and mqd
>>     structure drm/amdgpu/vcn: changes when kernel queue is disabled
>>     drm/amdgpu/vcn: handle interrupt received from fw drm/amdgpu/vcn:
>>     handle the suspend context interrupt
>>     drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +-
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +-
>>     .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c | 16 +
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 -
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 ++
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 300
>>     +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h |
>>     43 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 69 +++-
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 4 +
>>     drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +
>>     drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 90 +-----
>>     drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 75 ++++-
>>     drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 122 +++++--
>>     .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h | 10 +
>>     .../drm/amd/include/umsch_mm_4_0_api_def.h | 12 +-
>>     include/uapi/drm/amdgpu_drm.h | 14 + 18 files changed, 646
>>     insertions(+), 151 deletions(-)
>> 
>> --
>> Saleem

--
Saleem

[-- Attachment #2: Type: text/html, Size: 4176 bytes --]

Re: [PATCH 00/14] user queue support for VCN 4.0.5

[David Wu]

ping...

On 2026-02-10 16:47, David (Ming Qiang) Wu wrote:
> add user queue support for VCN 4.0.5
>
> David (Ming Qiang) Wu (10):
>    amdgpu: add global aggregated doorbell bo
>    drm/amdgpu: add AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL
>    drm/amdgpu/userq: add doorbell size for VCN and VPE
>    drm/amdgpu: use amdgpu_user_queue instead of amdgpu_umsch_mm
>    amdgpu/umsch: Add VCN IP init to umsch driver
>    drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to be common
>    drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping
>    drm/amdgpu/umsch: user queue support for vcn
>    drm/amdgpu: add AMDGPU_INFO_DOORBELL
>    drm/amdgpu/umsch: userq suspend and resume context
>
> Saleemkhan Jamadar (4):
>    amdgpu/umsch: Update UMSCH interface and mqd structure
>    drm/amdgpu/vcn: changes when kernel queue is disabled
>    drm/amdgpu/vcn: handle interrupt received from fw
>    drm/amdgpu/vcn: handle the suspend context interrupt
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |   2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |   2 +-
>   .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  16 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  10 -
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c       |   2 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c       |  18 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 300 +++++++++++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h  |  43 ++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c     |  69 +++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h     |   4 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h       |   4 +
>   drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    |  90 +-----
>   drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c    |  75 ++++-
>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c       | 122 +++++--
>   .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h |  10 +
>   .../drm/amd/include/umsch_mm_4_0_api_def.h    |  12 +-
>   include/uapi/drm/amdgpu_drm.h                 |  14 +
>   18 files changed, 646 insertions(+), 151 deletions(-)
>

Re: [PATCH 00/14] user queue support for VCN 4.0.5

[Wu, David]

[-- Attachment #1: Type: text/plain, Size: 2346 bytes --]

ping...

On 2/19/2026 1:00 PM, David Wu wrote:
> ping...
>
> On 2026-02-10 16:47, David (Ming Qiang) Wu wrote:
>> add user queue support for VCN 4.0.5
>>
>> David (Ming Qiang) Wu (10):
>>    amdgpu: add global aggregated doorbell bo
>>    drm/amdgpu: add AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL
>>    drm/amdgpu/userq: add doorbell size for VCN and VPE
>>    drm/amdgpu: use amdgpu_user_queue instead of amdgpu_umsch_mm
>>    amdgpu/umsch: Add VCN IP init to umsch driver
>>    drm/amdgpu/userq: change mes_userq_create_wptr_mapping() to be common
>>    drm/amdgpu/userq: rework on amdgpu_userq_create_wptr_mapping
>>    drm/amdgpu/umsch: user queue support for vcn
>>    drm/amdgpu: add AMDGPU_INFO_DOORBELL
>>    drm/amdgpu/umsch: userq suspend and resume context
>>
>> Saleemkhan Jamadar (4):
>>    amdgpu/umsch: Update UMSCH interface and mqd structure
>>    drm/amdgpu/vcn: changes when kernel queue is disabled
>>    drm/amdgpu/vcn: handle interrupt received from fw
>>    drm/amdgpu/vcn: handle the suspend context interrupt
>>
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h           |   4 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c   |   2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |   2 +-
>>   .../gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c  |  16 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c       |  10 -
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c       |   2 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c       |  18 ++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c  | 300 +++++++++++++++++-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h  |  43 ++-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c     |  69 +++-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h     |   4 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h       |   4 +
>>   drivers/gpu/drm/amd/amdgpu/mes_userqueue.c    |  90 +-----
>>   drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c    |  75 ++++-
>>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c       | 122 +++++--
>>   .../amd/include/ivsrcid/vcn/irqsrcs_vcn_4_0.h |  10 +
>>   .../drm/amd/include/umsch_mm_4_0_api_def.h    |  12 +-
>>   include/uapi/drm/amdgpu_drm.h                 |  14 +
>>   18 files changed, 646 insertions(+), 151 deletions(-)
>>

[-- Attachment #2: Type: text/html, Size: 4070 bytes --]