* [PATCH 0/8] Improvements for IB handling V9
@ 2026-02-16 21:13 Alex Deucher
2026-02-16 21:13 ` [PATCH 1/8] drm/amdgpu: rework ring reset backup and reemit v9 Alex Deucher
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher
This set contains a number of bug fixes and cleanups for
IB handling that I worked on over the holidays. Many of
the original patches have landed now. These are the
remaining patches.
Patch 1:
Rework the backup and reemit code for per ring reset so that
we can safely reemit repeatedly. This removes the current
single reemit limit currently in place. V9 moves this to the start
of the series as its dependencies have been reviewed and
applied.
Patches 2-4:
Removes the direct submit path for IBs and requires
that all IB submissions use a job structure. This
greatly simplifies the IB submission code. V2 uses
GFP_ATOMIC when in reset. V3 sqaushes all of the
IP changes into one patch. Not sure there is much
value breaking this out per IP. V4 uses the pool type
to determine the alloc flags. No changes in V8.
V9 fixes some typos in the gfx9 RAS IB handling.
Patches 5-8:
Improvements for adapter resets. Properly add the bad job
back to the pending list so we can stop calling
drm_sched_stop/start(). Return the proper error number
in the CS IOCTL when the context is guilty. Now that that
is handled properly we can call drm_sched_increase_karma()
for ring resets as well. Properly set the error on the the
timedout fence for adapter resets. These changes also resulted
in a small clean up the the VCN reset helpler. No changes in
V9.
Alex Deucher (8):
drm/amdgpu: rework ring reset backup and reemit v9
drm/amdgpu/job: use GFP_ATOMIC while in gpu reset
drm/amdgpu: switch all IPs to using job for IBs
drm/amdgpu: require a job to schedule an IB
drm/amdgpu: plumb timedout fence through to force completion
drm/amdgpu: simplify VCN reset helper
drm/amdgpu/cs: return -ETIME for guilty contexts
drm/amdgpu: Call drm_sched_increase_karma() for ring resets
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 125 +++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 127 ++++++++----------
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 20 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 46 ++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 26 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 52 +++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 37 +++---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 31 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 24 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 139 ++++++++++----------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 139 ++++++++++----------
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 27 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 38 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 38 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 38 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 38 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 37 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 36 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 36 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 36 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 36 ++---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 +-
39 files changed, 689 insertions(+), 671 deletions(-)
--
2.53.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/8] drm/amdgpu: rework ring reset backup and reemit v9
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 2/8] drm/amdgpu/job: use GFP_ATOMIC while in gpu reset Alex Deucher
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
Store the start wptr and ib size in the IB fence. On queue
reset, save the ring contents of all IBs.
For reemit, reemit the entire IB state for non-guilty contexts.
For guilty contexts, replace the IB submission with nops, but reemit
the rest. Split the reemit per fence and when we reemit, update the
wptr with the new values from reemit. This allows us to reemit jobs
repeatedly as the wptrs get properly updated each time.
v2: further simplify the logic
v3: reemit vm state, not just vm fence
v4: just nop the IB and possibly the VM portion of the submission
v5: simplify the vm fence check
v6: split the vm and ib fences
v7: fix commit message
v8: use wptr rather than count_dw to calculate offsets
v9: fix missing documenation update spotted by the kernel test robot
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 99 +++++++++--------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 26 ++++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 46 +++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 20 ++---
4 files changed, 74 insertions(+), 117 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 07568516c5066..d209591e3710a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -89,16 +89,6 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
return seq;
}
-static void amdgpu_fence_save_fence_wptr_start(struct amdgpu_fence *af)
-{
- af->fence_wptr_start = af->ring->wptr;
-}
-
-static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af)
-{
- af->fence_wptr_end = af->ring->wptr;
-}
-
/**
* amdgpu_fence_emit - emit a fence on the requested ring
*
@@ -124,11 +114,9 @@ void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
&ring->fence_drv.lock,
adev->fence_context + ring->idx, seq);
- amdgpu_fence_save_fence_wptr_start(af);
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT);
- amdgpu_fence_save_fence_wptr_end(af);
- amdgpu_fence_save_wptr(af);
+
pm_runtime_get_noresume(adev_to_drm(adev)->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
if (unlikely(rcu_dereference_protected(*ptr, 1))) {
@@ -240,7 +228,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
do {
struct dma_fence *fence, **ptr;
- struct amdgpu_fence *am_fence;
++last_seq;
last_seq &= drv->num_fences_mask;
@@ -253,12 +240,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
if (!fence)
continue;
- /* Save the wptr in the fence driver so we know what the last processed
- * wptr was. This is required for re-emitting the ring state for
- * queues that are reset but are not guilty and thus have no guilty fence.
- */
- am_fence = container_of(fence, struct amdgpu_fence, base);
- drv->signalled_wptr = am_fence->wptr;
dma_fence_signal(fence);
dma_fence_put(fence);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -707,25 +688,29 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
*/
/**
- * amdgpu_fence_driver_update_timedout_fence_state - Update fence state and set errors
+ * amdgpu_ring_set_fence_errors_and_reemit - Set dma_fence errors and reemit
*
- * @af: fence of the ring to update
+ * @ring: the ring to operate on
+ * @guilty_fence: fence of the ring to update
*
*/
-void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af)
+void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence)
{
struct dma_fence *unprocessed;
struct dma_fence __rcu **ptr;
struct amdgpu_fence *fence;
- struct amdgpu_ring *ring = af->ring;
unsigned long flags;
u32 seq, last_seq;
- bool reemitted = false;
+ unsigned int i;
+ bool is_guilty_fence;
+ bool is_guilty_context;
last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask;
seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask;
- /* mark all fences from the guilty context with an error */
+ ring->reemit = true;
+ amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy);
spin_lock_irqsave(&ring->fence_drv.lock, flags);
do {
last_seq++;
@@ -737,39 +722,45 @@ void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af)
if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) {
fence = container_of(unprocessed, struct amdgpu_fence, base);
+ is_guilty_fence = fence == guilty_fence;
+ is_guilty_context = fence->context == guilty_fence->context;
- if (fence->reemitted > 1)
- reemitted = true;
- else if (fence == af)
+ /* mark all fences from the guilty context with an error */
+ if (is_guilty_fence)
dma_fence_set_error(&fence->base, -ETIME);
- else if (fence->context == af->context)
+ else if (is_guilty_context)
dma_fence_set_error(&fence->base, -ECANCELED);
+
+ /* reemit the packet stream and update wptrs */
+ fence->ib_wptr = ring->wptr;
+ for (i = 0; i < fence->ib_dw_size; i++) {
+ /* Skip the IB(s) for the guilty context. */
+ if (is_guilty_context &&
+ i >= fence->skip_ib_dw_start_offset &&
+ i < fence->skip_ib_dw_end_offset)
+ amdgpu_ring_write(ring, ring->funcs->nop);
+ else
+ amdgpu_ring_write(ring,
+ ring->ring_backup[fence->backup_idx + i]);
+ }
}
rcu_read_unlock();
} while (last_seq != seq);
spin_unlock_irqrestore(&ring->fence_drv.lock, flags);
-
- if (reemitted) {
- /* if we've already reemitted once then just cancel everything */
- amdgpu_fence_driver_force_completion(af->ring);
- af->ring->ring_backup_entries_to_copy = 0;
- }
-}
-
-void amdgpu_fence_save_wptr(struct amdgpu_fence *af)
-{
- af->wptr = af->ring->wptr;
+ amdgpu_ring_commit(ring);
+ ring->reemit = false;
}
static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring,
- u64 start_wptr, u64 end_wptr)
+ struct amdgpu_fence *af)
{
- unsigned int first_idx = start_wptr & ring->buf_mask;
- unsigned int last_idx = end_wptr & ring->buf_mask;
+ unsigned int first_idx = af->ib_wptr & ring->buf_mask;
+ unsigned int dw_size = af->ib_dw_size;
unsigned int i;
+ af->backup_idx = ring->ring_backup_entries_to_copy;
/* Backup the contents of the ring buffer. */
- for (i = first_idx; i != last_idx; ++i, i &= ring->buf_mask)
+ for (i = first_idx; dw_size > 0; ++i, i &= ring->buf_mask, --dw_size)
ring->ring_backup[ring->ring_backup_entries_to_copy++] = ring->ring[i];
}
@@ -779,12 +770,10 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
struct dma_fence *unprocessed;
struct dma_fence __rcu **ptr;
struct amdgpu_fence *fence;
- u64 wptr;
u32 seq, last_seq;
last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask;
seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask;
- wptr = ring->fence_drv.signalled_wptr;
ring->ring_backup_entries_to_copy = 0;
do {
@@ -798,21 +787,7 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
if (unprocessed && !dma_fence_is_signaled(unprocessed)) {
fence = container_of(unprocessed, struct amdgpu_fence, base);
- /* save everything if the ring is not guilty, otherwise
- * just save the content from other contexts.
- */
- if (!fence->reemitted &&
- (!guilty_fence || (fence->context != guilty_fence->context))) {
- amdgpu_ring_backup_unprocessed_command(ring, wptr,
- fence->wptr);
- } else if (!fence->reemitted) {
- /* always save the fence */
- amdgpu_ring_backup_unprocessed_command(ring,
- fence->fence_wptr_start,
- fence->fence_wptr_end);
- }
- wptr = fence->wptr;
- fence->reemitted++;
+ amdgpu_ring_backup_unprocessed_command(ring, fence);
}
rcu_read_unlock();
} while (last_seq != seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index eb92c96d290b6..f1ed4a436f5b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -129,6 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
struct amdgpu_ib *ib = &ibs[0];
struct dma_fence *tmp = NULL;
struct amdgpu_fence *af;
+ struct amdgpu_fence *vm_af;
bool need_ctx_switch;
struct amdgpu_vm *vm;
uint64_t fence_ctx;
@@ -215,9 +216,17 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
dma_fence_put(tmp);
}
- if (job)
+ if (job) {
+ vm_af = job->hw_vm_fence;
+ /* VM sequence */
+ vm_af->ib_wptr = ring->wptr;
amdgpu_vm_flush(ring, job, need_pipe_sync);
+ vm_af->ib_dw_size =
+ amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr);
+ }
+ /* IB sequence */
+ af->ib_wptr = ring->wptr;
amdgpu_ring_ib_begin(ring);
if (ring->funcs->insert_start)
@@ -238,6 +247,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
cond_exec = amdgpu_ring_init_cond_exec(ring,
ring->cond_exe_gpu_addr);
+ /* Skip the IB for guilty contexts */
+ af->skip_ib_dw_start_offset =
+ amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
amdgpu_device_flush_hdp(adev, ring);
if (need_ctx_switch)
@@ -276,6 +288,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
amdgpu_ring_emit_frame_cntl(ring, false, secure);
amdgpu_device_invalidate_hdp(adev, ring);
+ /* Skip the IB for guilty contexts */
+ af->skip_ib_dw_end_offset =
+ amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
@@ -312,13 +327,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
ring->funcs->emit_wave_limit(ring, false);
amdgpu_ring_ib_end(ring);
- /* Save the wptr associated with this fence.
- * This must be last for resets to work properly
- * as we need to save the wptr associated with this
- * fence so we know what rings contents to backup
- * after we reset the queue.
- */
- amdgpu_fence_save_wptr(af);
+
+ af->ib_dw_size = amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr);
amdgpu_ring_commit(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 129ad51386535..83750ab4e81b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -90,10 +90,13 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
/* Make sure we aren't trying to allocate more space
- * than the maximum for one submission
+ * than the maximum for one submission. Skip for reemit
+ * since we may be reemitting several submissions.
*/
- if (WARN_ON_ONCE(ndw > ring->max_dw))
- return -ENOMEM;
+ if (!ring->reemit) {
+ if (WARN_ON_ONCE(ndw > ring->max_dw))
+ return -ENOMEM;
+ }
ring->count_dw = ndw;
ring->wptr_old = ring->wptr;
@@ -104,29 +107,6 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
return 0;
}
-/**
- * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit
- *
- * @ring: amdgpu_ring structure holding ring information
- * @ndw: number of dwords to allocate in the ring buffer
- *
- * Allocate @ndw dwords in the ring buffer (all asics).
- * doesn't check the max_dw limit as we may be reemitting
- * several submissions.
- */
-static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
-{
- /* Align requested size with padding so unlock_commit can
- * pad safely */
- ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
-
- ring->count_dw = ndw;
- ring->wptr_old = ring->wptr;
-
- if (ring->funcs->begin_use)
- ring->funcs->begin_use(ring);
-}
-
/**
* amdgpu_ring_insert_nop - insert NOP packets
*
@@ -875,7 +855,6 @@ void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
struct amdgpu_fence *guilty_fence)
{
- unsigned int i;
int r;
/* verify that the ring is functional */
@@ -883,16 +862,9 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
if (r)
return r;
- /* set an error on all fences from the context */
- if (guilty_fence)
- amdgpu_fence_driver_update_timedout_fence_state(guilty_fence);
- /* Re-emit the non-guilty commands */
- if (ring->ring_backup_entries_to_copy) {
- amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy);
- for (i = 0; i < ring->ring_backup_entries_to_copy; i++)
- amdgpu_ring_write(ring, ring->ring_backup[i]);
- amdgpu_ring_commit(ring);
- }
+ /* set an error on all fences from the context and reemit */
+ amdgpu_ring_set_fence_errors_and_reemit(ring, guilty_fence);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 5a82db0888f0a..ce5af137ee400 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -121,7 +121,6 @@ struct amdgpu_fence_driver {
/* sync_seq is protected by ring emission lock */
uint32_t sync_seq;
atomic_t last_seq;
- u64 signalled_wptr;
bool initialized;
struct amdgpu_irq_src *irq_src;
unsigned irq_type;
@@ -146,23 +145,23 @@ struct amdgpu_fence {
struct amdgpu_ring *ring;
ktime_t start_timestamp;
- /* wptr for the total submission for resets */
- u64 wptr;
+ /* location and size of the IB */
+ u64 ib_wptr;
+ unsigned int ib_dw_size;
+ unsigned int skip_ib_dw_start_offset;
+ unsigned int skip_ib_dw_end_offset;
/* fence context for resets */
u64 context;
- /* has this fence been reemitted */
- unsigned int reemitted;
- /* wptr for the fence for the submission */
- u64 fence_wptr_start;
- u64 fence_wptr_end;
+ /* idx for ring backups */
+ unsigned int backup_idx;
};
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
-void amdgpu_fence_driver_update_timedout_fence_state(struct amdgpu_fence *af);
-void amdgpu_fence_save_wptr(struct amdgpu_fence *af);
+void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
+ struct amdgpu_fence *guilty_fence);
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
@@ -313,6 +312,7 @@ struct amdgpu_ring {
/* backups for resets */
uint32_t *ring_backup;
unsigned int ring_backup_entries_to_copy;
+ bool reemit;
unsigned rptr_offs;
u64 rptr_gpu_addr;
u32 *rptr_cpu_addr;
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/8] drm/amdgpu/job: use GFP_ATOMIC while in gpu reset
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
2026-02-16 21:13 ` [PATCH 1/8] drm/amdgpu: rework ring reset backup and reemit v9 Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 3/8] drm/amdgpu: switch all IPs to using job for IBs Alex Deucher
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
If we need to allocate a job during GPU reset, use
GFP_ATOMIC rather than GFP_KERNEL.
v2: use pool type it determine alloc flags.
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 13 ++++++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 5 +++--
7 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 3bfd79c89df32..823b92005689a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -671,7 +671,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
goto err;
}
- ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0);
+ ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job, 0, false);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f3b5bcdbf2ae6..6b494e4e8c0e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -282,7 +282,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
for (i = 0; i < p->gang_size; ++i) {
ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
num_ibs[i], &p->jobs[i],
- p->filp->client_id);
+ p->filp->client_id, false);
if (ret)
goto free_all_kdata;
switch (p->adev->enforce_isolation[fpriv->xcp_id]) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index f1ed4a436f5b4..80565c4a31bdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -69,7 +69,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
if (size) {
r = amdgpu_sa_bo_new(&adev->ib_pools[pool_type],
- &ib->sa_bo, size);
+ &ib->sa_bo, size, pool_type == AMDGPU_IB_POOL_DIRECT);
if (r) {
dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 55172c2dcc355..95aa87b4406eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -188,7 +188,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct drm_sched_entity *entity, void *owner,
unsigned int num_ibs, struct amdgpu_job **job,
- u64 drm_client_id)
+ u64 drm_client_id, bool need_atomic)
{
struct amdgpu_fence *af;
int r;
@@ -196,18 +196,21 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
if (num_ibs == 0)
return -EINVAL;
- *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
+ *job = kzalloc(struct_size(*job, ibs, num_ibs),
+ need_atomic ? GFP_ATOMIC : GFP_KERNEL);
if (!*job)
return -ENOMEM;
- af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
+ af = kzalloc(sizeof(struct amdgpu_fence),
+ need_atomic ? GFP_ATOMIC : GFP_KERNEL);
if (!af) {
r = -ENOMEM;
goto err_job;
}
(*job)->hw_fence = af;
- af = kzalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
+ af = kzalloc(sizeof(struct amdgpu_fence),
+ need_atomic ? GFP_ATOMIC : GFP_KERNEL);
if (!af) {
r = -ENOMEM;
goto err_fence;
@@ -246,7 +249,7 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
int r;
r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job,
- k_job_id);
+ k_job_id, pool_type == AMDGPU_IB_POOL_DIRECT);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index 56a88e14a0448..9de2cae966fea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -113,7 +113,7 @@ static inline struct amdgpu_ring *amdgpu_job_ring(struct amdgpu_job *job)
int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct drm_sched_entity *entity, void *owner,
unsigned int num_ibs, struct amdgpu_job **job,
- u64 drm_client_id);
+ u64 drm_client_id, bool need_atomic);
int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
struct drm_sched_entity *entity, void *owner,
size_t size, enum amdgpu_ib_pool_type pool_type,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 912c9afaf9e11..8abff5fdae81d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -341,7 +341,7 @@ int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
struct drm_suballoc **sa_bo,
- unsigned int size);
+ unsigned int size, bool need_atomic);
void amdgpu_sa_bo_free(struct drm_suballoc **sa_bo,
struct dma_fence *fence);
#if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index 39070b2a4c04f..1d44b95de7e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -78,10 +78,11 @@ void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
struct drm_suballoc **sa_bo,
- unsigned int size)
+ unsigned int size, bool need_atomic)
{
struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
- GFP_KERNEL, false, 0);
+ need_atomic ? GFP_ATOMIC : GFP_KERNEL,
+ false, 0);
if (IS_ERR(sa)) {
*sa_bo = NULL;
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/8] drm/amdgpu: switch all IPs to using job for IBs
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
2026-02-16 21:13 ` [PATCH 1/8] drm/amdgpu: rework ring reset backup and reemit v9 Alex Deucher
2026-02-16 21:13 ` [PATCH 2/8] drm/amdgpu/job: use GFP_ATOMIC while in gpu reset Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 4/8] drm/amdgpu: require a job to schedule an IB Alex Deucher
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Pierre-Eric Pelloux-Prayer
Switch to using a job structure for IBs.
v2: fix missing ib pointer setup spotted by the kernel test robot
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 37 +++---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 31 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 29 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 29 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 29 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 29 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 24 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 139 ++++++++++++-----------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 139 ++++++++++++-----------
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 27 ++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 29 ++---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 38 ++++---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 38 ++++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 38 ++++---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 38 ++++---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 37 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 36 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 36 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 36 +++---
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 36 +++---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 +++--
22 files changed, 502 insertions(+), 427 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index fd881388d6125..9fb1946be1ba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -817,7 +817,8 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
const uint32_t test_pattern = 0xdeadbeef;
- struct amdgpu_ib ib = {};
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
uint32_t index;
uint64_t wb_addr;
@@ -832,23 +833,28 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
adev->wb.wb[index] = 0;
wb_addr = adev->wb.gpu_addr + (index * 4);
- ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ ret = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VPE_RING_TEST);
if (ret)
goto err0;
-
- ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);
- ib.ptr[1] = lower_32_bits(wb_addr);
- ib.ptr[2] = upper_32_bits(wb_addr);
- ib.ptr[3] = test_pattern;
- ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
- ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
- ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
- ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
- ib.length_dw = 8;
-
- ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (ret)
+ ib = &job->ibs[0];
+
+ ib->ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);
+ ib->ptr[1] = lower_32_bits(wb_addr);
+ ib->ptr[2] = upper_32_bits(wb_addr);
+ ib->ptr[3] = test_pattern;
+ ib->ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
+ ib->ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
+ ib->ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
+ ib->ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
+ ib->length_dw = 8;
+
+ ret = amdgpu_job_submit_direct(job, ring, &f);
+ if (ret) {
+ amdgpu_job_free(job);
goto err1;
+ }
ret = dma_fence_wait_timeout(f, false, timeout);
if (ret <= 0) {
@@ -859,7 +865,6 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 22780c09177d8..c6fccb92e656c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -651,7 +651,8 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
u32 tmp = 0;
@@ -665,22 +666,27 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
+ ib = &job->ibs[0];
- ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
+ ib->ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = 1;
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = 1;
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -696,7 +702,6 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 1893ceeeb26c8..50954b60e49df 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4071,15 +4071,14 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned int index;
uint64_t gpu_addr;
uint32_t *cpu_ptr;
long r;
- memset(&ib, 0, sizeof(ib));
-
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
@@ -4088,22 +4087,27 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
- r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err1;
}
+ ib = &job->ibs[0];
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -4118,7 +4122,6 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index b1a1b8a10a08b..d03a4577d4ebf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -604,7 +604,8 @@ static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
uint64_t gpu_addr;
@@ -616,8 +617,6 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
return 0;
- memset(&ib, 0, sizeof(ib));
-
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
@@ -626,22 +625,27 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
- r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err1;
}
+ ib = &job->ibs[0];
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -656,7 +660,6 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index a418ae609c363..905dbd06c28f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -493,7 +493,8 @@ static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
uint64_t gpu_addr;
@@ -505,8 +506,6 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
return 0;
- memset(&ib, 0, sizeof(ib));
-
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
@@ -515,22 +514,27 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
- r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 16,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err1;
}
+ ib = &job->ibs[0];
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -545,7 +549,6 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index eb9725ae1607a..cc5422a398a40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -307,7 +307,8 @@ static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
uint64_t gpu_addr;
@@ -319,8 +320,6 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
return 0;
- memset(&ib, 0, sizeof(ib));
-
r = amdgpu_device_wb_get(adev, &index);
if (r)
return r;
@@ -329,22 +328,27 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
cpu_ptr = &adev->wb.wb[index];
- r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 16,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r) {
dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r);
goto err1;
}
+ ib = &job->ibs[0];
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -359,7 +363,6 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 73223d97a87f5..2f8aa99f17480 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1895,24 +1895,29 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
struct dma_fence *f = NULL;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
uint32_t tmp = 0;
long r;
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r)
return r;
- ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
- ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
- ib.ptr[2] = 0xDEADBEEF;
- ib.length_dw = 3;
+ ib = &job->ibs[0];
+ ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
+ ib->ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
+ ib->ptr[2] = 0xDEADBEEF;
+ ib->length_dw = 3;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto error;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1928,7 +1933,6 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
error:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2b691452775bc..fa235b981c2e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2291,25 +2291,31 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
uint32_t tmp = 0;
long r;
WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r)
return r;
- ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
- ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
- ib.ptr[2] = 0xDEADBEEF;
- ib.length_dw = 3;
+ ib = &job->ibs[0];
+ ib->ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ib->ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
+ ib->ptr[2] = 0xDEADBEEF;
+ ib->length_dw = 3;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto error;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -2325,7 +2331,6 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
error:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a6b4c8f41dc11..4736216cd0211 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -868,9 +868,9 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
-
unsigned int index;
uint64_t gpu_addr;
uint32_t tmp;
@@ -882,22 +882,26 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r)
goto err1;
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib = &job->ibs[0];
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -914,7 +918,6 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
@@ -1474,7 +1477,8 @@ static const u32 sec_ded_counter_registers[] =
static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
int r, i;
u32 tmp;
@@ -1505,106 +1509,108 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
total_size += sizeof(sgpr_init_compute_shader);
/* allocate an indirect buffer to put the commands in */
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, total_size,
- AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, total_size,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_RUN_SHADER);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%d).\n", r);
return r;
}
+ ib = &job->ibs[0];
/* load the compute shaders */
for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
- ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
+ ib->ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
- ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
+ ib->ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
/* init the ib length to 0 */
- ib.length_dw = 0;
+ ib->length_dw = 0;
/* VGPR */
/* write the register state for the compute dispatch */
for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = vgpr_init_regs[i + 1];
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ gpu_addr = (ib->gpu_addr + (u64)vgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 8; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = 8; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* SGPR1 */
/* write the register state for the compute dispatch */
for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = sgpr1_init_regs[i + 1];
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 8; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = 8; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* SGPR2 */
/* write the register state for the compute dispatch */
for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = sgpr2_init_regs[i + 1];
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = 8; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = 8; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* shedule the ib on the ring */
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ r = amdgpu_job_submit_direct(job, ring, &f);
if (r) {
drm_err(adev_to_drm(adev), "ib submit failed (%d).\n", r);
+ amdgpu_job_free(job);
goto fail;
}
@@ -1629,7 +1635,6 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
RREG32(sec_ded_counter_registers[i]);
fail:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7e9d753f4a808..3d7f9494f92f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1224,9 +1224,9 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
-
unsigned index;
uint64_t gpu_addr;
uint32_t tmp;
@@ -1238,22 +1238,26 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r)
goto err1;
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib = &job->ibs[0];
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1270,7 +1274,6 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
@@ -4624,7 +4627,8 @@ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
int r, i;
unsigned total_size, vgpr_offset, sgpr_offset;
@@ -4670,112 +4674,114 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
total_size += sizeof(sgpr_init_compute_shader);
/* allocate an indirect buffer to put the commands in */
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, total_size,
- AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, total_size,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_RUN_SHADER);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%d).\n", r);
return r;
}
+ ib = &job->ibs[0];
/* load the compute shaders */
for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++)
- ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i];
+ ib->ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i];
for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
- ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
+ ib->ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
/* init the ib length to 0 */
- ib.length_dw = 0;
+ ib->length_dw = 0;
/* VGPR */
/* write the register state for the compute dispatch */
for (i = 0; i < gpr_reg_size; i++) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i])
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value;
+ ib->ptr[ib->length_dw++] = vgpr_init_regs_ptr[i].reg_value;
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
+ gpu_addr = (ib->gpu_addr + (u64)vgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = compute_dim_x * 2; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* SGPR1 */
/* write the register state for the compute dispatch */
for (i = 0; i < gpr_reg_size; i++) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i])
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
+ ib->ptr[ib->length_dw++] = sgpr1_init_regs[i].reg_value;
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
+ gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* SGPR2 */
/* write the register state for the compute dispatch */
for (i = 0; i < gpr_reg_size; i++) {
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
- ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
+ ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i])
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
+ ib->ptr[ib->length_dw++] = sgpr2_init_regs[i].reg_value;
}
/* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
- gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
- ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
+ gpu_addr = (ib->gpu_addr + (u64)sgpr_offset) >> 8;
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
+ ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO)
- PACKET3_SET_SH_REG_START;
- ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
- ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
+ ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
/* write dispatch packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
- ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
- ib.ptr[ib.length_dw++] = 1; /* y */
- ib.ptr[ib.length_dw++] = 1; /* z */
- ib.ptr[ib.length_dw++] =
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
+ ib->ptr[ib->length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */
+ ib->ptr[ib->length_dw++] = 1; /* y */
+ ib->ptr[ib->length_dw++] = 1; /* z */
+ ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
/* write CS partial flush packet */
- ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
- ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
+ ib->ptr[ib->length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
/* shedule the ib on the ring */
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+ r = amdgpu_job_submit_direct(job, ring, &f);
if (r) {
drm_err(adev_to_drm(adev), "ib schedule failed (%d).\n", r);
+ amdgpu_job_free(job);
goto fail;
}
@@ -4787,7 +4793,6 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
}
fail:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
index 8058ea91ecafd..96ec6d9ea8656 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c
@@ -345,12 +345,13 @@ const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = {
static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
struct amdgpu_ring *ring,
- struct amdgpu_ib *ib,
const u32 *shader_ptr, u32 shader_size,
const struct soc15_reg_entry *init_regs, u32 regs_size,
u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,
struct dma_fence **fence_ptr)
{
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
int r, i;
uint32_t total_size, shader_offset;
u64 gpu_addr;
@@ -360,14 +361,14 @@ static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
shader_offset = total_size;
total_size += ALIGN(shader_size, 256);
- /* allocate an indirect buffer to put the commands in */
- memset(ib, 0, sizeof(*ib));
- r = amdgpu_ib_get(adev, NULL, total_size,
- AMDGPU_IB_POOL_DIRECT, ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, total_size,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_RUN_SHADER);
if (r) {
dev_err(adev->dev, "failed to get ib (%d).\n", r);
return r;
}
+ ib = &job->ibs[0];
/* load the compute shaders */
for (i = 0; i < shader_size/sizeof(u32); i++)
@@ -408,11 +409,11 @@ static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
ib->ptr[ib->length_dw++] =
REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
- /* shedule the ib on the ring */
- r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr);
+ /* schedule the ib on the ring */
+ r = amdgpu_job_submit_direct(job, ring, fence_ptr);
if (r) {
dev_err(adev->dev, "ib submit failed (%d).\n", r);
- amdgpu_ib_free(ib, NULL);
+ amdgpu_job_free(job);
}
return r;
}
@@ -493,7 +494,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
int wb_size = adev->gfx.config.max_shader_engines *
CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
struct amdgpu_ib wb_ib;
- struct amdgpu_ib disp_ibs[3];
struct dma_fence *fences[3];
u32 pattern[3] = { 0x1, 0x5, 0xa };
@@ -514,7 +514,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
r = gfx_v9_4_2_run_shader(adev,
&adev->gfx.compute_ring[0],
- &disp_ibs[0],
sgpr112_init_compute_shader_aldebaran,
sizeof(sgpr112_init_compute_shader_aldebaran),
sgpr112_init_regs_aldebaran,
@@ -539,7 +538,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
r = gfx_v9_4_2_run_shader(adev,
&adev->gfx.compute_ring[1],
- &disp_ibs[1],
sgpr96_init_compute_shader_aldebaran,
sizeof(sgpr96_init_compute_shader_aldebaran),
sgpr96_init_regs_aldebaran,
@@ -579,7 +577,6 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
r = gfx_v9_4_2_run_shader(adev,
&adev->gfx.compute_ring[0],
- &disp_ibs[2],
sgpr64_init_compute_shader_aldebaran,
sizeof(sgpr64_init_compute_shader_aldebaran),
sgpr64_init_regs_aldebaran,
@@ -611,13 +608,10 @@ static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
}
disp2_failed:
- amdgpu_ib_free(&disp_ibs[2], NULL);
dma_fence_put(fences[2]);
disp1_failed:
- amdgpu_ib_free(&disp_ibs[1], NULL);
dma_fence_put(fences[1]);
disp0_failed:
- amdgpu_ib_free(&disp_ibs[0], NULL);
dma_fence_put(fences[0]);
pro_end:
amdgpu_ib_free(&wb_ib, NULL);
@@ -637,7 +631,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
int wb_size = adev->gfx.config.max_shader_engines *
CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
struct amdgpu_ib wb_ib;
- struct amdgpu_ib disp_ib;
struct dma_fence *fence;
u32 pattern = 0xa;
@@ -657,7 +650,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
r = gfx_v9_4_2_run_shader(adev,
&adev->gfx.compute_ring[0],
- &disp_ib,
vgpr_init_compute_shader_aldebaran,
sizeof(vgpr_init_compute_shader_aldebaran),
vgpr_init_regs_aldebaran,
@@ -687,7 +679,6 @@ static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
}
disp_failed:
- amdgpu_ib_free(&disp_ib, NULL);
dma_fence_put(fence);
pro_end:
amdgpu_ib_free(&wb_ib, NULL);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index ad4d442e7345e..d78b2c2ae13a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -451,9 +451,9 @@ static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
-
unsigned index;
uint64_t gpu_addr;
uint32_t tmp;
@@ -465,22 +465,26 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 20,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST);
if (r)
goto err1;
- ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
- ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
- ib.ptr[2] = lower_32_bits(gpu_addr);
- ib.ptr[3] = upper_32_bits(gpu_addr);
- ib.ptr[4] = 0xDEADBEEF;
- ib.length_dw = 5;
+ ib = &job->ibs[0];
+ ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+ ib->ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+ ib->ptr[2] = lower_32_bits(gpu_addr);
+ ib->ptr[3] = upper_32_bits(gpu_addr);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->length_dw = 5;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err2;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -497,7 +501,6 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err2:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err1:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0090ace49024f..34c5acfa038d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -583,7 +583,8 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
u32 tmp = 0;
@@ -597,26 +598,30 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -632,7 +637,6 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2526d393162ac..73bd9005dbeaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -857,7 +857,8 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
u32 tmp = 0;
@@ -871,26 +872,30 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -905,7 +910,6 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
else
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index a35d9951e22a9..ab8b08b9783a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1515,7 +1515,8 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -1529,26 +1530,30 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1564,7 +1569,6 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 7f77367848d43..fceccaa03f0cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1111,7 +1111,8 @@ static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -1125,26 +1126,30 @@ static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1160,7 +1165,6 @@ static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 52f4e9e099cbf..e91f976f869dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1073,7 +1073,8 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -1081,7 +1082,6 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
tmp = 0xCAFEDEAD;
- memset(&ib, 0, sizeof(ib));
r = amdgpu_device_wb_get(adev, &index);
if (r) {
@@ -1092,27 +1092,31 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(tmp);
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err0;
}
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1132,7 +1136,6 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 0a8269795241d..3838eb48eeeee 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -973,7 +973,8 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -981,7 +982,6 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
tmp = 0xCAFEDEAD;
- memset(&ib, 0, sizeof(ib));
r = amdgpu_device_wb_get(adev, &index);
if (r) {
@@ -992,26 +992,31 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(tmp);
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err0;
}
- ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1031,7 +1036,6 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 2643364328498..25bee64cb00d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -980,7 +980,8 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -988,7 +989,6 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
tmp = 0xCAFEDEAD;
- memset(&ib, 0, sizeof(ib));
r = amdgpu_device_wb_get(adev, &index);
if (r) {
@@ -999,26 +999,31 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(tmp);
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err0;
}
- ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1038,7 +1043,6 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index f938be0524cd1..77a6eef8072cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -996,7 +996,8 @@ static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -1004,7 +1005,6 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
tmp = 0xCAFEDEAD;
- memset(&ib, 0, sizeof(ib));
r = amdgpu_device_wb_get(adev, &index);
if (r) {
@@ -1015,26 +1015,31 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(tmp);
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r) {
drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r);
goto err0;
}
- ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1054,7 +1059,6 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
index 3de76afe3e454..3540bd427f6eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
@@ -986,7 +986,8 @@ static int sdma_v7_1_ring_test_ring(struct amdgpu_ring *ring)
static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
long r;
@@ -994,7 +995,6 @@ static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
u64 gpu_addr;
tmp = 0xCAFEDEAD;
- memset(&ib, 0, sizeof(ib));
r = amdgpu_device_wb_get(adev, &index);
if (r) {
@@ -1005,26 +1005,31 @@ static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(tmp);
- r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r) {
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
goto err0;
}
- ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
+ ib = &job->ibs[0];
+ ib->ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr);
- ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
- ib.ptr[4] = 0xDEADBEEF;
- ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
- ib.length_dw = 8;
-
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr);
+ ib->ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
+ ib->ptr[4] = 0xDEADBEEF;
+ ib->ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
+ ib->length_dw = 8;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -1044,7 +1049,6 @@ static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 3e58feb2d5e4f..8362db058da2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -258,7 +258,8 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring)
static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib ib;
+ struct amdgpu_job *job;
+ struct amdgpu_ib *ib;
struct dma_fence *f = NULL;
unsigned index;
u32 tmp = 0;
@@ -272,20 +273,25 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
gpu_addr = adev->wb.gpu_addr + (index * 4);
tmp = 0xCAFEDEAD;
adev->wb.wb[index] = cpu_to_le32(tmp);
- memset(&ib, 0, sizeof(ib));
- r = amdgpu_ib_get(adev, NULL, 256,
- AMDGPU_IB_POOL_DIRECT, &ib);
+
+ r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 256,
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST);
if (r)
goto err0;
- ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1);
- ib.ptr[1] = lower_32_bits(gpu_addr);
- ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
- ib.ptr[3] = 0xDEADBEEF;
- ib.length_dw = 4;
- r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
- if (r)
+ ib = &job->ibs[0];
+ ib->ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1);
+ ib->ptr[1] = lower_32_bits(gpu_addr);
+ ib->ptr[2] = upper_32_bits(gpu_addr) & 0xff;
+ ib->ptr[3] = 0xDEADBEEF;
+ ib->length_dw = 4;
+
+ r = amdgpu_job_submit_direct(job, ring, &f);
+ if (r) {
+ amdgpu_job_free(job);
goto err1;
+ }
r = dma_fence_wait_timeout(f, false, timeout);
if (r == 0) {
@@ -301,7 +307,6 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = -EINVAL;
err1:
- amdgpu_ib_free(&ib, NULL);
dma_fence_put(f);
err0:
amdgpu_device_wb_free(adev, index);
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/8] drm/amdgpu: require a job to schedule an IB
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
` (2 preceding siblings ...)
2026-02-16 21:13 ` [PATCH 3/8] drm/amdgpu: switch all IPs to using job for IBs Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 5/8] drm/amdgpu: plumb timedout fence through to force completion Alex Deucher
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
Remove the old direct submit path. This simplifies
the code.
v2: remove more local variables
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 113 ++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +-
4 files changed, 45 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 823b92005689a..4ec1058b7cdfa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -685,7 +685,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
job->vmid = vmid;
job->num_ibs = 1;
- ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
+ ret = amdgpu_ib_schedule(ring, job, &f);
if (ret) {
drm_err(adev_to_drm(adev), "failed to schedule IB.\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 80565c4a31bdf..55a9670f1dd90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -103,8 +103,6 @@ void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f)
* amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
*
* @ring: ring index the IB is associated with
- * @num_ibs: number of IBs to schedule
- * @ibs: IB objects to schedule
* @job: job to schedule
* @f: fence created during this submission
*
@@ -121,90 +119,70 @@ void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f)
* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
* to SI there was just a DE IB.
*/
-int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
- struct amdgpu_ib *ibs, struct amdgpu_job *job,
+int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
struct dma_fence **f)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_ib *ib = &ibs[0];
+ struct amdgpu_ib *ib;
struct dma_fence *tmp = NULL;
struct amdgpu_fence *af;
struct amdgpu_fence *vm_af;
bool need_ctx_switch;
- struct amdgpu_vm *vm;
uint64_t fence_ctx;
uint32_t status = 0, alloc_size;
unsigned int fence_flags = 0;
- bool secure, init_shadow;
- u64 shadow_va, csa_va, gds_va;
+ bool secure;
int vmid = AMDGPU_JOB_GET_VMID(job);
bool need_pipe_sync = false;
unsigned int cond_exec;
unsigned int i;
int r = 0;
- if (num_ibs == 0)
+ if (!job)
+ return -EINVAL;
+ if (job->num_ibs == 0)
return -EINVAL;
- /* ring tests don't use a job */
- if (job) {
- vm = job->vm;
- fence_ctx = job->base.s_fence ?
- job->base.s_fence->finished.context : 0;
- shadow_va = job->shadow_va;
- csa_va = job->csa_va;
- gds_va = job->gds_va;
- init_shadow = job->init_shadow;
- af = job->hw_fence;
- /* Save the context of the job for reset handling.
- * The driver needs this so it can skip the ring
- * contents for guilty contexts.
- */
- af->context = fence_ctx;
- /* the vm fence is also part of the job's context */
- job->hw_vm_fence->context = fence_ctx;
- } else {
- vm = NULL;
- fence_ctx = 0;
- shadow_va = 0;
- csa_va = 0;
- gds_va = 0;
- init_shadow = false;
- af = kzalloc(sizeof(*af), GFP_ATOMIC);
- if (!af)
- return -ENOMEM;
- }
+ ib = &job->ibs[0];
+ fence_ctx = job->base.s_fence ?
+ job->base.s_fence->finished.context : 0;
+ af = job->hw_fence;
+ vm_af = job->hw_vm_fence;
+ /* Save the context of the job for reset handling.
+ * The driver needs this so it can skip the ring
+ * contents for guilty contexts.
+ */
+ af->context = fence_ctx;
+ /* the vm fence is also part of the job's context */
+ vm_af->context = fence_ctx;
if (!ring->sched.ready) {
dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
- r = -EINVAL;
- goto free_fence;
+ return -EINVAL;
}
- if (vm && !job->vmid) {
+ if (job->vm && !job->vmid) {
dev_err(adev->dev, "VM IB without ID\n");
- r = -EINVAL;
- goto free_fence;
+ return -EINVAL;
}
if ((ib->flags & AMDGPU_IB_FLAGS_SECURE) &&
(!ring->funcs->secure_submission_supported)) {
dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);
- r = -EINVAL;
- goto free_fence;
+ return -EINVAL;
}
- alloc_size = ring->funcs->emit_frame_size + num_ibs *
+ alloc_size = ring->funcs->emit_frame_size + job->num_ibs *
ring->funcs->emit_ib_size;
r = amdgpu_ring_alloc(ring, alloc_size);
if (r) {
dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
- goto free_fence;
+ return r;
}
need_ctx_switch = ring->current_ctx != fence_ctx;
- if (ring->funcs->emit_pipeline_sync && job &&
+ if (ring->funcs->emit_pipeline_sync &&
((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {
@@ -216,14 +194,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
dma_fence_put(tmp);
}
- if (job) {
- vm_af = job->hw_vm_fence;
- /* VM sequence */
- vm_af->ib_wptr = ring->wptr;
- amdgpu_vm_flush(ring, job, need_pipe_sync);
- vm_af->ib_dw_size =
- amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr);
- }
+ /* VM sequence */
+ vm_af->ib_wptr = ring->wptr;
+ amdgpu_vm_flush(ring, job, need_pipe_sync);
+ vm_af->ib_dw_size =
+ amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr);
/* IB sequence */
af->ib_wptr = ring->wptr;
@@ -240,8 +215,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
ring->funcs->emit_wave_limit(ring, true);
if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)
- amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
- init_shadow, vmid);
+ amdgpu_ring_emit_gfx_shadow(ring, job->shadow_va, job->csa_va, job->gds_va,
+ job->init_shadow, vmid);
if (ring->funcs->init_cond_exec)
cond_exec = amdgpu_ring_init_cond_exec(ring,
@@ -255,7 +230,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
if (need_ctx_switch)
status |= AMDGPU_HAVE_CTX_SWITCH;
- if (job && ring->funcs->emit_cntxcntl) {
+ if (ring->funcs->emit_cntxcntl) {
status |= job->preamble_status;
status |= job->preemption_status;
amdgpu_ring_emit_cntxcntl(ring, status);
@@ -264,15 +239,15 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
/* Setup initial TMZiness and send it off.
*/
secure = false;
- if (job && ring->funcs->emit_frame_cntl) {
+ if (ring->funcs->emit_frame_cntl) {
secure = ib->flags & AMDGPU_IB_FLAGS_SECURE;
amdgpu_ring_emit_frame_cntl(ring, true, secure);
}
- for (i = 0; i < num_ibs; ++i) {
- ib = &ibs[i];
+ for (i = 0; i < job->num_ibs; ++i) {
+ ib = &job->ibs[i];
- if (job && ring->funcs->emit_frame_cntl) {
+ if (ring->funcs->emit_frame_cntl) {
if (secure != !!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) {
amdgpu_ring_emit_frame_cntl(ring, false, secure);
secure = !secure;
@@ -284,7 +259,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
status &= ~AMDGPU_HAVE_CTX_SWITCH;
}
- if (job && ring->funcs->emit_frame_cntl)
+ if (ring->funcs->emit_frame_cntl)
amdgpu_ring_emit_frame_cntl(ring, false, secure);
amdgpu_device_invalidate_hdp(adev, ring);
@@ -296,7 +271,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
/* wrap the last IB with fence */
- if (job && job->uf_addr) {
+ if (job->uf_addr) {
amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
fence_flags | AMDGPU_FENCE_FLAG_64BIT);
}
@@ -310,8 +285,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
amdgpu_fence_emit(ring, af, fence_flags);
*f = &af->base;
/* get a ref for the job */
- if (job)
- dma_fence_get(*f);
+ dma_fence_get(*f);
if (ring->funcs->insert_end)
ring->funcs->insert_end(ring);
@@ -319,7 +293,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
amdgpu_ring_patch_cond_exec(ring, cond_exec);
ring->current_ctx = fence_ctx;
- if (job && ring->funcs->emit_switch_buffer)
+ if (ring->funcs->emit_switch_buffer)
amdgpu_ring_emit_switch_buffer(ring);
if (ring->funcs->emit_wave_limit &&
@@ -333,11 +307,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
amdgpu_ring_commit(ring);
return 0;
-
-free_fence:
- if (!job)
- kfree(af);
- return r;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 95aa87b4406eb..cd0707737a29b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -377,7 +377,7 @@ int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
int r;
job->base.sched = &ring->sched;
- r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
+ r = amdgpu_ib_schedule(ring, job, fence);
if (r)
return r;
@@ -447,8 +447,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
dev_dbg(adev->dev, "Skip scheduling IBs in ring(%s)",
ring->name);
} else {
- r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
- &fence);
+ r = amdgpu_ib_schedule(ring, job, &fence);
if (r)
dev_err(adev->dev,
"Error scheduling IBs (%d) in ring(%s)", r,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index ce5af137ee400..fafb876d73da1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -575,8 +575,7 @@ int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
enum amdgpu_ib_pool_type pool,
struct amdgpu_ib *ib);
void amdgpu_ib_free(struct amdgpu_ib *ib, struct dma_fence *f);
-int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
- struct amdgpu_ib *ibs, struct amdgpu_job *job,
+int amdgpu_ib_schedule(struct amdgpu_ring *ring, struct amdgpu_job *job,
struct dma_fence **f);
int amdgpu_ib_pool_init(struct amdgpu_device *adev);
void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/8] drm/amdgpu: plumb timedout fence through to force completion
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
` (3 preceding siblings ...)
2026-02-16 21:13 ` [PATCH 4/8] drm/amdgpu: require a job to schedule an IB Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 6/8] drm/amdgpu: simplify VCN reset helper Alex Deucher
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher
When we do a full adapter reset, if we know the timedout fence
mark the fence with -ETIME rather than -ECANCELED so it
gets properly handled by userspace.
v2: rebase
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 26 +++++++++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 21 ++++++++++-------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 +-
9 files changed, 48 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index aeb90708f2293..663d115ab169c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1936,7 +1936,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
/* swap out the old fences */
amdgpu_ib_preempt_fences_swap(ring, fences);
- amdgpu_fence_driver_force_completion(ring);
+ amdgpu_fence_driver_force_completion(ring, NULL);
/* resubmit unfinished jobs */
amdgpu_ib_preempt_job_recovery(&ring->sched);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c53954d3a529f..0ea170e7d4f7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5777,6 +5777,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
{
int i, r = 0;
struct amdgpu_job *job = NULL;
+ struct dma_fence *fence = NULL;
struct amdgpu_device *tmp_adev = reset_context->reset_req_dev;
bool need_full_reset =
test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
@@ -5789,6 +5790,9 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
amdgpu_fence_driver_isr_toggle(adev, true);
+ if (job)
+ fence = &job->hw_fence->base;
+
/* block all schedulers and reset given job's ring */
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
@@ -5797,7 +5801,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
continue;
/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
- amdgpu_fence_driver_force_completion(ring);
+ amdgpu_fence_driver_force_completion(ring, fence);
}
amdgpu_fence_driver_isr_toggle(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d209591e3710a..0542d88f7159a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -547,7 +547,7 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
r = -ENODEV;
/* no need to trigger GPU reset as we are unloading */
if (r)
- amdgpu_fence_driver_force_completion(ring);
+ amdgpu_fence_driver_force_completion(ring, NULL);
if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
ring->fence_drv.irq_src &&
@@ -662,16 +662,34 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error)
* amdgpu_fence_driver_force_completion - force signal latest fence of ring
*
* @ring: fence of the ring to signal
+ * @timedout_fence: fence of the timedout job
*
*/
-void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
+void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring,
+ struct dma_fence *timedout_fence)
{
- amdgpu_fence_driver_set_error(ring, -ECANCELED);
+ struct amdgpu_fence_driver *drv = &ring->fence_drv;
+ unsigned long flags;
+
+ spin_lock_irqsave(&drv->lock, flags);
+ for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) {
+ struct dma_fence *fence;
+
+ fence = rcu_dereference_protected(drv->fences[i],
+ lockdep_is_held(&drv->lock));
+ if (fence && !dma_fence_is_signaled_locked(fence)) {
+ if (fence == timedout_fence)
+ dma_fence_set_error(fence, -ETIME);
+ else
+ dma_fence_set_error(fence, -ECANCELED);
+ }
+ }
+ spin_unlock_irqrestore(&drv->lock, flags);
+
amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
amdgpu_fence_process(ring);
}
-
/*
* Kernel queue reset handling
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index fafb876d73da1..6ac66dac524ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -159,7 +159,8 @@ struct amdgpu_fence {
extern const struct drm_sched_backend_ops amdgpu_sched_ops;
void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
-void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
+void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring,
+ struct dma_fence *timedout_fence);
void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring,
struct amdgpu_fence *guilty_fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 321310ba2c08e..fcd81242059e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -600,10 +600,10 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
* to be submitted to the queues after the reset is complete.
*/
if (!ret) {
- amdgpu_fence_driver_force_completion(gfx_ring);
+ amdgpu_fence_driver_force_completion(gfx_ring, NULL);
drm_sched_wqueue_start(&gfx_ring->sched);
if (adev->sdma.has_page_queue) {
- amdgpu_fence_driver_force_completion(page_ring);
+ amdgpu_fence_driver_force_completion(page_ring, NULL);
drm_sched_wqueue_start(&page_ring->sched);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 9d5cca7da1d9e..3a3bc0d370fa6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -512,7 +512,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
}
memset_io(ptr, 0, size);
/* to restore uvd fence seq */
- amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
+ amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL);
}
}
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 75ae9b429420e..d22c8980fa42b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1482,15 +1482,16 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,
/**
* amdgpu_vcn_reset_engine - Reset a specific VCN engine
- * @adev: Pointer to the AMDGPU device
- * @instance_id: VCN engine instance to reset
+ * @ring: Pointer to the VCN ring
+ * @timedout_fence: fence that timed out
*
* Returns: 0 on success, or a negative error code on failure.
*/
-static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev,
- uint32_t instance_id)
+static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring,
+ struct amdgpu_fence *timedout_fence)
{
- struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id];
+ struct amdgpu_device *adev = ring->adev;
+ struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
int r, i;
mutex_lock(&vinst->engine_reset_mutex);
@@ -1514,9 +1515,13 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev,
if (r)
goto unlock;
}
- amdgpu_fence_driver_force_completion(&vinst->ring_dec);
+ amdgpu_fence_driver_force_completion(&vinst->ring_dec,
+ (&vinst->ring_dec == ring) ?
+ &timedout_fence->base : NULL);
for (i = 0; i < vinst->num_enc_rings; i++)
- amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]);
+ amdgpu_fence_driver_force_completion(&vinst->ring_enc[i],
+ (&vinst->ring_enc[i] == ring) ?
+ &timedout_fence->base : NULL);
/* Restart the scheduler's work queue for the dec and enc rings
* if they were stopped by this function. This allows new tasks
@@ -1552,7 +1557,7 @@ int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
if (adev->vcn.inst[ring->me].using_unified_queue)
return -EINVAL;
- return amdgpu_vcn_reset_engine(adev, ring->me);
+ return amdgpu_vcn_reset_engine(ring, timedout_fence);
}
int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index e78526a4e521e..a6aa72ec8fb19 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1669,7 +1669,7 @@ static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
ring = &adev->jpeg.inst[inst].ring_dec[i];
/* Force completion of any remaining jobs */
- amdgpu_fence_driver_force_completion(ring);
+ amdgpu_fence_driver_force_completion(ring, NULL);
if (ring->use_doorbell)
WREG32_SOC15_OFFSET(
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
index c28c6aff17aaa..100ea1a914b4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
@@ -1332,7 +1332,7 @@ static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins
for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) {
ring = &adev->jpeg.inst[inst].ring_dec[i];
/* Force completion of any remaining jobs */
- amdgpu_fence_driver_force_completion(ring);
+ amdgpu_fence_driver_force_completion(ring, NULL);
if (ring->use_doorbell)
WREG32_SOC15_OFFSET(
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/8] drm/amdgpu: simplify VCN reset helper
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
` (4 preceding siblings ...)
2026-02-16 21:13 ` [PATCH 5/8] drm/amdgpu: plumb timedout fence through to force completion Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 7/8] drm/amdgpu/cs: return -ETIME for guilty contexts Alex Deucher
2026-02-16 21:13 ` [PATCH 8/8] drm/amdgpu: Call drm_sched_increase_karma() for ring resets Alex Deucher
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
Remove the wrapper function.
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 41 ++++++++-----------------
1 file changed, 13 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index d22c8980fa42b..4de5c8b9a4cc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1481,19 +1481,27 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block,
}
/**
- * amdgpu_vcn_reset_engine - Reset a specific VCN engine
- * @ring: Pointer to the VCN ring
- * @timedout_fence: fence that timed out
+ * amdgpu_vcn_ring_reset - Reset a VCN ring
+ * @ring: ring to reset
+ * @vmid: vmid of guilty job
+ * @timedout_fence: fence of timed out job
*
+ * This helper is for VCN blocks without unified queues because
+ * resetting the engine resets all queues in that case. With
+ * unified queues we have one queue per engine.
* Returns: 0 on success, or a negative error code on failure.
*/
-static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring,
- struct amdgpu_fence *timedout_fence)
+int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
+ unsigned int vmid,
+ struct amdgpu_fence *timedout_fence)
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
int r, i;
+ if (adev->vcn.inst[ring->me].using_unified_queue)
+ return -EINVAL;
+
mutex_lock(&vinst->engine_reset_mutex);
/* Stop the scheduler's work queue for the dec and enc rings if they are running.
* This ensures that no new tasks are submitted to the queues while
@@ -1537,29 +1545,6 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring,
return r;
}
-/**
- * amdgpu_vcn_ring_reset - Reset a VCN ring
- * @ring: ring to reset
- * @vmid: vmid of guilty job
- * @timedout_fence: fence of timed out job
- *
- * This helper is for VCN blocks without unified queues because
- * resetting the engine resets all queues in that case. With
- * unified queues we have one queue per engine.
- * Returns: 0 on success, or a negative error code on failure.
- */
-int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring,
- unsigned int vmid,
- struct amdgpu_fence *timedout_fence)
-{
- struct amdgpu_device *adev = ring->adev;
-
- if (adev->vcn.inst[ring->me].using_unified_queue)
- return -EINVAL;
-
- return amdgpu_vcn_reset_engine(ring, timedout_fence);
-}
-
int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev,
const struct amdgpu_hwip_reg_entry *reg, u32 count)
{
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 7/8] drm/amdgpu/cs: return -ETIME for guilty contexts
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
` (5 preceding siblings ...)
2026-02-16 21:13 ` [PATCH 6/8] drm/amdgpu: simplify VCN reset helper Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
2026-02-16 21:13 ` [PATCH 8/8] drm/amdgpu: Call drm_sched_increase_karma() for ring resets Alex Deucher
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
Return -ETIME rather than -ECANCELED for guilty contexts.
Userspace only considers contexts to be guilty if they
return -ETIME. Returning -ECANCELED means the context was
innocent.
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 6b494e4e8c0e9..564beb888abe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -62,7 +62,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
if (atomic_read(&p->ctx->guilty)) {
amdgpu_ctx_put(p->ctx);
- return -ECANCELED;
+ return -ETIME;
}
amdgpu_sync_create(&p->sync);
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 8/8] drm/amdgpu: Call drm_sched_increase_karma() for ring resets
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
` (6 preceding siblings ...)
2026-02-16 21:13 ` [PATCH 7/8] drm/amdgpu/cs: return -ETIME for guilty contexts Alex Deucher
@ 2026-02-16 21:13 ` Alex Deucher
7 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2026-02-16 21:13 UTC (permalink / raw)
To: amd-gfx, christian.koenig; +Cc: Alex Deucher, Jesse Zhang
Mark the entity as guilty. Align with adapter resets.
This only makes sense now that the CS IOCTL returns -ETIME
rather than -ECANCELED. Without that patch, this would
break userspace.
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index cd0707737a29b..dd9b649cf88e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -137,6 +137,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
s_job->sched->name);
/* Stop the scheduler to prevent anybody else from touching the ring buffer. */
drm_sched_wqueue_stop(&ring->sched);
+ if (job->vm)
+ drm_sched_increase_karma(&job->base);
r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence);
if (!r) {
/* Start the scheduler again */
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-02-16 21:14 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-16 21:13 [PATCH 0/8] Improvements for IB handling V9 Alex Deucher
2026-02-16 21:13 ` [PATCH 1/8] drm/amdgpu: rework ring reset backup and reemit v9 Alex Deucher
2026-02-16 21:13 ` [PATCH 2/8] drm/amdgpu/job: use GFP_ATOMIC while in gpu reset Alex Deucher
2026-02-16 21:13 ` [PATCH 3/8] drm/amdgpu: switch all IPs to using job for IBs Alex Deucher
2026-02-16 21:13 ` [PATCH 4/8] drm/amdgpu: require a job to schedule an IB Alex Deucher
2026-02-16 21:13 ` [PATCH 5/8] drm/amdgpu: plumb timedout fence through to force completion Alex Deucher
2026-02-16 21:13 ` [PATCH 6/8] drm/amdgpu: simplify VCN reset helper Alex Deucher
2026-02-16 21:13 ` [PATCH 7/8] drm/amdgpu/cs: return -ETIME for guilty contexts Alex Deucher
2026-02-16 21:13 ` [PATCH 8/8] drm/amdgpu: Call drm_sched_increase_karma() for ring resets Alex Deucher
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