[PATCH 0/8] DC Patches Feb 25, 2026

[PATCH 0/8] DC Patches Feb 25, 2026

[Alex Hung]

This DC patchset brings improvements in multiple areas. In summary, we have:
* Prevent integer overflow when mhz to khz
* Remove always-false branches
* Remove redundant initializers
* Silence unused variable warning
* Initialize replay_state to PR_STATE_INVALID
* Fallback to boot snapshot for dispclk
* Skip cursor cache reset if hubp powergating is disabled

Cc: Dan Wheeler <daniel.wheeler@amd.com>

Alex Hung (3):
  drm/amd/display: Remove redundant initializers
  drm/amd/display: Remove always-false branches
  drm/amd/display: Prevent integer overflow when mhz to khz

Benjamin Nwankwo (1):
  drm/amd/display: Skip cursor cache reset if hubp powergating is
    disabled

Clay King (1):
  drm/amd/display: Silence unused variable warning

Dillon Varone (1):
  drm/amd/display: Fallback to boot snapshot for dispclk

Ivan Lipski (1):
  drm/amd/display: Initialize replay_state to PR_STATE_INVALID

Taimur Hassan (1):
  drm/amd/display: Promote DC to 3.2.372

 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c  | 14 ++++++------
 .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.c  | 22 +++++++++----------
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../display/dc/dml2_0/dml2_dc_resource_mgmt.c |  6 ++---
 .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c  |  7 +++---
 .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c  |  5 -----
 .../amd/display/dc/hubp/dcn10/dcn10_hubp.c    |  6 +++--
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c |  6 ++++-
 .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c   |  6 +----
 .../dc/link/protocols/link_dp_panel_replay.c  |  2 +-
 .../dc/resource/dcn42/dcn42_resource.c        |  4 ++--
 11 files changed, 39 insertions(+), 41 deletions(-)

-- 
2.43.0

[PATCH 1/8] drm/amd/display: Skip cursor cache reset if hubp powergating is disabled

[Alex Hung]

From: Benjamin Nwankwo <Benjamin.Nwankwo@amd.com>

[WHY]
On pipe resets, cursor cache resets to sync with power gated hubp.
But dcn42 doesn't power gate hubp which causes a discrepancy
where cursor registers are still enabled while the cache is cleared.
This ultimately leads to a pipe's cursor incorrectly retaining its
enabled state, while the cursor isn't in its viewport

[HOW]
Skip memsets for dpp and hubp cursor caches if either
disable_hubp_power_gate or ignore_pg flags are true

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Benjamin Nwankwo <Benjamin.Nwankwo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c   | 7 ++++---
 drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c | 6 ++++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
index ce91e5d28956..194dba734cc1 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
@@ -193,9 +193,10 @@ void dpp_reset(struct dpp *dpp_base)
 	dpp->filter_v_c = NULL;
 	dpp->filter_h = NULL;
 	dpp->filter_v = NULL;
-
-	memset(&dpp_base->pos, 0, sizeof(dpp_base->pos));
-	memset(&dpp_base->att, 0, sizeof(dpp_base->att));
+	if (!dpp_base->ctx->dc->debug.ignore_pg) {
+		memset(&dpp_base->pos, 0, sizeof(dpp_base->pos));
+		memset(&dpp_base->att, 0, sizeof(dpp_base->att));
+	}
 
 	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
 	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index 6378e3fd7249..a2ddf81538e6 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -548,8 +548,10 @@ void hubp1_dcc_control(struct hubp *hubp, bool enable,
 
 void hubp_reset(struct hubp *hubp)
 {
-	memset(&hubp->pos, 0, sizeof(hubp->pos));
-	memset(&hubp->att, 0, sizeof(hubp->att));
+	if (!hubp->ctx->dc->debug.ignore_pg && !hubp->ctx->dc->debug.disable_hubp_power_gate) {
+		memset(&hubp->pos, 0, sizeof(hubp->pos));
+		memset(&hubp->att, 0, sizeof(hubp->att));
+	}
 	hubp->cursor_offload = false;
 }
 
-- 
2.43.0

[PATCH 2/8] drm/amd/display: Fallback to boot snapshot for dispclk

[Alex Hung]

From: Dillon Varone <Dillon.Varone@amd.com>

[WHY & HOW]
If the dentist is unavailable, fallback to reading CLKIP via the boot
snapshot to get the current dispclk.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 95d9e17a269b..69cc70106bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -72,7 +72,11 @@ void dcn401_initialize_min_clocks(struct dc *dc)
 		 * audio corruption. Read current DISPCLK from DENTIST and request the same
 		 * freq to ensure that the timing is valid and unchanged.
 		 */
-		clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+		if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {
+			clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
+		} else {
+			clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;
+		}
 	}
 	clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
 	clocks->fclk_p_state_change_support = true;
-- 
2.43.0

[PATCH 3/8] drm/amd/display: Initialize replay_state to PR_STATE_INVALID

[Alex Hung]

From: Ivan Lipski <ivan.lipski@amd.com>

[WHY & HOW]
Initialize the replay_state variable to PR_STATE_INVALID instead of
PR_STATE_0 before retrieving the actual replay state.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../drm/amd/display/dc/link/protocols/link_dp_panel_replay.c    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 7e45d1e767bb..6661078c0241 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -389,7 +389,7 @@ bool dp_pr_get_state(const struct dc_link *link, uint64_t *state)
 	const struct dc *dc = link->ctx->dc;
 	unsigned int panel_inst = 0;
 	uint32_t retry_count = 0;
-	uint32_t replay_state = 0;
+	uint32_t replay_state = PR_STATE_INVALID;
 
 	if (!dp_pr_get_panel_inst(dc, link, &panel_inst))
 		return false;
-- 
2.43.0

[PATCH 4/8] drm/amd/display: Silence unused variable warning

[Alex Hung]

From: Clay King <clayking@amd.com>

[WHY & HOW]
Remove unused dpp_pipe_count variable.

Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c   | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c
index 4cfe64aa8492..74812a7d5e28 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c
@@ -909,10 +909,10 @@ static unsigned int get_source_mpc_factor(const struct dml2_context *ctx,
 		const struct dc_plane_state *plane)
 {
 	struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
-	int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane,
-			&state->res_ctx, dpp_pipes);
 
-	ASSERT(dpp_pipe_count > 0);
+	if (ctx->config.callbacks.get_dpp_pipes_for_plane(plane, &state->res_ctx, dpp_pipes) <= 0)
+		ASSERT(false);
+
 	return ctx->config.callbacks.get_mpc_slice_count(dpp_pipes[0]);
 }
 
-- 
2.43.0

[PATCH 5/8] drm/amd/display: Remove redundant initializers

[Alex Hung]

[WHAT]
Remove unnecessary default value assignments for variables that
are unconditionally assigned before use.

Linux kernel code style prefers no assignments during initialization
when variables are assigned unconditionally as they can obscures
the actual data flow. In addition, compilers will be able to catch them
if variables are used without being updated later in all conditions.

This is reported as UNUSED_VALUE errors by Coverity.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c   | 10 +++++-----
 .../drm/amd/display/dc/resource/dcn42/dcn42_resource.c |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index 19df8b47248b..d3cc624cd758 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -105,7 +105,7 @@ union dcn42_dpia_host_router_bw {
 static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr,
 		unsigned int delay_us, unsigned int max_retries)
 {
-	uint32_t res_val = DALSMC_Result_CmdRejectedBusy;
+	uint32_t res_val;
 
 	do {
 		res_val = REG_READ(DAL_RESP_REG);
@@ -180,7 +180,7 @@ int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr)
 
 int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
 {
-	int actual_dispclk_set_mhz = -1;
+	int actual_dispclk_set_mhz;
 
 	if (!clk_mgr->smu_present)
 		return requested_dispclk_khz;
@@ -199,7 +199,7 @@ int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl
 
 int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
 {
-	int actual_dcfclk_set_mhz = -1;
+	int actual_dcfclk_set_mhz;
 
 	if (!clk_mgr->smu_present)
 		return requested_dcfclk_khz;
@@ -217,7 +217,7 @@ int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
 
 int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
 {
-	int actual_min_ds_dcfclk_mhz = -1;
+	int actual_min_ds_dcfclk_mhz;
 
 	if (!clk_mgr->smu_present)
 		return requested_min_ds_dcfclk_khz;
@@ -235,7 +235,7 @@ int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re
 
 int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
 {
-	int actual_dppclk_set_mhz = -1;
+	int actual_dppclk_set_mhz;
 
 	if (!clk_mgr->smu_present)
 		return requested_dpp_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index 9f2f4d61d323..8e41367cf238 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1811,8 +1811,8 @@ static bool dcn42_resource_construct(
 	int i, j;
 	struct dc_context *ctx = dc->ctx;
 	struct irq_service_init_data init_data;
-	uint32_t pipe_fuses = 0;
-	uint32_t num_pipes = 4;
+	uint32_t pipe_fuses;
+	uint32_t num_pipes;
 
 #undef REG_STRUCT
 #define REG_STRUCT bios_regs
-- 
2.43.0

[PATCH 6/8] drm/amd/display: Remove always-false branches

[Alex Hung]

[WHAT]
program_prealpha_dealpha and hpo_frl_stream_enc_acquired are always
false and all branches depending on them will never be taken.

This is reported as DEADCODE errors by Coverity.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c    | 5 -----
 drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 6 +-----
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
index 244c91b762b0..c126fb9d5bfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
@@ -132,7 +132,6 @@ static void dpp42_dpp_setup(
 	uint32_t alpha_plane_enable = 0;
 	uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
 	uint32_t realpha_en = 0, realpha_ablnd_en = 0;
-	uint32_t program_prealpha_dealpha = 0;
 	struct out_csc_color_matrix tbl_entry;
 	int i;
 
@@ -256,10 +255,6 @@ static void dpp42_dpp_setup(
 		CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 
-	if (program_prealpha_dealpha) {
-		dealpha_en = 1;
-		realpha_en = 1;
-	}
 	REG_SET_2(PRE_DEALPHA, 0,
 		PRE_DEALPHA_EN, dealpha_en,
 		PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
index 0d9871f9864b..f0e1ed0f2949 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c
@@ -1078,7 +1078,6 @@ void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context)
 void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
 	struct pg_block_update *update_state)
 {
-	bool hpo_frl_stream_enc_acquired = false;
 	bool hpo_dp_stream_enc_acquired = false;
 	int i = 0, j = 0;
 
@@ -1172,12 +1171,9 @@ void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
 		}
 	}
 
-	if (hpo_frl_stream_enc_acquired || hpo_dp_stream_enc_acquired)
+	if (hpo_dp_stream_enc_acquired)
 		update_state->pg_res_update[PG_HPO] = true;
 
-	if (hpo_frl_stream_enc_acquired)
-		update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
-
 	if (count_active_streams(dc) > 0) {
 		update_state->pg_res_update[PG_DCCG] = true;
 		update_state->pg_res_update[PG_DCIO] = true;
-- 
2.43.0

[PATCH 7/8] drm/amd/display: Prevent integer overflow when mhz to khz

[Alex Hung]

[WHAT]
Cast to long long before multiplication to prevent overflow
when converting mhz to khz by multiplying by 1000.

This is reported as INTEGER_OVERFLOW errors by Coverity.

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c   | 14 +++++++-------
 .../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c   | 12 ++++++------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
index 604d256cb47a..9d8f81c3d3f0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
@@ -204,7 +204,7 @@ int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl
 			khz_to_mhz_ceil(requested_dispclk_khz));
 
 	smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz);
-	return actual_dispclk_set_mhz * 1000;
+	return (int)((long long)actual_dispclk_set_mhz * 1000);
 }
 
 int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
@@ -221,7 +221,7 @@ int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 
 	/* TODO: add code for programing DP DTO, currently this is down by command table */
 
-	return actual_dprefclk_set_mhz * 1000;
+	return (int)((long long)actual_dprefclk_set_mhz * 1000);
 }
 
 int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
@@ -238,7 +238,7 @@ int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
 
 	smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz);
 
-	return actual_dcfclk_set_mhz * 1000;
+	return (int)((long long)actual_dcfclk_set_mhz * 1000);
 }
 
 int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
@@ -255,7 +255,7 @@ int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re
 
 	smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
 
-	return actual_min_ds_dcfclk_mhz * 1000;
+	return (int)((long long)actual_min_ds_dcfclk_mhz * 1000);
 }
 
 int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
@@ -272,7 +272,7 @@ int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz
 
 	smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz);
 
-	return actual_dppclk_set_mhz * 1000;
+	return (int)((long long)actual_dppclk_set_mhz * 1000);
 }
 
 void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
@@ -424,7 +424,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
 						 0);
 
 	smu_print("%s:  SMU DPREF clk  = %d mhz\n",  __func__, dprefclk);
-	return dprefclk * 1000;
+	return (int)((long long)dprefclk * 1000);
 }
 
 int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
@@ -439,7 +439,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
 					       0);
 
 	smu_print("%s: get_dtbclk  = %dmhz\n", __func__, dtbclk);
-	return dtbclk * 1000;
+	return (int)((long long)dtbclk * 1000);
 }
 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
 void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index d3cc624cd758..c791bb1edb47 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -193,7 +193,7 @@ int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl
 
 	smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n",
 		requested_dispclk_khz, actual_dispclk_set_mhz);
-	return actual_dispclk_set_mhz * 1000;
+	return (int)((long long)actual_dispclk_set_mhz * 1000);
 }
 
 
@@ -212,7 +212,7 @@ int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste
 	smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n",
 		requested_dcfclk_khz, actual_dcfclk_set_mhz);
 
-	return actual_dcfclk_set_mhz * 1000;
+	return (int)((long long)actual_dcfclk_set_mhz * 1000);
 }
 
 int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
@@ -230,7 +230,7 @@ int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re
 	smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n",
 		requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz);
 
-	return actual_min_ds_dcfclk_mhz * 1000;
+	return (int)((long long)actual_min_ds_dcfclk_mhz * 1000);
 }
 
 int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
@@ -248,7 +248,7 @@ int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz
 	smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n",
 		requested_dpp_khz, actual_dppclk_set_mhz);
 
-	return actual_dppclk_set_mhz * 1000;
+	return (int)((long long)actual_dppclk_set_mhz * 1000);
 }
 
 void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
@@ -399,7 +399,7 @@ int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr)
 						 0);
 
 	smu_print("%s:  SMU DPREF clk  = %d mhz\n",  __func__, dprefclk);
-	return dprefclk * 1000;
+	return (int)((long long)dprefclk * 1000);
 }
 
 int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
@@ -414,7 +414,7 @@ int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr)
 					       0);
 
 	smu_print("%s: get_dtbclk  = %dmhz\n", __func__, dtbclk);
-	return dtbclk * 1000;
+	return (int)((long long)dtbclk * 1000);
 }
 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
 void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
-- 
2.43.0

[PATCH 8/8] drm/amd/display: Promote DC to 3.2.372

[Alex Hung]

From: Taimur Hassan <Syed.Hassan@amd.com>

This version brings along the follwing updates:

- Prevent integer overflow when mhz to khz
- Remove always-false branches
- Remove redundant initializers
- Silence unused variable warning
- Initialize replay_state to PR_STATE_INVALID
- Fallback to boot snapshot for dispclk
- Skip cursor cache reset if hubp powergating is disabled

Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 32fcbedd82d4..4bdb7bb47c75 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
 struct dcn_optc_reg_state;
 struct dcn_dccg_reg_state;
 
-#define DC_VER "3.2.371"
+#define DC_VER "3.2.372"
 
 /**
  * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
-- 
2.43.0

RE: [PATCH 0/8] DC Patches Feb 25, 2026

[Wheeler, Daniel]

[Public]

Hi all,

This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.

APU
        * Single Display eDP -> 1080p 60hz, 1920x1200 165hz, 3840x2400 60hz
        * Single Display DP (SST DSC) -> 4k144hz, 4k240hz
        * Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
        * Thunderbolt -> LG Ultrafine 5k
        * MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
        * USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
        * SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
        * MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.

DGPU
        * Single Display DP (SST DSC) -> 4k144hz, 4k240hz
        * Multiple Display DP -> 4k240hz + 4k144hz
        * MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
        * MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)

The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
        * Changing display configurations and settings
        * Video/Audio playback
        * Benchmark testing
        * Suspend/Resume testing
        * Feature testing (Freesync, HDCP, etc.)

Automated testing includes (but is not limited to)
        * Script testing (scripts to automate some of the manual checks)
        * IGT testing

The testing is mainly tested on the following displays, but occasionally there are tests with other displays
        * Samsung G8 Neo 4k240hz
        * Samsung QN55QN95B 4k 120hz
        * Acer XV322QKKV 4k144hz
        * HP U27 4k Wireless 4k60hz
        * LG 27UD58B 4k60hz
        * LG 32UN650WA 4k60hz
        * LG Ultrafine 5k 5k60hz
        * AU Optronics B140HAN01.1 1080p 60hz eDP
        * AU Optronics B160UAN01.J 1920x1200 165hz eDP
        * Samsung ATNA60YV02-0 3840x2400 60Hz OLED eDP


The patchset consists of the amd-staging-drm-next branch (Head commit - 0809aaeac51f26cd340f626d6446c85b04919d33 -> drm/amd/display: Promote DC to 3.2.371) with new patches added on top of it.

Tested on Ubuntu 24.04.3, on Wayland and X11, using Gnome.

Tested-by: Dan Wheeler <daniel.wheeler@amd.com>



Thank you,

Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com



-----Original Message-----
From: Hung, Alex <Alex.Hung@amd.com>
Sent: Wednesday, February 25, 2026 6:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Li, Roman <Roman.Li@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Chung, ChiaHsuan (Tom) <ChiaHsuan.Chung@amd.com>; Zuo, Jerry <Jerry.Zuo@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Wu, Ray <Ray.Wu@amd.com>; LIPSKI, IVAN <IVAN.LIPSKI@amd.com>; Hung, Alex <Alex.Hung@amd.com>
Subject: [PATCH 0/8] DC Patches Feb 25, 2026

This DC patchset brings improvements in multiple areas. In summary, we have:
* Prevent integer overflow when mhz to khz
* Remove always-false branches
* Remove redundant initializers
* Silence unused variable warning
* Initialize replay_state to PR_STATE_INVALID
* Fallback to boot snapshot for dispclk
* Skip cursor cache reset if hubp powergating is disabled

Cc: Dan Wheeler <daniel.wheeler@amd.com>

Alex Hung (3):
  drm/amd/display: Remove redundant initializers
  drm/amd/display: Remove always-false branches
  drm/amd/display: Prevent integer overflow when mhz to khz

Benjamin Nwankwo (1):
  drm/amd/display: Skip cursor cache reset if hubp powergating is
    disabled

Clay King (1):
  drm/amd/display: Silence unused variable warning

Dillon Varone (1):
  drm/amd/display: Fallback to boot snapshot for dispclk

Ivan Lipski (1):
  drm/amd/display: Initialize replay_state to PR_STATE_INVALID

Taimur Hassan (1):
  drm/amd/display: Promote DC to 3.2.372

 .../amd/display/dc/clk_mgr/dcn35/dcn35_smu.c  | 14 ++++++------  .../amd/display/dc/clk_mgr/dcn42/dcn42_smu.c  | 22 +++++++++----------
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../display/dc/dml2_0/dml2_dc_resource_mgmt.c |  6 ++---  .../drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c  |  7 +++---  .../drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c  |  5 -----
 .../amd/display/dc/hubp/dcn10/dcn10_hubp.c    |  6 +++--
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c |  6 ++++-
 .../amd/display/dc/hwss/dcn42/dcn42_hwseq.c   |  6 +----
 .../dc/link/protocols/link_dp_panel_replay.c  |  2 +-
 .../dc/resource/dcn42/dcn42_resource.c        |  4 ++--
 11 files changed, 39 insertions(+), 41 deletions(-)

--
2.43.0