From: "Timur Kristóf" <timur.kristof@gmail.com>
To: amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com,
christian.koenig@amd.com
Cc: "Timur Kristóf" <timur.kristof@gmail.com>
Subject: [PATCH 6/7] Documentation/gpu: Add TCC, update TCP in amdgpu glossary
Date: Thu, 16 Apr 2026 22:26:42 +0200 [thread overview]
Message-ID: <20260416202643.25350-7-timur.kristof@gmail.com> (raw)
In-Reply-To: <20260416202643.25350-1-timur.kristof@gmail.com>
These are the L2 and L1 cache on some AMD GPU architectures.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 033167025fcca..d553dd599c966 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at
TC
Texture Cache
+ TCC
+ Texture Cache per Channel - L2 cache attached to the memory channels.
+ May be used when shader cores are accessing memory.
+ Despite "Texture" in the name, this is used by any kind of memory access.
+ TCCs may be mapped to TCPs, depending on the architecture.
+
TCP (AMDGPU)
- Texture Cache per Pipe. Even though the name "Texture" is part of this
+ Texture Cache per Pipe - L1 cache attached to each CU.
+ Even though the name "Texture" is part of this
acronym, the TCP represents the path to memory shaders; i.e., it is not
related to texture. The name is a leftover from older designs where shader
stages had different cache designs; it refers to the L1 cache in older
--
2.53.0
next prev parent reply other threads:[~2026-04-16 20:26 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-16 20:26 [PATCH 0/7] Various SI fixes, fix Radeon HD 7870 XT Timur Kristóf
2026-04-16 20:26 ` [PATCH 1/7] drm/amdgpu/gmc: Fix AMDGPU_GART_PLACEMENT_LOW to not overlap with VRAM Timur Kristóf
2026-04-17 10:58 ` Christian König
2026-04-16 20:26 ` [PATCH 2/7] drm/amdgpu/vce: Align VCPU BO to a power of two address Timur Kristóf
2026-04-17 7:08 ` Christian König
2026-04-16 20:26 ` [PATCH 3/7] drm/amdgpu: Add alignment to amdgpu_gtt_mgr_alloc_entries() Timur Kristóf
2026-04-16 20:26 ` [PATCH 4/7] drm/amdgpu/vce1: Fix workaround to ensure low 32-bit VCPU address Timur Kristóf
2026-04-17 7:21 ` Christian König
2026-04-16 20:26 ` [PATCH 5/7] drm/amdgpu/uvd3.1: Don't validate the firmware when already validated Timur Kristóf
2026-04-17 7:22 ` Christian König
2026-04-16 20:26 ` Timur Kristóf [this message]
2026-04-17 7:24 ` [PATCH 6/7] Documentation/gpu: Add TCC, update TCP in amdgpu glossary Christian König
2026-04-17 8:36 ` Timur Kristóf
2026-04-17 9:03 ` Christian König
2026-04-16 20:26 ` [PATCH 7/7] drm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs Timur Kristóf
2026-04-17 12:56 ` Christian König
2026-04-17 13:36 ` Alex Deucher
2026-04-17 14:09 ` Timur Kristóf
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260416202643.25350-7-timur.kristof@gmail.com \
--to=timur.kristof@gmail.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=christian.koenig@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox