Re: [PATCH 7/7] drm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs

["Timur Kristóf" <timur.kristof@gmail.com>]

On 2026. április 17., péntek 15:36:20 közép-európai nyári idő Alex Deucher 
wrote:
> > > +static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev)
> > > +{
> > > +     u32 i, tcc, tcp_addr_config, num_active_tcc = 0;
> > > +     u64 chan_steer, patched_chan_steer = 0;
> > > +     const u32 num_max_tcc =
> > > adev->gfx.config.max_texture_channel_caches;
> > > +     const u32 dis_tcc_mask = amdgpu_gfx_create_bitmask(num_max_tcc) &
> > > +                              REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE),
> > > +                                            CGTS_TCC_DISABLE,
> > > TCC_DISABLE);
> I would OR dis_tcc_mask with mmCGTS_USER_TCC_DISABLE as well in case
> someone has set additional TCCs to disable as well.  Other than that,
> looks good to me.

Thank you, will do.

I'll split off the VCE patches into a separate series and send a second version 
of this series with the consideration for CGTS_USER_TCC_DISABLE added.

Timur