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From: "Christian König" <christian.koenig@amd.com>
To: "Timur Kristóf" <timur.kristof@gmail.com>,
	amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com
Subject: Re: [PATCH 6/7] Documentation/gpu: Add TCC, update TCP in amdgpu glossary
Date: Fri, 17 Apr 2026 11:03:56 +0200	[thread overview]
Message-ID: <5666ee13-9798-4dee-9614-d2f0ec5e8a31@amd.com> (raw)
In-Reply-To: <4874819.vXUDI8C0e8@timur-hyperion>

On 4/17/26 10:36, Timur Kristóf wrote:
> On Friday, April 17, 2026 9:24:55 AM Central European Summer Time Christian 
> König wrote:
>> On 4/16/26 22:26, Timur Kristóf wrote:
>>> These are the L2 and L1 cache on some AMD GPU architectures.
>>>
>>> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
>>> ---
>>>
>>>  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 9 ++++++++-
>>>  1 file changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index
>>> 033167025fcca..d553dd599c966 100644
>>> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
>>> @@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at
>>>
>>>      TC
>>>      
>>>        Texture Cache
>>>
>>> +    TCC
>>> +      Texture Cache per Channel - L2 cache attached to the memory
>>> channels. +      May be used when shader cores are accessing memory.
>>> +      Despite "Texture" in the name, this is used by any kind of memory
>>> access. +      TCCs may be mapped to TCPs, depending on the architecture.
>>> +
>>
>> Good to have, but maybe put that below TCP. E.g. L1 first and then L2.
> 
> I prefer to keep the alphabetical order for consistency with the rest of the 
> glossary.

Good argument as well, feel free to add my rb to the patch as it is.

Regards,
Christian

> 
> 
> 


  reply	other threads:[~2026-04-17  9:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-16 20:26 [PATCH 0/7] Various SI fixes, fix Radeon HD 7870 XT Timur Kristóf
2026-04-16 20:26 ` [PATCH 1/7] drm/amdgpu/gmc: Fix AMDGPU_GART_PLACEMENT_LOW to not overlap with VRAM Timur Kristóf
2026-04-17 10:58   ` Christian König
2026-04-16 20:26 ` [PATCH 2/7] drm/amdgpu/vce: Align VCPU BO to a power of two address Timur Kristóf
2026-04-17  7:08   ` Christian König
2026-04-16 20:26 ` [PATCH 3/7] drm/amdgpu: Add alignment to amdgpu_gtt_mgr_alloc_entries() Timur Kristóf
2026-04-16 20:26 ` [PATCH 4/7] drm/amdgpu/vce1: Fix workaround to ensure low 32-bit VCPU address Timur Kristóf
2026-04-17  7:21   ` Christian König
2026-04-16 20:26 ` [PATCH 5/7] drm/amdgpu/uvd3.1: Don't validate the firmware when already validated Timur Kristóf
2026-04-17  7:22   ` Christian König
2026-04-16 20:26 ` [PATCH 6/7] Documentation/gpu: Add TCC, update TCP in amdgpu glossary Timur Kristóf
2026-04-17  7:24   ` Christian König
2026-04-17  8:36     ` Timur Kristóf
2026-04-17  9:03       ` Christian König [this message]
2026-04-16 20:26 ` [PATCH 7/7] drm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs Timur Kristóf
2026-04-17 12:56   ` Christian König
2026-04-17 13:36     ` Alex Deucher
2026-04-17 14:09       ` Timur Kristóf

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