[PATCH v4 08/10] drm/amdgpu/mes: route NORMAL aggregated doorbell through global agdb_bo

[Jesse Zhang <Jesse.Zhang@amd.com>]

From: "Jesse.zhang" <Jesse.zhang@amd.com>

SDMA UMQ submits cannot reliably wake the SDMA engine via the per-queue
doorbell because LSDMA programs the HQD-slot DOORBELL_OFFSET register
asynchronously after MES MAP_QUEUE — early rings hit a stale slot and
get silently dropped.  Going through the MES aggregated doorbell works,
but today's slot lives inside the MES kernel doorbell page, which is
not user-mappable.  This forces every SDMA UMQ submit through
amdgpu_userq_signal_ioctl just so the kernel can WDOORBELL32() the
agg slot — defeating the purpose of user mode queues.

Allocate the NORMAL-priority aggregated doorbell inside the global
adev->agdb_bo.  MES is told via SET_HW_RESOURCES to monitor the new
location — code unchanged because it reads
mes->aggregated_doorbells[NORMAL] which now points into agdb_bo.

Suggested-by:  Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c  | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  9 +++++++++
 2 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index bdf2561b5404..974dd7a3fc4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -28,6 +28,7 @@
 #include "amdgpu.h"
 #include "soc15_common.h"
 #include "amdgpu_mes_ctx.h"
+#include "amdgpu_doorbell.h"
 
 #define AMDGPU_MES_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
 #define AMDGPU_ONE_DOORBELL_SIZE 8
@@ -57,6 +58,29 @@ static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev)
 		set_bit(i, mes->doorbell_bitmap);
 	}
 
+	/*
+	 * Relocate the NORMAL-priority aggregated doorbell into the global
+	 * aggregated-doorbell BO so userspace SDMA UMQs can mmap it (via
+	 * AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL) and ring it directly,
+	 * bypassing signal_ioctl.  GFX/COMPUTE NORMAL queues are unaffected
+	 * functionally — they don't actively ring the agg doorbell; the HW
+	 * CP_UNMAPPED_DOORBELL intercept wakes MES for them.  SDMA has no
+	 * such intercept and needs an explicit wake path.  Other priorities
+	 * stay in the MES kernel doorbell page.
+	 */
+	if (adev->agdb_bo) {
+		int r = amdgpu_bo_reserve(adev->agdb_bo, true);
+
+		if (r)
+			return r;
+		adev->sdma.agdb_offset = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 << 1;
+		adev->mes.aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] =
+			amdgpu_doorbell_index_on_bar(adev, adev->agdb_bo,
+						     adev->sdma.agdb_offset,
+						     sizeof(u32));
+		amdgpu_bo_unreserve(adev->agdb_bo);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 2bf365609775..11cefb4c3a27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -144,6 +144,15 @@ struct amdgpu_sdma {
 	struct list_head	reset_callback_list;
 	bool			no_user_submission;
 	bool			disable_uq;
+	/*
+	 * Dword offset within adev->agdb_bo for the SDMA UMQ aggregated
+	 * doorbell.  MES is told via SET_HW_RESOURCES to monitor this slot
+	 * for NORMAL priority wakes.  Userspace mmaps adev->agdb_bo (via
+	 * AMDGPU_GEM_GLOBAL_AGGREGATED_DOORBELL) and writes WPTR here to
+	 * wake SDMA UMQs without going through signal_ioctl.  Reported via
+	 * AMDGPU_INFO_DOORBELL with query_hw_ip.type = AMDGPU_HW_IP_DMA.
+	 */
+	uint32_t		agdb_offset;
 	void (*get_csa_info)(struct amdgpu_device *adev,
 			     struct amdgpu_sdma_csa_info *csa_info);
 };
-- 
2.49.0