* [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock @ 2026-05-08 2:47 Andre Hirata 2026-05-08 8:43 ` Christian König 2026-05-08 11:12 ` [PATCH v2] " Andre Jun Hirata 0 siblings, 2 replies; 16+ messages in thread From: Andre Hirata @ 2026-05-08 2:47 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: Andre Jun Hirata, Gabriel Dimant, Guilherme Gabriel, amd-gfx, dri-devel From: Andre Jun Hirata <andrejhirata@usp.br> Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 384 ++++++++++------------------ 1 file changed, 135 insertions(+), 249 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..fc8f137a2 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -46,10 +47,9 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -62,10 +62,9 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -80,13 +79,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,9 +113,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -126,9 +121,9 @@ int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + ret = smu_set_gfx_power_up_by_imu(smu); + } msleep(10); @@ -144,13 +139,10 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -163,13 +155,10 @@ int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -184,13 +173,10 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } return ret; @@ -216,12 +202,9 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_asic_baco_capability(pp_handle); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -234,12 +217,9 @@ int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->asic_reset_mode_2(pp_handle); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -252,12 +232,9 @@ int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -270,18 +247,15 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } @@ -291,9 +265,8 @@ bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) bool support_mode1_reset = false; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); } return support_mode1_reset; @@ -305,9 +278,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) int ret = -EOPNOTSUPP; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -319,9 +291,8 @@ bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) bool support_link_reset = false; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); } return support_link_reset; @@ -333,9 +304,8 @@ int amdgpu_dpm_link_reset(struct amdgpu_device *adev) int ret = -EOPNOTSUPP; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -352,10 +322,9 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, return 0; if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->switch_power_profile( adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -371,10 +340,9 @@ int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, return 0; if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->pause_power_profile( adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -387,10 +355,9 @@ int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, int ret = 0; if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, pstate); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -404,9 +371,8 @@ int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -419,9 +385,8 @@ ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, int ret = -EOPNOTSUPP; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -434,9 +399,8 @@ int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int ret = -EOPNOTSUPP; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -450,9 +414,8 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) int ret = 0; if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -467,10 +430,9 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, int ret = 0; if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_clockgating_by_smu(pp_handle, msg_id); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -485,10 +447,9 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, int ret = -EOPNOTSUPP; if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->smu_i2c_bus_access(pp_handle, acquire); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -497,7 +458,7 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +471,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -524,12 +484,11 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso return -EINVAL; if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -541,9 +500,8 @@ int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit int ret = -EOPNOTSUPP; if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -555,9 +513,8 @@ int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) int ret = -EOPNOTSUPP; if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -583,9 +540,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +549,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +583,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,25 +626,23 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) @@ -696,10 +650,9 @@ int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) int ret = 0; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); } return ret; @@ -713,9 +666,8 @@ int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -728,9 +680,8 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t si if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -743,9 +694,8 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -766,9 +716,8 @@ bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -781,9 +730,8 @@ int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -796,9 +744,8 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -811,9 +758,8 @@ bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -831,12 +777,11 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -867,9 +812,8 @@ int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -884,9 +828,8 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -899,9 +842,8 @@ int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -914,9 +856,8 @@ int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -929,9 +870,8 @@ int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -944,9 +884,8 @@ int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -969,12 +908,11 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, @@ -986,9 +924,8 @@ int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1002,10 +939,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); return vstate; } @@ -1015,11 +951,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); @@ -1027,16 +963,15 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; -out: - mutex_unlock(&adev->pm.mutex); + return; } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + adev->pm.dpm.user_state = state; + } if (is_support_sw_smu(adev)) return; @@ -1055,12 +990,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1156,10 +1090,9 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1174,11 +1107,10 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1194,10 +1126,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1213,12 +1144,11 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1234,12 +1164,11 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1255,12 +1184,11 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1274,10 +1202,9 @@ int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1290,10 +1217,9 @@ int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1308,11 +1234,10 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1325,9 +1250,8 @@ int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1339,10 +1263,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1362,9 +1286,8 @@ int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1376,10 +1299,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1400,10 +1323,9 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1417,11 +1339,10 @@ int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1434,10 +1355,9 @@ int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1451,10 +1371,9 @@ ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1468,10 +1387,9 @@ int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1485,10 +1403,9 @@ int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1502,10 +1419,9 @@ int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1519,10 +1435,9 @@ int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1536,10 +1451,9 @@ int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1553,10 +1467,9 @@ int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1572,12 +1485,11 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1592,10 +1504,9 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1607,9 +1518,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1532,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1640,11 +1549,10 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1706,11 +1614,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1742,10 +1649,9 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1760,11 +1666,10 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1778,10 +1683,9 @@ int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1796,11 +1700,10 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1815,11 +1718,10 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1833,10 +1735,9 @@ int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1850,10 +1751,9 @@ int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1867,10 +1767,9 @@ int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1882,9 +1781,8 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, @@ -1896,10 +1794,9 @@ int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1913,10 +1810,9 @@ int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1929,10 +1825,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,10 +1838,9 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, @@ -1958,11 +1852,9 @@ int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -1975,10 +1867,9 @@ int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -1993,11 +1884,10 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -2011,10 +1901,9 @@ int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -2043,9 +1932,8 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); return ret; } @@ -2070,10 +1958,9 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, return support_temp_metrics; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); support_temp_metrics = pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); } return support_temp_metrics; @@ -2103,10 +1990,9 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); return ret; } -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 2:47 [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock Andre Hirata @ 2026-05-08 8:43 ` Christian König 2026-05-08 10:36 ` Andre Jun Hirata 2026-05-08 11:12 ` [PATCH v2] " Andre Jun Hirata 1 sibling, 1 reply; 16+ messages in thread From: Christian König @ 2026-05-08 8:43 UTC (permalink / raw) To: Andre Hirata, kenneth.feng, alexander.deucher, airlied, simona Cc: Gabriel Dimant, Guilherme Gabriel, amd-gfx, dri-devel Just two notes, apart from that looks like a nice cleanup to me. On 5/8/26 04:47, Andre Hirata wrote: > @@ -46,10 +47,9 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) > if (!pp_funcs->get_sclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > > return ret; In a lot of cases you can now turn the patter "ret = f(...); return ret;" into just return f(..); and potentially drop the ret variable. > } > > @@ -291,9 +265,8 @@ bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) > bool support_mode1_reset = false; > > if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > support_mode1_reset = smu_mode1_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > } > > return support_mode1_reset; For cases like this here the coding pattern to check the pre-requisites and abort early is usually better. So this example here would become: if (!is_support_sw_smu(adev)) return false; guard(mutex)(&adev->pm.mutex); return smu_mode1_reset_is_support(smu); Which as far as I can see is less code and much easier to read/understand. But both suggestions could be a separate patch if you want to keep this one as it is. Regards, Christian. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 8:43 ` Christian König @ 2026-05-08 10:36 ` Andre Jun Hirata 0 siblings, 0 replies; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-08 10:36 UTC (permalink / raw) To: christian.koenig Cc: airlied, alexander.deucher, amd-gfx, andrejhirata, dri-devel, gabriel.dimant, guilhermesangabriel, kenneth.feng, simona Thanks for the feedback! I'll prepare a v2 incorporating both suggestions. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 2:47 [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock Andre Hirata 2026-05-08 8:43 ` Christian König @ 2026-05-08 11:12 ` Andre Jun Hirata 2026-05-08 12:44 ` Christian König 2026-05-08 14:21 ` [PATCH v3] " Andre Jun Hirata 1 sibling, 2 replies; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-08 11:12 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 847 +++++++++------------------- 1 file changed, 264 insertions(+), 583 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..4583985ce 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,9 +107,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -126,9 +115,9 @@ int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + ret = smu_set_gfx_power_up_by_imu(smu); + } msleep(10); @@ -139,44 +128,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +160,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +188,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +225,64 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return false; } - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu) } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); + return false; } - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +290,88 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->switch_power_profile) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->pause_power_profile) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->set_df_cstate) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +379,13 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +394,14 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,22 +410,20 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +436,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -518,49 +443,43 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) { + return -EINVAL; + } + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) { + return -EOPNOTSUPP; } - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +502,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +511,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +545,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,39 +588,34 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; - - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, - enable); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return 0; } - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + enable); } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) @@ -713,11 +626,8 @@ int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) @@ -728,11 +638,8 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t si if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) @@ -743,11 +650,8 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -766,11 +670,8 @@ bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) @@ -781,11 +682,8 @@ int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) @@ -796,11 +694,8 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) @@ -811,11 +706,8 @@ bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +715,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +749,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +762,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +832,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +860,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,11 +870,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); @@ -1027,16 +882,15 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; -out: - mutex_unlock(&adev->pm.mutex); + return; } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + adev->pm.dpm.user_state = state; + } if (is_support_sw_smu(adev)) return; @@ -1055,12 +909,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +1004,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +1018,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1038,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, - table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + table); } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1049,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1066,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1083,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1124,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1152,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1170,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1185,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1204,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1336,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,17 +1352,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) @@ -1607,9 +1368,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1382,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1394,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1453,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1460,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1488,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1502,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1530,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1545,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1601,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1639,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1652,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1688,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1729,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1752,16 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); + if (!is_support_sw_smu(adev)) { + return false; } - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1783,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 11:12 ` [PATCH v2] " Andre Jun Hirata @ 2026-05-08 12:44 ` Christian König 2026-05-08 14:21 ` [PATCH v3] " Andre Jun Hirata 1 sibling, 0 replies; 16+ messages in thread From: Christian König @ 2026-05-08 12:44 UTC (permalink / raw) To: Andre Jun Hirata, kenneth.feng, alexander.deucher, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel On 5/8/26 13:12, Andre Jun Hirata wrote: > Use guard() and scoped_guard() for handling mutex lock instead of > manually locking and unlocking the mutex. This prevents forgotten > locks due to early exits and removes the need of gotos. > > Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> > Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> > Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> > Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> > Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Just a few more stile nits below, with those fixed Reviewed-by: Christian König <christian.koenig@amd.com> > --- > v2: incorporate Christian König's suggestions: > - use return f() directly instead of ret = f(); return ret; > - use early return pattern before guard() where applicable > > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 847 +++++++++------------------- > 1 file changed, 264 insertions(+), 583 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > index feadf604b..4583985ce 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > @@ -30,6 +30,7 @@ > #include "amd_pcie.h" > #include "amdgpu_display.h" > #include "hwmgr.h" > +#include <linux/cleanup.h> > #include <linux/power_supply.h> > #include "amdgpu_smu.h" > > @@ -41,33 +42,25 @@ > int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; > bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && > (!is_vcn || adev->vcn.num_vcn_inst == 1)) { > dev_dbg(adev->dev, "IP block%d already in the target %s state!", > block_type, gate ? "gate" : "ungate"); > - goto out_unlock; > + return ret; > } > > switch (block_type) { > @@ -115,9 +107,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > if (!ret) > atomic_set(&adev->pm.pwr_state[block_type], pwr_state); > > -out_unlock: > - mutex_unlock(&adev->pm.mutex); > - > return ret; > } > > @@ -126,9 +115,9 @@ int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) > struct smu_context *smu = adev->powerplay.pp_handle; > int ret = -EOPNOTSUPP; While at it this initialization is superflous since the value is overwritten directly below. > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_gfx_power_up_by_imu(smu); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + ret = smu_set_gfx_power_up_by_imu(smu); > + } > > msleep(10); > > @@ -139,44 +128,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* enter BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 1); > } > > int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* exit BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 0); > } > > int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, > enum pp_mp1_state mp1_state) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > if (mp1_state == PP_MP1_STATE_FLR) { > @@ -184,23 +160,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, > if (amdgpu_sriov_vf(adev)) > adev->pm.dpm_enabled = false; > } else if (pp_funcs && pp_funcs->set_mp1_state) { > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->set_mp1_state( > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_mp1_state( > adev->powerplay.pp_handle, > mp1_state); > - > - mutex_unlock(&adev->pm.mutex); > } > > - return ret; > + return 0; > } > > int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret; > > if (!pp_funcs || !pp_funcs->get_asic_baco_capability) > return 0; > @@ -216,49 +188,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) > if (adev->in_s3) > return 0; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->get_asic_baco_capability(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_asic_baco_capability(pp_handle); > } > > int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_mode_2) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_mode_2(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_mode_2(pp_handle); > } > > int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); > } > > int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) > @@ -270,75 +225,64 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > /* enter BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > if (ret) > - goto out; > + return ret; > > /* exit BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > -out: > - mutex_unlock(&adev->pm.mutex); > return ret; > } > > bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_mode1_reset = false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_mode1_reset = smu_mode1_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return false; > } The {} should be dropped around single line if. Same on a couple of other locations. I suggest to run checkpatch.pl once more, it will most likely complain. Regards, Christian. > > - return support_mode1_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset_is_support(smu) > } > > int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_mode1_reset(smu); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset(smu); > } > > bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_link_reset = false; > > if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_link_reset = smu_link_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > + return false; > } > > - return support_link_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset_is_support(smu); > } > > int amdgpu_dpm_link_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_link_reset(smu); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset(smu); > } > > int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, > @@ -346,100 +290,88 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, > bool en) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->switch_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->switch_power_profile( > - adev->powerplay.pp_handle, type, en); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->switch_power_profile) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->switch_power_profile( > + adev->powerplay.pp_handle, type, en); > } > > int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, > bool pause) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->pause_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->pause_power_profile( > - adev->powerplay.pp_handle, pause); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->pause_power_profile) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->pause_power_profile( > + adev->powerplay.pp_handle, pause); > } > > int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, > uint32_t pstate) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_xgmi_pstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > - pstate); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > + pstate); > } > > int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, > uint32_t cstate) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > > - if (pp_funcs && pp_funcs->set_df_cstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_df_cstate(pp_handle, cstate); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->set_df_cstate) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_df_cstate(pp_handle, cstate); > } > > ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, > enum pp_pm_policy p_type, char *buf) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_pm_policy_info(smu, p_type, buf); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_pm_policy_info(smu, p_type, buf); > } > > int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, > int policy_level) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_pm_policy(smu, policy_type, policy_level); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_pm_policy(smu, policy_type, policy_level); > } > > int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) > @@ -447,15 +379,13 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->enable_mgpu_fan_boost(pp_handle); > } > > int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, > @@ -464,16 +394,14 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_clockgating_by_smu(pp_handle, > - msg_id); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_clockgating_by_smu(pp_handle, > + msg_id); > } > > int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, > @@ -482,22 +410,20 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->smu_i2c_bus_access(pp_handle, > - acquire); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return = pp_funcs->smu_i2c_bus_access(pp_handle, > + acquire); > } > > void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) > { > if (adev->pm.dpm_enabled) { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (power_supply_is_system_supplied() > 0) > adev->pm.ac_power = true; > else > @@ -510,7 +436,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) > if (is_support_sw_smu(adev)) > smu_set_ac_dc(adev->powerplay.pp_handle); > > - mutex_unlock(&adev->pm.mutex); > } > } > > @@ -518,49 +443,43 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso > void *data, uint32_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EINVAL; > > if (!data || !size) > return -EINVAL; > > - if (pp_funcs && pp_funcs->read_sensor) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, > + if (!pp_funcs || !pp_funcs->read_sensor) { > + return -EINVAL; > + } > + > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->read_sensor(adev->powerplay.pp_handle, > sensor, > data, > size); > - mutex_unlock(&adev->pm.mutex); > - } > - > - return ret; > } > > int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); > - mutex_unlock(&adev->pm.mutex); > + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) { > + return -EOPNOTSUPP; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) > @@ -583,9 +502,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) > amdgpu_fence_wait_empty(ring); > } > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) > @@ -593,14 +511,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.uvd_active = true; > - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; > - } else { > - adev->pm.dpm.uvd_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.uvd_active = true; > + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; > + } else { > + adev->pm.dpm.uvd_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -627,15 +545,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.vce_active = true; > - /* XXX select vce level based on ring/task */ > - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; > - } else { > - adev->pm.dpm.vce_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.vce_active = true; > + /* XXX select vce level based on ring/task */ > + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; > + } else { > + adev->pm.dpm.vce_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -670,39 +588,34 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) > int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int r = 0; > + int ret = 0; > > if (!pp_funcs || !pp_funcs->load_firmware || > (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) > return 0; > > - mutex_lock(&adev->pm.mutex); > - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); > - if (r) { > + guard(mutex)(&adev->pm.mutex); > + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); > + if (ret) { > pr_err("smu firmware loading failed\n"); > - goto out; > + return ret; > } > > if (smu_version) > *smu_version = adev->pm.fw_version; > > -out: > - mutex_unlock(&adev->pm.mutex); > - return r; > + return ret; > } > > int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) > { > - int ret = 0; > - > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > - enable); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return 0; > } > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > + enable); > } > > int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) > @@ -713,11 +626,8 @@ int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_pages_num(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_pages_num(smu, size); > } > > int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) > @@ -728,11 +638,8 @@ int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t si > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_channel_flag(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_channel_flag(smu, size); > } > > int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) > @@ -743,11 +650,8 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_rma_reason(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_rma_reason(smu); > } > > /** > @@ -766,11 +670,8 @@ bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma_is_supported(smu); > } > > int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) > @@ -781,11 +682,8 @@ int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma(smu, inst_mask); > } > > int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) > @@ -796,11 +694,8 @@ int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn(smu, inst_mask); > } > > bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) > @@ -811,11 +706,8 @@ bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn_is_supported(smu); > } > > int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, > @@ -823,22 +715,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, > uint32_t *min, > uint32_t *max) > { > - int ret = 0; > - > if (type != PP_SCLK) > return -EINVAL; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, > SMU_SCLK, > min, > max); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, > @@ -862,16 +749,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, > int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_write_watermarks_table(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_write_watermarks_table(smu); > } > > int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, > @@ -879,76 +762,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, > uint64_t event_arg) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_wait_for_event(smu, event, event_arg); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_wait_for_event(smu, event, event_arg); > } > > int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_entrycount_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_entrycount_gfxoff(smu, value); > } > > int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_status_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_status_gfxoff(smu, value); > } > > uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > @@ -969,28 +832,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, > enum gfx_change_state state) > { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (adev->powerplay.pp_funcs && > adev->powerplay.pp_funcs->gfx_state_change_set) > ((adev)->powerplay.pp_funcs->gfx_state_change_set( > (adev)->powerplay.pp_handle, state)); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, > void *umc_ecc) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_ecc_info(smu, umc_ecc); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_ecc_info(smu, umc_ecc); > } > > struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, > @@ -1002,12 +860,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, > if (!pp_funcs->get_vce_clock_state) > return NULL; > > - mutex_lock(&adev->pm.mutex); > - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > idx); > - mutex_unlock(&adev->pm.mutex); > - > - return vstate; > } > > void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > @@ -1015,11 +870,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > if (!pp_funcs->get_current_power_state) { > *state = adev->pm.dpm.user_state; > - goto out; > + return; > } > > *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); > @@ -1027,16 +882,15 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > *state > POWER_STATE_TYPE_INTERNAL_3DPERF) > *state = adev->pm.dpm.user_state; > > -out: > - mutex_unlock(&adev->pm.mutex); > + return; > } > > void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, > enum amd_pm_state_type state) > { > - mutex_lock(&adev->pm.mutex); > - adev->pm.dpm.user_state = state; > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + adev->pm.dpm.user_state = state; > + } > > if (is_support_sw_smu(adev)) > return; > @@ -1055,12 +909,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device > if (!pp_funcs) > return AMD_DPM_FORCED_LEVEL_AUTO; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (pp_funcs->get_performance_level) > level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); > else > level = adev->pm.dpm.forced_level; > - mutex_unlock(&adev->pm.mutex); > > return level; > } > @@ -1151,17 +1004,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, > struct pp_states_info *states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pp_num_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, > @@ -1169,24 +1018,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, > enum amd_pm_state_type *user_state) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->dispatch_tasks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > task_id, > user_state); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!table) > return -EINVAL; > @@ -1194,12 +1038,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) > if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, > - table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return = pp_funcs->get_pp_table(adev->powerplay.pp_handle, > + table); > } > > int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, > @@ -1208,19 +1049,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fine_grain_clk_vol) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, > @@ -1229,19 +1066,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->odn_edit_dpm_table) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, > @@ -1250,52 +1083,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, > int *offset) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->emit_clock_levels) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > type, > buf, > offset); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, > uint64_t ppfeature_masks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > ppfeature_masks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, > @@ -1303,33 +1124,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, > uint32_t mask) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->force_clock_level) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, > type, > mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1339,10 +1152,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_sclk_od) > - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_sclk_od) > + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1357,16 +1170,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1376,10 +1185,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_mclk_od) > - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_mclk_od) > + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1395,170 +1204,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, > char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_profile_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, > long *input, uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_profile_mode) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_gpu_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pm_metrics) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, > uint32_t *fan_mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > fan_mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, > uint32_t mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, > @@ -1567,19 +1336,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, > enum pp_power_type power_type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_limit) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, > limit, > pp_limit_level, > power_type); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, > @@ -1587,17 +1352,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, > uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_limit) > return -EINVAL; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, > limit_type, limit); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) > @@ -1607,9 +1368,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > cclk_dpm_supported = is_support_cclk_dpm(adev); > - mutex_unlock(&adev->pm.mutex); > > return (int)cclk_dpm_supported; > } > @@ -1622,10 +1382,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade > if (!pp_funcs->debugfs_print_current_performance_level) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, > m); > - mutex_unlock(&adev->pm.mutex); > > return 0; > } > @@ -1635,18 +1394,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, > size_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_smu_prv_buf_details) > return -ENOSYS; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > addr, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) > @@ -1698,7 +1453,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!buf || !size) > return -EINVAL; > @@ -1706,13 +1460,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, > if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, > buf, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) > @@ -1737,17 +1488,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, > const struct amd_pp_display_configuration *input) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_configuration_change) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > input); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, > @@ -1755,35 +1502,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, > struct amd_pp_clocks *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, > struct amd_pp_simple_clock_info *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_display_mode_validation_clocks) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > @@ -1791,18 +1530,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > struct pp_clock_levels_with_latency *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_latency) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > @@ -1810,69 +1545,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > struct pp_clock_levels_with_voltage *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_voltage) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, > void *clock_ranges) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_watermarks_for_clocks_ranges) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, > clock_ranges); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, > struct pp_display_clock_request *clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_clock_voltage_request) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, > struct amd_pp_clock_info *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_current_clocks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) > @@ -1882,43 +1601,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) > if (!pp_funcs->notify_smu_enable_pwe) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, > uint32_t count) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_active_display_count) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > count); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, > uint32_t clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_min_deep_sleep_dcefclk) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > @@ -1929,10 +1639,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > if (!pp_funcs->set_hard_min_dcefclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > @@ -1943,44 +1652,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > if (!pp_funcs->set_hard_min_fclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, > bool disable_memory_clock_switch) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_disable_memory_clock_switch) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, > disable_memory_clock_switch); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, > struct pp_smu_nv_clock_table *max_clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_max_sustainable_clocks_by_dc) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, > max_clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > @@ -1988,35 +1688,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > unsigned int *num_states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_uclk_dpm_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > clock_values_in_khz, > num_states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, > struct dpm_clocks *clock_table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_dpm_clock_table) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > clock_table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > /** > @@ -2037,17 +1729,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, > enum smu_temp_metric_type type, void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret; > > if (!pp_funcs->get_temp_metrics || > !amdgpu_dpm_is_temp_metrics_supported(adev, type)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); > } > > /** > @@ -2064,19 +1752,16 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, > enum smu_temp_metric_type type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - bool support_temp_metrics = false; > > if (!pp_funcs->temp_metrics_is_supported) > - return support_temp_metrics; > + return false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_temp_metrics = > - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); > - mutex_unlock(&adev->pm.mutex); > + if (!is_support_sw_smu(adev)) { > + return false; > } > > - return support_temp_metrics; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); > } > > /** > @@ -2098,17 +1783,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, > void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_xcp_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 11:12 ` [PATCH v2] " Andre Jun Hirata 2026-05-08 12:44 ` Christian König @ 2026-05-08 14:21 ` Andre Jun Hirata 2026-05-08 17:23 ` [PATCH v4] " Andre Jun Hirata 1 sibling, 1 reply; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-08 14:21 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Reviewed-by: Christian König <christian.koenig@amd.com> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- 1 file changed, 261 insertions(+), 607 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..2a0f4abc4 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,9 +107,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -126,9 +115,8 @@ int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu) } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,11 +845,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); @@ -1027,16 +857,14 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; -out: - mutex_unlock(&adev->pm.mutex); + return; } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +883,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +978,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +992,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1012,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, - table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + table); } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1023,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1040,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1057,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1098,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1126,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1144,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1159,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1178,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1310,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,17 +1326,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) @@ -1607,9 +1342,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1356,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1368,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1427,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1434,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1462,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1476,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1504,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1519,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1575,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1613,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1626,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1662,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1703,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1726,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1756,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 14:21 ` [PATCH v3] " Andre Jun Hirata @ 2026-05-08 17:23 ` Andre Jun Hirata 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata 2026-05-13 5:11 ` [PATCH v4] " kernel test robot 0 siblings, 2 replies; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-08 17:23 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Reviewed-by: Christian König <christian.koenig@amd.com> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard v4: - fix build errors introduced in v3 - fix incorrect is_support_sw_smu() condition - remove accidental "return =" typos drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- 1 file changed, 261 insertions(+), 607 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..2a0f4abc4 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,9 +107,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } @@ -126,9 +115,8 @@ int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu) } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,11 +845,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); @@ -1027,16 +857,14 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; -out: - mutex_unlock(&adev->pm.mutex); + return; } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +883,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +978,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +992,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1012,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, - table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + table); } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1023,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1040,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1057,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1098,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1126,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1144,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1159,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1178,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1310,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,17 +1326,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) @@ -1607,9 +1342,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1356,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1368,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1427,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1434,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1462,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1476,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1504,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1519,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1575,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1613,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1626,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1662,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1703,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1726,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1756,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 17:23 ` [PATCH v4] " Andre Jun Hirata @ 2026-05-08 23:03 ` Andre Jun Hirata 2026-05-11 4:58 ` Wang, Yang(Kevin) ` (2 more replies) 2026-05-13 5:11 ` [PATCH v4] " kernel test robot 1 sibling, 3 replies; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-08 23:03 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard v4: - fix build errors introduced in v3 - fix incorrect is_support_sw_smu() condition - remove accidental "return =" typos v5: fix incorrect diff in v4 --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- 1 file changed, 261 insertions(+), 607 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..5fa043026 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; + int ret; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu) } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,11 +845,11 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); @@ -1027,16 +857,14 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; -out: - mutex_unlock(&adev->pm.mutex); + return; } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +883,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +978,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +992,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1012,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1023,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1040,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1057,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1098,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1126,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1144,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1159,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1178,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1310,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,17 +1326,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) @@ -1607,9 +1342,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1356,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1368,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1427,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1434,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1462,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1476,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1504,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1519,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1575,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1613,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1626,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1662,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1703,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1726,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1756,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata @ 2026-05-11 4:58 ` Wang, Yang(Kevin) 2026-05-11 12:42 ` [PATCH v6] " Andre Jun Hirata 2026-05-13 4:39 ` [PATCH v5] " kernel test robot 2026-05-13 6:12 ` kernel test robot 2 siblings, 1 reply; 16+ messages in thread From: Wang, Yang(Kevin) @ 2026-05-11 4:58 UTC (permalink / raw) To: Andre Jun Hirata, Feng, Kenneth, Deucher, Alexander, Koenig, Christian, airlied@gmail.com, simona@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, gabriel.dimant@usp.br, guilhermesangabriel@usp.br AMD General Comments inline. With that fixed, the patch is Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Best Regards, Kevin > -----Original Message----- > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Andre Jun > Hirata > Sent: Saturday, May 9, 2026 07:03 > To: Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; > airlied@gmail.com; simona@ffwll.ch > Cc: amd-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; > gabriel.dimant@usp.br; guilhermesangabriel@usp.br; Andre Jun Hirata > <andrejhirata@usp.br> > Subject: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock > > Use guard() and scoped_guard() for handling mutex lock instead of > manually locking and unlocking the mutex. This prevents forgotten > locks due to early exits and removes the need of gotos. > > Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> > Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> > Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> > Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> > Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> > > v2: incorporate Christian König's suggestions: > - use return f() directly instead of ret = f(); return ret; > - use early return pattern before guard() where applicable > > v3: fix style nits pointed by Christian König: > - drop superfluous ret initialization in set_gfx_power_up_by_imu > - drop unnecessary braces around single-line scoped_guard > > v4: > - fix build errors introduced in v3 > - fix incorrect is_support_sw_smu() condition > - remove accidental "return =" typos > > v5: fix incorrect diff in v4 > --- > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- > 1 file changed, 261 insertions(+), 607 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > index feadf604b..5fa043026 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > @@ -30,6 +30,7 @@ > #include "amd_pcie.h" > #include "amdgpu_display.h" > #include "hwmgr.h" > +#include <linux/cleanup.h> > #include <linux/power_supply.h> > #include "amdgpu_smu.h" > > @@ -41,33 +42,25 @@ > int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct > amdgpu_device *adev, > enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : > POWER_STATE_ON; > bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && > (!is_vcn || adev->vcn.num_vcn_inst == 1)) { > dev_dbg(adev->dev, "IP block%d already in the target %s state!", > block_type, gate ? "gate" : "ungate"); > - goto out_unlock; > + return ret; > } > > switch (block_type) { > @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct > amdgpu_device *adev, > if (!ret) > atomic_set(&adev->pm.pwr_state[block_type], pwr_state); > > -out_unlock: > - mutex_unlock(&adev->pm.mutex); > - > return ret; > } > > int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > + int ret; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_gfx_power_up_by_imu(smu); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) > + ret = smu_set_gfx_power_up_by_imu(smu); > > msleep(10); > > @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device > *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* enter BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 1); > } > > int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* exit BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 0); > } > > int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, > enum pp_mp1_state mp1_state) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > if (mp1_state == PP_MP1_STATE_FLR) { > @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device > *adev, > if (amdgpu_sriov_vf(adev)) > adev->pm.dpm_enabled = false; > } else if (pp_funcs && pp_funcs->set_mp1_state) { > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->set_mp1_state( > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_mp1_state( > adev->powerplay.pp_handle, > mp1_state); > - > - mutex_unlock(&adev->pm.mutex); > } > > - return ret; > + return 0; > } > > int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret; > > if (!pp_funcs || !pp_funcs->get_asic_baco_capability) > return 0; > @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct > amdgpu_device *adev) > if (adev->in_s3) > return 0; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->get_asic_baco_capability(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_asic_baco_capability(pp_handle); > } > > int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_mode_2) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_mode_2(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_mode_2(pp_handle); > } > > int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); > } > > int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) > @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device > *adev) > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > /* enter BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > if (ret) > - goto out; > + return ret; > > /* exit BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > -out: > - mutex_unlock(&adev->pm.mutex); > return ret; > } > > bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_mode1_reset = false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_mode1_reset = smu_mode1_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_mode1_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset_is_support(smu) [kevin]: Miss ';' ? > } > > int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_mode1_reset(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset(smu); > } > > bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_link_reset = false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_link_reset = smu_link_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_link_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset_is_support(smu); > } > > int amdgpu_dpm_link_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_link_reset(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset(smu); > } > > int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, > @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct > amdgpu_device *adev, > bool en) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->switch_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->switch_power_profile( > - adev->powerplay.pp_handle, type, en); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->switch_power_profile) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->switch_power_profile( > + adev->powerplay.pp_handle, type, en); > } > > int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, > bool pause) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->pause_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->pause_power_profile( > - adev->powerplay.pp_handle, pause); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->pause_power_profile) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->pause_power_profile( > + adev->powerplay.pp_handle, pause); > } > > int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, > uint32_t pstate) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_xgmi_pstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > - pstate); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > + pstate); > } > > int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, > uint32_t cstate) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > > - if (pp_funcs && pp_funcs->set_df_cstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_df_cstate(pp_handle, cstate); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_df_cstate) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_df_cstate(pp_handle, cstate); > } > > ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, > enum pp_pm_policy p_type, char *buf) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_pm_policy_info(smu, p_type, buf); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_pm_policy_info(smu, p_type, buf); > } > > int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, > int policy_level) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_pm_policy(smu, policy_type, policy_level); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_pm_policy(smu, policy_type, policy_level); > } > > int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) > @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct > amdgpu_device *adev) > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->enable_mgpu_fan_boost(pp_handle); > } > > int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, > @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct > amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_clockgating_by_smu(pp_handle, > - msg_id); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_clockgating_by_smu(pp_handle, > + msg_id); > } > > int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, > @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct > amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->smu_i2c_bus_access(pp_handle, > - acquire); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->smu_i2c_bus_access(pp_handle, > + acquire); > } > > void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) > { > if (adev->pm.dpm_enabled) { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (power_supply_is_system_supplied() > 0) > adev->pm.ac_power = true; > else > @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct > amdgpu_device *adev) > if (is_support_sw_smu(adev)) > smu_set_ac_dc(adev->powerplay.pp_handle); > > - mutex_unlock(&adev->pm.mutex); > } > } > > @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device > *adev, enum amd_pp_sensors senso > void *data, uint32_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EINVAL; > > if (!data || !size) > return -EINVAL; > > - if (pp_funcs && pp_funcs->read_sensor) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, > + if (!pp_funcs || !pp_funcs->read_sensor) > + return -EINVAL; > + > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->read_sensor(adev->powerplay.pp_handle, > sensor, > data, > size); > - mutex_unlock(&adev->pm.mutex); > - } > - > - return ret; > } > > int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t > *limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, > limit); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, > limit); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) > @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device > *adev) > amdgpu_fence_wait_empty(ring); > } > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) > @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device > *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.uvd_active = true; > - adev->pm.dpm.state = > POWER_STATE_TYPE_INTERNAL_UVD; > - } else { > - adev->pm.dpm.uvd_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.uvd_active = true; > + adev->pm.dpm.state = > POWER_STATE_TYPE_INTERNAL_UVD; > + } else { > + adev->pm.dpm.uvd_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device > *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.vce_active = true; > - /* XXX select vce level based on ring/task */ > - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; > - } else { > - adev->pm.dpm.vce_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.vce_active = true; > + /* XXX select vce level based on ring/task */ > + adev->pm.dpm.vce_level = > AMD_VCE_LEVEL_AC_ALL; > + } else { > + adev->pm.dpm.vce_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device > *adev, bool enable) > int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t > *smu_version) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int r = 0; > + int ret = 0; > > if (!pp_funcs || !pp_funcs->load_firmware || > (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) > return 0; > > - mutex_lock(&adev->pm.mutex); > - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); > - if (r) { > + guard(mutex)(&adev->pm.mutex); > + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); > + if (ret) { > pr_err("smu firmware loading failed\n"); > - goto out; > + return ret; > } > > if (smu_version) > *smu_version = adev->pm.fw_version; > > -out: > - mutex_unlock(&adev->pm.mutex); > - return r; > + return ret; > } > > int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool > enable) > { > - int ret = 0; > + if (!is_support_sw_smu(adev)) > + return 0; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > enable); > - mutex_unlock(&adev->pm.mutex); > - } > - > - return ret; > } > > int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, > uint32_t size) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_pages_num(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_pages_num(smu, size); > } > > int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, > uint32_t size) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_channel_flag(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_channel_flag(smu, size); > } > > int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_rma_reason(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_rma_reason(smu); > } > > /** > @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct > amdgpu_device *adev) > bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool ret; > > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma_is_supported(smu); > } > > int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma(smu, inst_mask); > } > > int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn(smu, inst_mask); > } > > bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool ret; > > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn_is_supported(smu); > } > > int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, > @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct > amdgpu_device *adev, > uint32_t *min, > uint32_t *max) > { > - int ret = 0; > - > if (type != PP_SCLK) > return -EINVAL; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, > SMU_SCLK, > min, > max); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, > @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct > amdgpu_device *adev, > int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_write_watermarks_table(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_write_watermarks_table(smu); > } > > int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, > @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device > *adev, > uint64_t event_arg) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_wait_for_event(smu, event, event_arg); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_wait_for_event(smu, event, event_arg); > } > > int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_entrycount_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_entrycount_gfxoff(smu, value); > } > > int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_status_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_status_gfxoff(smu, value); > } > > uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > @@ -969,28 +807,23 @@ uint64_t > amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, > enum gfx_change_state state) > { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (adev->powerplay.pp_funcs && > adev->powerplay.pp_funcs->gfx_state_change_set) > ((adev)->powerplay.pp_funcs->gfx_state_change_set( > (adev)->powerplay.pp_handle, state)); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, > void *umc_ecc) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_ecc_info(smu, umc_ecc); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_ecc_info(smu, umc_ecc); > } > > struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device > *adev, > @@ -1002,12 +835,9 @@ struct amd_vce_state > *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, > if (!pp_funcs->get_vce_clock_state) > return NULL; > > - mutex_lock(&adev->pm.mutex); > - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > idx); > - mutex_unlock(&adev->pm.mutex); > - > - return vstate; > } > > void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > @@ -1015,11 +845,11 @@ void amdgpu_dpm_get_current_power_state(struct > amdgpu_device *adev, > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > if (!pp_funcs->get_current_power_state) { > *state = adev->pm.dpm.user_state; > - goto out; > + return; > } > > *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); > @@ -1027,16 +857,14 @@ void amdgpu_dpm_get_current_power_state(struct > amdgpu_device *adev, > *state > POWER_STATE_TYPE_INTERNAL_3DPERF) > *state = adev->pm.dpm.user_state; > > -out: > - mutex_unlock(&adev->pm.mutex); > + return; [kevin]: The 'return;' can be removed directly. > } > > void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, > enum amd_pm_state_type state) > { > - mutex_lock(&adev->pm.mutex); > - adev->pm.dpm.user_state = state; > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) > + adev->pm.dpm.user_state = state; > > if (is_support_sw_smu(adev)) > return; > @@ -1055,12 +883,11 @@ enum amd_dpm_forced_level > amdgpu_dpm_get_performance_level(struct amdgpu_device > if (!pp_funcs) > return AMD_DPM_FORCED_LEVEL_AUTO; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (pp_funcs->get_performance_level) > level = pp_funcs->get_performance_level(adev- > >powerplay.pp_handle); > else > level = adev->pm.dpm.forced_level; > - mutex_unlock(&adev->pm.mutex); > > return level; > } > @@ -1151,17 +978,13 @@ int amdgpu_dpm_get_pp_num_states(struct > amdgpu_device *adev, > struct pp_states_info *states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pp_num_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, > @@ -1169,24 +992,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device > *adev, > enum amd_pm_state_type *user_state) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->dispatch_tasks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > task_id, > user_state); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!table) > return -EINVAL; > @@ -1194,12 +1012,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device > *adev, char **table) > if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev- > >scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, > @@ -1208,19 +1023,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct > amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fine_grain_clk_vol) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, > @@ -1229,19 +1040,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct > amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->odn_edit_dpm_table) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, > @@ -1250,52 +1057,40 @@ int amdgpu_dpm_emit_clock_levels(struct > amdgpu_device *adev, > int *offset) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->emit_clock_levels) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > type, > buf, > offset); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, > uint64_t ppfeature_masks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > ppfeature_masks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, > @@ -1303,33 +1098,25 @@ int amdgpu_dpm_force_clock_level(struct > amdgpu_device *adev, > uint32_t mask) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->force_clock_level) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, > type, > mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1339,10 +1126,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device > *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_sclk_od) > - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_sclk_od) > + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1357,16 +1144,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device > *adev, uint32_t value) > int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1376,10 +1159,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device > *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_mclk_od) > - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_mclk_od) > + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1395,170 +1178,130 @@ int amdgpu_dpm_get_power_profile_mode(struct > amdgpu_device *adev, > char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_profile_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, > long *input, uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_profile_mode) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_gpu_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void > *pm_metrics, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pm_metrics) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, > uint32_t *fan_mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > fan_mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, > uint32_t mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, > @@ -1567,19 +1310,15 @@ int amdgpu_dpm_get_power_limit(struct > amdgpu_device *adev, > enum pp_power_type power_type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_limit) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, > limit, > pp_limit_level, > power_type); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, > @@ -1587,17 +1326,13 @@ int amdgpu_dpm_set_power_limit(struct > amdgpu_device *adev, > uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_limit) > return -EINVAL; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, > limit_type, limit); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) > @@ -1607,9 +1342,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct > amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > cclk_dpm_supported = is_support_cclk_dpm(adev); > - mutex_unlock(&adev->pm.mutex); > > return (int)cclk_dpm_supported; > } > @@ -1622,10 +1356,9 @@ int > amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade > if (!pp_funcs->debugfs_print_current_performance_level) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->debugfs_print_current_performance_level(adev- > >powerplay.pp_handle, > m); > - mutex_unlock(&adev->pm.mutex); > > return 0; > } > @@ -1635,18 +1368,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct > amdgpu_device *adev, > size_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_smu_prv_buf_details) > return -ENOSYS; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > addr, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) > @@ -1698,7 +1427,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device > *adev, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!buf || !size) > return -EINVAL; > @@ -1706,13 +1434,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device > *adev, > if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev- > >scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, > buf, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) > @@ -1737,17 +1462,13 @@ int amdgpu_dpm_display_configuration_change(struct > amdgpu_device *adev, > const struct amd_pp_display_configuration > *input) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_configuration_change) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > input); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, > @@ -1755,35 +1476,27 @@ int amdgpu_dpm_get_clock_by_type(struct > amdgpu_device *adev, > struct amd_pp_clocks *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, > struct amd_pp_simple_clock_info > *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_display_mode_validation_clocks) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_display_mode_validation_clocks(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_display_mode_validation_clocks(adev- > >powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > @@ -1791,18 +1504,14 @@ int > amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > struct pp_clock_levels_with_latency > *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_latency) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_latency(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_latency(adev- > >powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > @@ -1810,69 +1519,53 @@ int > amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > struct pp_clock_levels_with_voltage > *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_voltage) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_voltage(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_voltage(adev- > >powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, > void *clock_ranges) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_watermarks_for_clocks_ranges) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_watermarks_for_clocks_ranges(adev- > >powerplay.pp_handle, > clock_ranges); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, > struct pp_display_clock_request *clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_clock_voltage_request) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_clock_voltage_request(adev- > >powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, > struct amd_pp_clock_info *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_current_clocks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) > @@ -1882,43 +1575,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct > amdgpu_device *adev) > if (!pp_funcs->notify_smu_enable_pwe) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, > uint32_t count) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_active_display_count) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > count); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, > uint32_t clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_min_deep_sleep_dcefclk) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > @@ -1929,10 +1613,9 @@ void > amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > if (!pp_funcs->set_hard_min_dcefclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > @@ -1943,44 +1626,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct > amdgpu_device *adev, > if (!pp_funcs->set_hard_min_fclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device > *adev, > bool disable_memory_clock_switch) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_disable_memory_clock_switch) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_disable_memory_clock_switch(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_disable_memory_clock_switch(adev- > >powerplay.pp_handle, > > disable_memory_clock_switch); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, > struct pp_smu_nv_clock_table > *max_clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_max_sustainable_clocks_by_dc) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev- > >powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_max_sustainable_clocks_by_dc(adev- > >powerplay.pp_handle, > max_clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device > *adev, > @@ -1988,35 +1662,27 @@ enum pp_smu_status > amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > unsigned int *num_states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_uclk_dpm_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > clock_values_in_khz, > num_states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, > struct dpm_clocks *clock_table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_dpm_clock_table) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > clock_table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > /** > @@ -2037,17 +1703,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct > amdgpu_device *adev, > enum smu_temp_metric_type type, void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret; > > if (!pp_funcs->get_temp_metrics || > !amdgpu_dpm_is_temp_metrics_supported(adev, type)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, > table); > } > > /** > @@ -2064,19 +1726,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct > amdgpu_device *adev, > enum smu_temp_metric_type type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - bool support_temp_metrics = false; > > if (!pp_funcs->temp_metrics_is_supported) > - return support_temp_metrics; > + return false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_temp_metrics = > - pp_funcs->temp_metrics_is_supported(adev- > >powerplay.pp_handle, type); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_temp_metrics; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, > type); > } > > /** > @@ -2098,17 +1756,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct > amdgpu_device *adev, int xcp_id, > void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_xcp_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct > amdgpu_device *adev) > -- > 2.43.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v6] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-11 4:58 ` Wang, Yang(Kevin) @ 2026-05-11 12:42 ` Andre Jun Hirata 2026-05-11 13:50 ` Lazar, Lijo 0 siblings, 1 reply; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-11 12:42 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: Andre Jun Hirata, Gabriel Dimant, Guilherme Gabriel, Yang Wang, amd-gfx, dri-devel Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard v4: - fix build errors introduced in v3 - fix incorrect is_support_sw_smu() condition - remove accidental "return =" typos v5: fix incorrect diff in v4 v6: fix missing semicolon in smu_mode1_reset_is_support() return statement drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- 1 file changed, 260 insertions(+), 608 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..e7ffb2b1b 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; + int ret; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu); } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (power_supply_is_system_supplied() > 0) adev->pm.ac_power = true; else @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) if (is_support_sw_smu(adev)) smu_set_ac_dc(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } } @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret = 0; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,28 +845,24 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); if (*state < POWER_STATE_TYPE_DEFAULT || *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; - -out: - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +881,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +976,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +990,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1010,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1021,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1038,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1055,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1096,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1124,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_sclk_od) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1142,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1157,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) { + if (pp_funcs->set_mclk_od) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1176,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1308,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,17 +1324,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) @@ -1607,9 +1340,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); return (int)cclk_dpm_supported; } @@ -1622,10 +1354,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1366,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1425,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1432,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1460,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1474,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1502,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1517,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1573,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1611,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1624,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1660,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1701,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1724,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1754,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v6] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-11 12:42 ` [PATCH v6] " Andre Jun Hirata @ 2026-05-11 13:50 ` Lazar, Lijo 2026-05-12 23:04 ` [PATCH v7] " Andre Jun Hirata 0 siblings, 1 reply; 16+ messages in thread From: Lazar, Lijo @ 2026-05-11 13:50 UTC (permalink / raw) To: Andre Jun Hirata, kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: Gabriel Dimant, Guilherme Gabriel, Yang Wang, amd-gfx, dri-devel On 11-May-26 6:12 PM, Andre Jun Hirata wrote: > Use guard() and scoped_guard() for handling mutex lock instead of > manually locking and unlocking the mutex. This prevents forgotten > locks due to early exits and removes the need of gotos. > > Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> > Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> > Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> > Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> > Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> > > Reviewed-by: Christian König <christian.koenig@amd.com> > Reviewed-by: Yang Wang <kevinyang.wang@amd.com> > --- > v2: incorporate Christian König's suggestions: > - use return f() directly instead of ret = f(); return ret; > - use early return pattern before guard() where applicable > > v3: fix style nits pointed by Christian König: > - drop superfluous ret initialization in set_gfx_power_up_by_imu > - drop unnecessary braces around single-line scoped_guard > > v4: > - fix build errors introduced in v3 > - fix incorrect is_support_sw_smu() condition > - remove accidental "return =" typos > > v5: fix incorrect diff in v4 > > v6: fix missing semicolon in smu_mode1_reset_is_support() return statement > Thanks for the changes. A few more nits noted below. With those addressed, Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> > drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 868 +++++++++------------------- > 1 file changed, 260 insertions(+), 608 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > index feadf604b..e7ffb2b1b 100644 > --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c > @@ -30,6 +30,7 @@ > #include "amd_pcie.h" > #include "amdgpu_display.h" > #include "hwmgr.h" > +#include <linux/cleanup.h> > #include <linux/power_supply.h> > #include "amdgpu_smu.h" > > @@ -41,33 +42,25 @@ > int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, > low); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; > bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && > (!is_vcn || adev->vcn.num_vcn_inst == 1)) { > dev_dbg(adev->dev, "IP block%d already in the target %s state!", > block_type, gate ? "gate" : "ungate"); > - goto out_unlock; > + return ret; > } > > switch (block_type) { > @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, > if (!ret) > atomic_set(&adev->pm.pwr_state[block_type], pwr_state); > > -out_unlock: > - mutex_unlock(&adev->pm.mutex); > - > return ret; > } > > int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > + int ret; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_gfx_power_up_by_imu(smu); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) > + ret = smu_set_gfx_power_up_by_imu(smu); > > msleep(10); > > @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* enter BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 1); > } > > int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > + guard(mutex)(&adev->pm.mutex); > /* exit BACO state */ > - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + return pp_funcs->set_asic_baco_state(pp_handle, 0); > } > > int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, > enum pp_mp1_state mp1_state) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > if (mp1_state == PP_MP1_STATE_FLR) { > @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, > if (amdgpu_sriov_vf(adev)) > adev->pm.dpm_enabled = false; > } else if (pp_funcs && pp_funcs->set_mp1_state) { > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->set_mp1_state( > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_mp1_state( > adev->powerplay.pp_handle, > mp1_state); > - > - mutex_unlock(&adev->pm.mutex); > } > > - return ret; > + return 0; > } > > int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret; > > if (!pp_funcs || !pp_funcs->get_asic_baco_capability) > return 0; > @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) > if (adev->in_s3) > return 0; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->get_asic_baco_capability(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_asic_baco_capability(pp_handle); > } > > int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_mode_2) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_mode_2(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_mode_2(pp_handle); > } > > int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > - int ret = 0; > > if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - > - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); > - > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); > } > > int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) > @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) > if (!pp_funcs || !pp_funcs->set_asic_baco_state) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > /* enter BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 1); > if (ret) > - goto out; > + return ret; > > /* exit BACO state */ > ret = pp_funcs->set_asic_baco_state(pp_handle, 0); > - > -out: > - mutex_unlock(&adev->pm.mutex); > return ret; > } > > bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_mode1_reset = false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_mode1_reset = smu_mode1_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_mode1_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset_is_support(smu); > } > > int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_mode1_reset(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_mode1_reset(smu); > } > > bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool support_link_reset = false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_link_reset = smu_link_reset_is_support(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_link_reset; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset_is_support(smu); > } > > int amdgpu_dpm_link_reset(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_link_reset(smu); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_link_reset(smu); > } > > int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, > @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, > bool en) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->switch_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->switch_power_profile( > - adev->powerplay.pp_handle, type, en); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->switch_power_profile) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->switch_power_profile( > + adev->powerplay.pp_handle, type, en); > } > > int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, > bool pause) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (amdgpu_sriov_vf(adev)) > return 0; > > - if (pp_funcs && pp_funcs->pause_power_profile) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->pause_power_profile( > - adev->powerplay.pp_handle, pause); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->pause_power_profile) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->pause_power_profile( > + adev->powerplay.pp_handle, pause); > } > > int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, > uint32_t pstate) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_xgmi_pstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > - pstate); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, > + pstate); > } > > int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, > uint32_t cstate) > { > - int ret = 0; > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > void *pp_handle = adev->powerplay.pp_handle; > > - if (pp_funcs && pp_funcs->set_df_cstate) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_df_cstate(pp_handle, cstate); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_df_cstate) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_df_cstate(pp_handle, cstate); > } > > ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, > enum pp_pm_policy p_type, char *buf) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_pm_policy_info(smu, p_type, buf); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_pm_policy_info(smu, p_type, buf); > } > > int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, > int policy_level) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = -EOPNOTSUPP; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_pm_policy(smu, policy_type, policy_level); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_pm_policy(smu, policy_type, policy_level); > } > > int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) > @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->enable_mgpu_fan_boost(pp_handle); > } > > int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, > @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = 0; > > - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_clockgating_by_smu(pp_handle, > - msg_id); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) > + return 0; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_clockgating_by_smu(pp_handle, > + msg_id); > } > > int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, > @@ -482,22 +397,19 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, > void *pp_handle = adev->powerplay.pp_handle; > const struct amd_pm_funcs *pp_funcs = > adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->smu_i2c_bus_access(pp_handle, > - acquire); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->smu_i2c_bus_access(pp_handle, > + acquire); > } > > void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) > { > if (adev->pm.dpm_enabled) { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); Isn't scoped_guard more appropriate? Or may just return when (!adev->pm.dpm_enabled) to be consistent with the other changes. > if (power_supply_is_system_supplied() > 0) > adev->pm.ac_power = true; > else > @@ -510,7 +422,6 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) > if (is_support_sw_smu(adev)) > smu_set_ac_dc(adev->powerplay.pp_handle); > > - mutex_unlock(&adev->pm.mutex); > } > } > > @@ -518,49 +429,40 @@ int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors senso > void *data, uint32_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EINVAL; > > if (!data || !size) > return -EINVAL; > > - if (pp_funcs && pp_funcs->read_sensor) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, > + if (!pp_funcs || !pp_funcs->read_sensor) > + return -EINVAL; > + > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->read_sensor(adev->powerplay.pp_handle, > sensor, > data, > size); > - mutex_unlock(&adev->pm.mutex); > - } > - > - return ret; > } > > int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = -EOPNOTSUPP; > > - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) > + return -EOPNOTSUPP; > > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); > } > > void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) > @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) > amdgpu_fence_wait_empty(ring); > } > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) > @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.uvd_active = true; > - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; > - } else { > - adev->pm.dpm.uvd_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.uvd_active = true; > + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; > + } else { > + adev->pm.dpm.uvd_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) > int ret = 0; > > if (adev->family == AMDGPU_FAMILY_SI) { > - mutex_lock(&adev->pm.mutex); > - if (enable) { > - adev->pm.dpm.vce_active = true; > - /* XXX select vce level based on ring/task */ > - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; > - } else { > - adev->pm.dpm.vce_active = false; > + scoped_guard(mutex, &adev->pm.mutex) { > + if (enable) { > + adev->pm.dpm.vce_active = true; > + /* XXX select vce level based on ring/task */ > + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; > + } else { > + adev->pm.dpm.vce_active = false; > + } > } > - mutex_unlock(&adev->pm.mutex); > > amdgpu_dpm_compute_clocks(adev); > return; > @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) > int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int r = 0; > + int ret = 0; Ths init is not needed.> > if (!pp_funcs || !pp_funcs->load_firmware || > (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) > return 0; > > - mutex_lock(&adev->pm.mutex); > - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); > - if (r) { > + guard(mutex)(&adev->pm.mutex); > + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); > + if (ret) { > pr_err("smu firmware loading failed\n"); > - goto out; > + return ret; > } > > if (smu_version) > *smu_version = adev->pm.fw_version; > > -out: > - mutex_unlock(&adev->pm.mutex); > - return r; > + return ret; > } > > int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) > { > - int ret = 0; > + if (!is_support_sw_smu(adev)) > + return 0; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, > enable); > - mutex_unlock(&adev->pm.mutex); > - } > - > - return ret; > } > > int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_pages_num(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_pages_num(smu, size); > } > > int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_hbm_bad_channel_flag(smu, size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_hbm_bad_channel_flag(smu, size); > } > > int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_send_rma_reason(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_send_rma_reason(smu); > } > > /** > @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) > bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool ret; > > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma_is_supported(smu); > } > > int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_sdma(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_sdma(smu, inst_mask); > } > > int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn(smu, inst_mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn(smu, inst_mask); > } > > bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - bool ret; > > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_reset_vcn_is_supported(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_reset_vcn_is_supported(smu); > } > > int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, > @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, > uint32_t *min, > uint32_t *max) > { > - int ret = 0; > - > if (type != PP_SCLK) > return -EINVAL; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, > SMU_SCLK, > min, > max); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, > @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, > int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_write_watermarks_table(smu); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_write_watermarks_table(smu); > } > > int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, > @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, > uint64_t event_arg) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_wait_for_event(smu, event, event_arg); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_wait_for_event(smu, event, event_arg); > } > > int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_set_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_set_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_residency_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_residency_gfxoff(smu, value); > } > > int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_entrycount_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_entrycount_gfxoff(smu, value); > } > > int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_status_gfxoff(smu, value); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_status_gfxoff(smu, value); > } > > uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) > void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, > enum gfx_change_state state) > { > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (adev->powerplay.pp_funcs && > adev->powerplay.pp_funcs->gfx_state_change_set) > ((adev)->powerplay.pp_funcs->gfx_state_change_set( > (adev)->powerplay.pp_handle, state)); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, > void *umc_ecc) > { > struct smu_context *smu = adev->powerplay.pp_handle; > - int ret = 0; > > if (!is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = smu_get_ecc_info(smu, umc_ecc); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return smu_get_ecc_info(smu, umc_ecc); > } > > struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, > @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, > if (!pp_funcs->get_vce_clock_state) > return NULL; > > - mutex_lock(&adev->pm.mutex); > - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, > idx); > - mutex_unlock(&adev->pm.mutex); > - > - return vstate; > } > > void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > @@ -1015,28 +845,24 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > > if (!pp_funcs->get_current_power_state) { > *state = adev->pm.dpm.user_state; > - goto out; > + return; > } > > *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); > if (*state < POWER_STATE_TYPE_DEFAULT || > *state > POWER_STATE_TYPE_INTERNAL_3DPERF) > *state = adev->pm.dpm.user_state; > - > -out: > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, > enum amd_pm_state_type state) > { > - mutex_lock(&adev->pm.mutex); > - adev->pm.dpm.user_state = state; > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) > + adev->pm.dpm.user_state = state; > > if (is_support_sw_smu(adev)) > return; > @@ -1055,12 +881,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device > if (!pp_funcs) > return AMD_DPM_FORCED_LEVEL_AUTO; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > if (pp_funcs->get_performance_level) > level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); > else > level = adev->pm.dpm.forced_level; > - mutex_unlock(&adev->pm.mutex); > > return level; > } > @@ -1151,17 +976,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, > struct pp_states_info *states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pp_num_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, > states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, > @@ -1169,24 +990,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, > enum amd_pm_state_type *user_state) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->dispatch_tasks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, > task_id, > user_state); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!table) > return -EINVAL; > @@ -1194,12 +1010,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) > if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, > @@ -1208,19 +1021,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fine_grain_clk_vol) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, > @@ -1229,19 +1038,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, > uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->odn_edit_dpm_table) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, > type, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, > @@ -1250,52 +1055,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, > int *offset) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->emit_clock_levels) > return -ENOENT; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, > type, > buf, > offset); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, > uint64_t ppfeature_masks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, > ppfeature_masks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_ppfeature_status) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, > @@ -1303,33 +1096,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, > uint32_t mask) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->force_clock_level) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, > type, > mask); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_sclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1339,10 +1124,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_sclk_od) > - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_sclk_od) Since this is redone anyway, better to reverse the order - check if pointer exists and then take a mutex guard before setting. That is more aligned to scoped_guard. > + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1357,16 +1142,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) > int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_mclk_od) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); > } > > int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > @@ -1376,10 +1157,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) > if (is_support_sw_smu(adev)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - if (pp_funcs->set_mclk_od) > - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > - mutex_unlock(&adev->pm.mutex); > + scoped_guard(mutex, &adev->pm.mutex) { > + if (pp_funcs->set_mclk_od) Same as earlier, consider reversing the order. > + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); > + } > > if (amdgpu_dpm_dispatch_task(adev, > AMD_PP_TASK_READJUST_POWER_STATE, > @@ -1395,170 +1176,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, > char *buf) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_profile_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, > buf); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, > long *input, uint32_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_profile_mode) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, > input, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_gpu_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_pm_metrics) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, > uint32_t *fan_mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, > fan_mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_pwm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t *speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, > uint32_t speed) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_speed_rpm) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, > speed); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, > uint32_t mode) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_fan_control_mode) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, > mode); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, > @@ -1567,19 +1308,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, > enum pp_power_type power_type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_power_limit) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, > limit, > pp_limit_level, > power_type); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, > @@ -1587,17 +1324,13 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, > uint32_t limit) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_power_limit) > return -EINVAL; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, > limit_type, limit); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) > @@ -1607,9 +1340,8 @@ int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) > if (!is_support_sw_smu(adev)) > return false; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > cclk_dpm_supported = is_support_cclk_dpm(adev); May return directly here. Thanks, Lijo > - mutex_unlock(&adev->pm.mutex); > > return (int)cclk_dpm_supported; > } > @@ -1622,10 +1354,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade > if (!pp_funcs->debugfs_print_current_performance_level) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, > m); > - mutex_unlock(&adev->pm.mutex); > > return 0; > } > @@ -1635,18 +1366,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, > size_t *size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_smu_prv_buf_details) > return -ENOSYS; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, > addr, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) > @@ -1698,7 +1425,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, > size_t size) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!buf || !size) > return -EINVAL; > @@ -1706,13 +1432,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, > if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, > buf, > size); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) > @@ -1737,17 +1460,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, > const struct amd_pp_display_configuration *input) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_configuration_change) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, > input); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, > @@ -1755,35 +1474,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, > struct amd_pp_clocks *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, > struct amd_pp_simple_clock_info *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_display_mode_validation_clocks) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > @@ -1791,18 +1502,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, > struct pp_clock_levels_with_latency *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_latency) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > @@ -1810,69 +1517,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, > struct pp_clock_levels_with_voltage *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_clock_by_type_with_voltage) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, > type, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, > void *clock_ranges) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_watermarks_for_clocks_ranges) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, > clock_ranges); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, > struct pp_display_clock_request *clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_clock_voltage_request) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, > struct amd_pp_clock_info *clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_current_clocks) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, > clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) > @@ -1882,43 +1573,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) > if (!pp_funcs->notify_smu_enable_pwe) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, > uint32_t count) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_active_display_count) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, > count); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, > uint32_t clock) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->set_min_deep_sleep_dcefclk) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > @@ -1929,10 +1611,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, > if (!pp_funcs->set_hard_min_dcefclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > @@ -1943,44 +1624,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, > if (!pp_funcs->set_hard_min_fclk_by_freq) > return; > > - mutex_lock(&adev->pm.mutex); > + guard(mutex)(&adev->pm.mutex); > pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, > clock); > - mutex_unlock(&adev->pm.mutex); > } > > int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, > bool disable_memory_clock_switch) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->display_disable_memory_clock_switch) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, > disable_memory_clock_switch); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, > struct pp_smu_nv_clock_table *max_clocks) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_max_sustainable_clocks_by_dc) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, > max_clocks); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > @@ -1988,35 +1660,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, > unsigned int *num_states) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_uclk_dpm_states) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, > clock_values_in_khz, > num_states); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, > struct dpm_clocks *clock_table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_dpm_clock_table) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, > clock_table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > /** > @@ -2037,17 +1701,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, > enum smu_temp_metric_type type, void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret; > > if (!pp_funcs->get_temp_metrics || > !amdgpu_dpm_is_temp_metrics_supported(adev, type)) > return -EOPNOTSUPP; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); > } > > /** > @@ -2064,19 +1724,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, > enum smu_temp_metric_type type) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - bool support_temp_metrics = false; > > if (!pp_funcs->temp_metrics_is_supported) > - return support_temp_metrics; > + return false; > > - if (is_support_sw_smu(adev)) { > - mutex_lock(&adev->pm.mutex); > - support_temp_metrics = > - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); > - mutex_unlock(&adev->pm.mutex); > - } > + if (!is_support_sw_smu(adev)) > + return false; > > - return support_temp_metrics; > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); > } > > /** > @@ -2098,17 +1754,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, > void *table) > { > const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > - int ret = 0; > > if (!pp_funcs->get_xcp_metrics) > return 0; > > - mutex_lock(&adev->pm.mutex); > - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > + guard(mutex)(&adev->pm.mutex); > + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, > table); > - mutex_unlock(&adev->pm.mutex); > - > - return ret; > } > > const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v7] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-11 13:50 ` Lazar, Lijo @ 2026-05-12 23:04 ` Andre Jun Hirata 2026-05-13 5:38 ` [PATCH v8] " Andre Jun Hirata 0 siblings, 1 reply; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-12 23:04 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, kevinyang.wang, lijo.lazar, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard v4: - fix build errors introduced in v3 - fix incorrect is_support_sw_smu() condition - remove accidental "return =" typos v5: fix incorrect diff in v4 v6: fix missing semicolon in smu_mode1_reset_is_support() return statement v7: address Lijo Lazar's review comments: - use early return when (!adev->pm.dpm_enabled) in acpi_event_handler - drop unnecessary ret init in amdgpu_pm_load_smu_firmware - check function pointer before taking mutex in set_sclk_od and set_mclk_od - return directly in amdgpu_dpm_is_cclk_dpm_supported drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 896 +++++++++------------------- 1 file changed, 272 insertions(+), 624 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..b14bd39cb 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; + int ret; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu); } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,85 +397,72 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { - if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); - if (power_supply_is_system_supplied() > 0) - adev->pm.ac_power = true; - else - adev->pm.ac_power = false; + if (!adev->pm.dpm_enabled) + return; - if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->enable_bapm) - amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); + guard(mutex)(&adev->pm.mutex); + if (power_supply_is_system_supplied() > 0) + adev->pm.ac_power = true; + else + adev->pm.ac_power = false; - if (is_support_sw_smu(adev)) - smu_set_ac_dc(adev->powerplay.pp_handle); + if (adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->enable_bapm) + amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); - mutex_unlock(&adev->pm.mutex); - } + if (is_support_sw_smu(adev)) + smu_set_ac_dc(adev->powerplay.pp_handle); } int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,28 +807,23 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, @@ -1002,12 +835,9 @@ struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,28 +845,24 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); if (*state < POWER_STATE_TYPE_DEFAULT || *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; - -out: - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +881,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +976,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +990,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1010,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1021,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1038,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1055,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1096,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1124,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + if (pp_funcs->set_sclk_od) { + scoped_guard(mutex, &adev->pm.mutex) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1142,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1157,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + if (pp_funcs->set_mclk_od) { + scoped_guard(mutex, &adev->pm.mutex) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1176,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1308,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,31 +1324,22 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) { - bool cclk_dpm_supported = false; - if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); - - return (int)cclk_dpm_supported; + guard(mutex)(&adev->pm.mutex); + return is_support_cclk_dpm(adev); } int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, @@ -1622,10 +1350,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1362,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1421,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1428,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1456,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1470,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1498,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1513,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1569,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1607,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1620,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1656,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1697,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1720,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1750,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v8] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-12 23:04 ` [PATCH v7] " Andre Jun Hirata @ 2026-05-13 5:38 ` Andre Jun Hirata 0 siblings, 0 replies; 16+ messages in thread From: Andre Jun Hirata @ 2026-05-13 5:38 UTC (permalink / raw) To: kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, kevinyang.wang, lijo.lazar, Andre Jun Hirata Use guard() and scoped_guard() for handling mutex lock instead of manually locking and unlocking the mutex. This prevents forgotten locks due to early exits and removes the need of gotos. Signed-off-by: Andre Jun Hirata <andrejhirata@usp.br> Co-developed-by: Gabriel Dimant <gabriel.dimant@usp.br> Signed-off-by: Gabriel Dimant <gabriel.dimant@usp.br> Co-developed-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Signed-off-by: Guilherme Gabriel <guilhermesangabriel@usp.br> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> --- v2: incorporate Christian König's suggestions: - use return f() directly instead of ret = f(); return ret; - use early return pattern before guard() where applicable v3: fix style nits pointed by Christian König: - drop superfluous ret initialization in set_gfx_power_up_by_imu - drop unnecessary braces around single-line scoped_guard v4: - fix build errors introduced in v3 - fix incorrect is_support_sw_smu() condition - remove accidental "return =" typos v5: fix incorrect diff in v4 v6: fix missing semicolon in smu_mode1_reset_is_support() return statement v7: address Lijo Lazar's review comments: - use early return when (!adev->pm.dpm_enabled) in acpi_event_handler - drop unnecessary ret init in amdgpu_pm_load_smu_firmware - check function pointer before taking mutex in set_sclk_od and set_mclk_od - return directly in amdgpu_dpm_is_cclk_dpm_supported v8: remove unused variable 'vstate' in amdgpu_dpm_get_vce_clock_state drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 897 +++++++++------------------- 1 file changed, 272 insertions(+), 625 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index feadf604b..bfa94bdaa 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -30,6 +30,7 @@ #include "amd_pcie.h" #include "amdgpu_display.h" #include "hwmgr.h" +#include <linux/cleanup.h> #include <linux/power_supply.h> #include "amdgpu_smu.h" @@ -41,33 +42,25 @@ int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk((adev)->powerplay.pp_handle, low); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, @@ -80,13 +73,12 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON; bool is_vcn = block_type == AMD_IP_BLOCK_TYPE_VCN; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state && (!is_vcn || adev->vcn.num_vcn_inst == 1)) { dev_dbg(adev->dev, "IP block%d already in the target %s state!", block_type, gate ? "gate" : "ungate"); - goto out_unlock; + return ret; } switch (block_type) { @@ -115,20 +107,16 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, if (!ret) atomic_set(&adev->pm.pwr_state[block_type], pwr_state); -out_unlock: - mutex_unlock(&adev->pm.mutex); - return ret; } int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; + int ret; - mutex_lock(&adev->pm.mutex); - ret = smu_set_gfx_power_up_by_imu(smu); - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + ret = smu_set_gfx_power_up_by_imu(smu); msleep(10); @@ -139,44 +127,31 @@ int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 1); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 1); } int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); - + guard(mutex)(&adev->pm.mutex); /* exit BACO state */ - ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - - mutex_unlock(&adev->pm.mutex); - - return ret; + return pp_funcs->set_asic_baco_state(pp_handle, 0); } int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; if (mp1_state == PP_MP1_STATE_FLR) { @@ -184,23 +159,19 @@ int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) adev->pm.dpm_enabled = false; } else if (pp_funcs && pp_funcs->set_mp1_state) { - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->set_mp1_state( + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_mp1_state( adev->powerplay.pp_handle, mp1_state); - - mutex_unlock(&adev->pm.mutex); } - return ret; + return 0; } int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret; if (!pp_funcs || !pp_funcs->get_asic_baco_capability) return 0; @@ -216,49 +187,32 @@ int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) if (adev->in_s3) return 0; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->get_asic_baco_capability(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_asic_baco_capability(pp_handle); } int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_mode_2) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_mode_2(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_mode_2(pp_handle); } int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - int ret = 0; if (!pp_funcs || !pp_funcs->asic_reset_enable_gfx_features) return -ENOENT; - mutex_lock(&adev->pm.mutex); - - ret = pp_funcs->asic_reset_enable_gfx_features(pp_handle); - - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->asic_reset_enable_gfx_features(pp_handle); } int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) @@ -270,75 +224,60 @@ int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) if (!pp_funcs || !pp_funcs->set_asic_baco_state) return -ENOENT; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); /* enter BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 1); if (ret) - goto out; + return ret; /* exit BACO state */ ret = pp_funcs->set_asic_baco_state(pp_handle, 0); - -out: - mutex_unlock(&adev->pm.mutex); return ret; } bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_mode1_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_mode1_reset = smu_mode1_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_mode1_reset; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset_is_support(smu); } int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_mode1_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_mode1_reset(smu); } bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool support_link_reset = false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_link_reset = smu_link_reset_is_support(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_link_reset; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset_is_support(smu); } int amdgpu_dpm_link_reset(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_link_reset(smu); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_link_reset(smu); } int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, @@ -346,100 +285,82 @@ int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, bool en) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->switch_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->switch_power_profile( - adev->powerplay.pp_handle, type, en); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->switch_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->switch_power_profile( + adev->powerplay.pp_handle, type, en); } int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev, bool pause) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (amdgpu_sriov_vf(adev)) return 0; - if (pp_funcs && pp_funcs->pause_power_profile) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->pause_power_profile( - adev->powerplay.pp_handle, pause); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->pause_power_profile) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->pause_power_profile( + adev->powerplay.pp_handle, pause); } int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, uint32_t pstate) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_xgmi_pstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, - pstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_xgmi_pstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, + pstate); } int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, uint32_t cstate) { - int ret = 0; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; void *pp_handle = adev->powerplay.pp_handle; - if (pp_funcs && pp_funcs->set_df_cstate) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_df_cstate(pp_handle, cstate); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_df_cstate) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_df_cstate(pp_handle, cstate); } ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_get_pm_policy_info(smu, p_type, buf); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_pm_policy_info(smu, p_type, buf); } int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = -EOPNOTSUPP; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_set_pm_policy(smu, policy_type, policy_level); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_pm_policy(smu, policy_type, policy_level); } int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) @@ -447,15 +368,12 @@ int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->enable_mgpu_fan_boost) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->enable_mgpu_fan_boost(pp_handle); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->enable_mgpu_fan_boost) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->enable_mgpu_fan_boost(pp_handle); } int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, @@ -464,16 +382,13 @@ int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - if (pp_funcs && pp_funcs->set_clockgating_by_smu) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_clockgating_by_smu(pp_handle, - msg_id); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_clockgating_by_smu) + return 0; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_clockgating_by_smu(pp_handle, + msg_id); } int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, @@ -482,85 +397,72 @@ int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, void *pp_handle = adev->powerplay.pp_handle; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->smu_i2c_bus_access) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->smu_i2c_bus_access(pp_handle, - acquire); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->smu_i2c_bus_access(pp_handle, + acquire); } void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) { - if (adev->pm.dpm_enabled) { - mutex_lock(&adev->pm.mutex); - if (power_supply_is_system_supplied() > 0) - adev->pm.ac_power = true; - else - adev->pm.ac_power = false; + if (!adev->pm.dpm_enabled) + return; - if (adev->powerplay.pp_funcs && - adev->powerplay.pp_funcs->enable_bapm) - amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); + guard(mutex)(&adev->pm.mutex); + if (power_supply_is_system_supplied() > 0) + adev->pm.ac_power = true; + else + adev->pm.ac_power = false; - if (is_support_sw_smu(adev)) - smu_set_ac_dc(adev->powerplay.pp_handle); + if (adev->powerplay.pp_funcs && + adev->powerplay.pp_funcs->enable_bapm) + amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); - mutex_unlock(&adev->pm.mutex); - } + if (is_support_sw_smu(adev)) + smu_set_ac_dc(adev->powerplay.pp_handle); } int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, void *data, uint32_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EINVAL; if (!data || !size) return -EINVAL; - if (pp_funcs && pp_funcs->read_sensor) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, + if (!pp_funcs || !pp_funcs->read_sensor) + return -EINVAL; + + guard(mutex)(&adev->pm.mutex); + return pp_funcs->read_sensor(adev->powerplay.pp_handle, sensor, data, size); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->get_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->get_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); } int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = -EOPNOTSUPP; - if (pp_funcs && pp_funcs->set_apu_thermal_limit) { - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); - mutex_unlock(&adev->pm.mutex); - } + if (!pp_funcs || !pp_funcs->set_apu_thermal_limit) + return -EOPNOTSUPP; - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); } void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) @@ -583,9 +485,8 @@ void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) amdgpu_fence_wait_empty(ring); } - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) @@ -593,14 +494,14 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.uvd_active = true; - adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; - } else { - adev->pm.dpm.uvd_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.uvd_active = true; + adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; + } else { + adev->pm.dpm.uvd_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -627,15 +528,15 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) int ret = 0; if (adev->family == AMDGPU_FAMILY_SI) { - mutex_lock(&adev->pm.mutex); - if (enable) { - adev->pm.dpm.vce_active = true; - /* XXX select vce level based on ring/task */ - adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; - } else { - adev->pm.dpm.vce_active = false; + scoped_guard(mutex, &adev->pm.mutex) { + if (enable) { + adev->pm.dpm.vce_active = true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + } else { + adev->pm.dpm.vce_active = false; + } } - mutex_unlock(&adev->pm.mutex); amdgpu_dpm_compute_clocks(adev); return; @@ -670,84 +571,66 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int r = 0; + int ret; if (!pp_funcs || !pp_funcs->load_firmware || (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) return 0; - mutex_lock(&adev->pm.mutex); - r = pp_funcs->load_firmware(adev->powerplay.pp_handle); - if (r) { + guard(mutex)(&adev->pm.mutex); + ret = pp_funcs->load_firmware(adev->powerplay.pp_handle); + if (ret) { pr_err("smu firmware loading failed\n"); - goto out; + return ret; } if (smu_version) *smu_version = adev->pm.fw_version; -out: - mutex_unlock(&adev->pm.mutex); - return r; + return ret; } int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) { - int ret = 0; + if (!is_support_sw_smu(adev)) + return 0; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_handle_passthrough_sbr(adev->powerplay.pp_handle, enable); - mutex_unlock(&adev->pm.mutex); - } - - return ret; } int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_pages_num(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_pages_num(smu, size); } int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_hbm_bad_channel_flag(smu, size); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_hbm_bad_channel_flag(smu, size); } int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_send_rma_reason(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_send_rma_reason(smu); } /** @@ -761,61 +644,45 @@ int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma_is_supported(smu); } int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_sdma(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_sdma(smu, inst_mask); } int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn(smu, inst_mask); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn(smu, inst_mask); } bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - bool ret; if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - ret = smu_reset_vcn_is_supported(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_reset_vcn_is_supported(smu); } int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, @@ -823,22 +690,17 @@ int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, uint32_t *min, uint32_t *max) { - int ret = 0; - if (type != PP_SCLK) return -EINVAL; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return smu_get_dpm_freq_range(adev->powerplay.pp_handle, SMU_SCLK, min, max); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, @@ -862,16 +724,12 @@ int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return 0; - mutex_lock(&adev->pm.mutex); - ret = smu_write_watermarks_table(smu); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_write_watermarks_table(smu); } int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, @@ -879,76 +737,56 @@ int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, uint64_t event_arg) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_wait_for_event(smu, event, event_arg); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_wait_for_event(smu, event, event_arg); } int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_set_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_set_residency_gfxoff(smu, value); } int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_residency_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_residency_gfxoff(smu, value); } int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_entrycount_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_entrycount_gfxoff(smu, value); } int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_status_gfxoff(smu, value); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_status_gfxoff(smu, value); } uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) @@ -969,45 +807,36 @@ uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, enum gfx_change_state state) { - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->gfx_state_change_set) ((adev)->powerplay.pp_funcs->gfx_state_change_set( (adev)->powerplay.pp_handle, state)); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, void *umc_ecc) { struct smu_context *smu = adev->powerplay.pp_handle; - int ret = 0; if (!is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = smu_get_ecc_info(smu, umc_ecc); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return smu_get_ecc_info(smu, umc_ecc); } struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, uint32_t idx) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - struct amd_vce_state *vstate = NULL; if (!pp_funcs->get_vce_clock_state) return NULL; - mutex_lock(&adev->pm.mutex); - vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, idx); - mutex_unlock(&adev->pm.mutex); - - return vstate; } void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, @@ -1015,28 +844,24 @@ void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (!pp_funcs->get_current_power_state) { *state = adev->pm.dpm.user_state; - goto out; + return; } *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); if (*state < POWER_STATE_TYPE_DEFAULT || *state > POWER_STATE_TYPE_INTERNAL_3DPERF) *state = adev->pm.dpm.user_state; - -out: - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, enum amd_pm_state_type state) { - mutex_lock(&adev->pm.mutex); - adev->pm.dpm.user_state = state; - mutex_unlock(&adev->pm.mutex); + scoped_guard(mutex, &adev->pm.mutex) + adev->pm.dpm.user_state = state; if (is_support_sw_smu(adev)) return; @@ -1055,12 +880,11 @@ enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device if (!pp_funcs) return AMD_DPM_FORCED_LEVEL_AUTO; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); if (pp_funcs->get_performance_level) level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); else level = adev->pm.dpm.forced_level; - mutex_unlock(&adev->pm.mutex); return level; } @@ -1151,17 +975,13 @@ int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, struct pp_states_info *states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pp_num_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, @@ -1169,24 +989,19 @@ int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, enum amd_pm_state_type *user_state) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->dispatch_tasks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, task_id, user_state); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!table) return -EINVAL; @@ -1194,12 +1009,9 @@ int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) if (amdgpu_sriov_vf(adev) || !pp_funcs->get_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pp_table(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, @@ -1208,19 +1020,15 @@ int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fine_grain_clk_vol) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, @@ -1229,19 +1037,15 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->odn_edit_dpm_table) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, type, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, @@ -1250,52 +1054,40 @@ int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, int *offset) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->emit_clock_levels) return -ENOENT; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, type, buf, offset); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, uint64_t ppfeature_masks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, ppfeature_masks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_ppfeature_status) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, @@ -1303,33 +1095,25 @@ int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, uint32_t mask) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->force_clock_level) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->force_clock_level(adev->powerplay.pp_handle, type, mask); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_sclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_sclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1339,10 +1123,10 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_sclk_od) - pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + if (pp_funcs->set_sclk_od) { + scoped_guard(mutex, &adev->pm.mutex) + pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1357,16 +1141,12 @@ int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_mclk_od) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_mclk_od(adev->powerplay.pp_handle); } int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) @@ -1376,10 +1156,10 @@ int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) if (is_support_sw_smu(adev)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - if (pp_funcs->set_mclk_od) - pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); - mutex_unlock(&adev->pm.mutex); + if (pp_funcs->set_mclk_od) { + scoped_guard(mutex, &adev->pm.mutex) + pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); + } if (amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, @@ -1395,170 +1175,130 @@ int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, char *buf) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_profile_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, buf); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, long *input, uint32_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_profile_mode) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, input, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_gpu_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_pm_metrics) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, uint32_t *fan_mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, fan_mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_pwm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, uint32_t *speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, uint32_t speed) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_speed_rpm) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, speed); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, uint32_t mode) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_fan_control_mode) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, mode); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, @@ -1567,19 +1307,15 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, enum pp_power_type power_type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_power_limit) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_power_limit(adev->powerplay.pp_handle, limit, pp_limit_level, power_type); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, @@ -1587,31 +1323,22 @@ int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, uint32_t limit) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_power_limit) return -EINVAL; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_power_limit(adev->powerplay.pp_handle, limit_type, limit); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) { - bool cclk_dpm_supported = false; - if (!is_support_sw_smu(adev)) return false; - mutex_lock(&adev->pm.mutex); - cclk_dpm_supported = is_support_cclk_dpm(adev); - mutex_unlock(&adev->pm.mutex); - - return (int)cclk_dpm_supported; + guard(mutex)(&adev->pm.mutex); + return is_support_cclk_dpm(adev); } int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, @@ -1622,10 +1349,9 @@ int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *ade if (!pp_funcs->debugfs_print_current_performance_level) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, m); - mutex_unlock(&adev->pm.mutex); return 0; } @@ -1635,18 +1361,14 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, size_t *size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_smu_prv_buf_details) return -ENOSYS; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, addr, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) @@ -1698,7 +1420,6 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, size_t size) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!buf || !size) return -EINVAL; @@ -1706,13 +1427,10 @@ int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev) || !pp_funcs->set_pp_table || adev->scpm_enabled) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_pp_table(adev->powerplay.pp_handle, buf, size); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) @@ -1737,17 +1455,13 @@ int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, const struct amd_pp_display_configuration *input) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_configuration_change) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_configuration_change(adev->powerplay.pp_handle, input); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, @@ -1755,35 +1469,27 @@ int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, struct amd_pp_clocks *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, struct amd_pp_simple_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_display_mode_validation_clocks) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, @@ -1791,18 +1497,14 @@ int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, struct pp_clock_levels_with_latency *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_latency) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, @@ -1810,69 +1512,53 @@ int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, struct pp_clock_levels_with_voltage *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_clock_by_type_with_voltage) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, type, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, void *clock_ranges) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_watermarks_for_clocks_ranges) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, clock_ranges); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, struct pp_display_clock_request *clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_clock_voltage_request) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, struct amd_pp_clock_info *clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_current_clocks) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_current_clocks(adev->powerplay.pp_handle, clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) @@ -1882,43 +1568,34 @@ void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) if (!pp_funcs->notify_smu_enable_pwe) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, uint32_t count) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_active_display_count) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_active_display_count(adev->powerplay.pp_handle, count); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, uint32_t clock) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->set_min_deep_sleep_dcefclk) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); - - return ret; } void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, @@ -1929,10 +1606,9 @@ void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_dcefclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, @@ -1943,44 +1619,35 @@ void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, if (!pp_funcs->set_hard_min_fclk_by_freq) return; - mutex_lock(&adev->pm.mutex); + guard(mutex)(&adev->pm.mutex); pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, clock); - mutex_unlock(&adev->pm.mutex); } int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, bool disable_memory_clock_switch) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->display_disable_memory_clock_switch) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, disable_memory_clock_switch); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, struct pp_smu_nv_clock_table *max_clocks) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_max_sustainable_clocks_by_dc) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, max_clocks); - mutex_unlock(&adev->pm.mutex); - - return ret; } enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, @@ -1988,35 +1655,27 @@ enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, unsigned int *num_states) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_uclk_dpm_states) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, clock_values_in_khz, num_states); - mutex_unlock(&adev->pm.mutex); - - return ret; } int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, struct dpm_clocks *clock_table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_dpm_clock_table) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, clock_table); - mutex_unlock(&adev->pm.mutex); - - return ret; } /** @@ -2037,17 +1696,13 @@ ssize_t amdgpu_dpm_get_temp_metrics(struct amdgpu_device *adev, enum smu_temp_metric_type type, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret; if (!pp_funcs->get_temp_metrics || !amdgpu_dpm_is_temp_metrics_supported(adev, type)) return -EOPNOTSUPP; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); - mutex_unlock(&adev->pm.mutex); - - return ret; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_temp_metrics(adev->powerplay.pp_handle, type, table); } /** @@ -2064,19 +1719,15 @@ bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, enum smu_temp_metric_type type) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - bool support_temp_metrics = false; if (!pp_funcs->temp_metrics_is_supported) - return support_temp_metrics; + return false; - if (is_support_sw_smu(adev)) { - mutex_lock(&adev->pm.mutex); - support_temp_metrics = - pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); - mutex_unlock(&adev->pm.mutex); - } + if (!is_support_sw_smu(adev)) + return false; - return support_temp_metrics; + guard(mutex)(&adev->pm.mutex); + return pp_funcs->temp_metrics_is_supported(adev->powerplay.pp_handle, type); } /** @@ -2098,17 +1749,13 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, void *table) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; if (!pp_funcs->get_xcp_metrics) return 0; - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, + guard(mutex)(&adev->pm.mutex); + return pp_funcs->get_xcp_metrics(adev->powerplay.pp_handle, xcp_id, table); - mutex_unlock(&adev->pm.mutex); - - return ret; } const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) -- 2.43.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata 2026-05-11 4:58 ` Wang, Yang(Kevin) @ 2026-05-13 4:39 ` kernel test robot 2026-05-13 6:12 ` kernel test robot 2 siblings, 0 replies; 16+ messages in thread From: kernel test robot @ 2026-05-13 4:39 UTC (permalink / raw) To: Andre Jun Hirata, kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: oe-kbuild-all, amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Hi Andre, kernel test robot noticed the following build errors: [auto build test ERROR on drm-misc/drm-misc-next] [also build test ERROR on linus/master v7.1-rc3 next-20260508] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Andre-Jun-Hirata/drm-amd-pm-Use-guard-mutex-instead-of-manual-lock-unlock/20260513-040937 base: https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-next patch link: https://lore.kernel.org/r/20260508230312.6108-1-andrejhirata%40usp.br patch subject: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock config: x86_64-rhel-9.4-ltp (https://download.01.org/0day-ci/archive/20260513/202605130638.LqIgORiV-lkp@intel.com/config) compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260513/202605130638.LqIgORiV-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202605130638.LqIgORiV-lkp@intel.com/ All error/warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_is_mode1_reset_supported': >> drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:247:47: error: expected ';' before '}' token 247 | return smu_mode1_reset_is_support(smu) | ^ | ; 248 | } | ~ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_vce_clock_state': >> drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:833:31: warning: unused variable 'vstate' [-Wunused-variable] 833 | struct amd_vce_state *vstate = NULL; | ^~~~~~ vim +247 drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c 238 239 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 240 { 241 struct smu_context *smu = adev->powerplay.pp_handle; 242 243 if (!is_support_sw_smu(adev)) 244 return false; 245 246 guard(mutex)(&adev->pm.mutex); > 247 return smu_mode1_reset_is_support(smu) 248 } 249 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata 2026-05-11 4:58 ` Wang, Yang(Kevin) 2026-05-13 4:39 ` [PATCH v5] " kernel test robot @ 2026-05-13 6:12 ` kernel test robot 2 siblings, 0 replies; 16+ messages in thread From: kernel test robot @ 2026-05-13 6:12 UTC (permalink / raw) To: Andre Jun Hirata, kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: llvm, oe-kbuild-all, amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Hi Andre, kernel test robot noticed the following build errors: [auto build test ERROR on drm-misc/drm-misc-next] [also build test ERROR on next-20260508] [cannot apply to linus/master v6.16-rc1] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Andre-Jun-Hirata/drm-amd-pm-Use-guard-mutex-instead-of-manual-lock-unlock/20260513-040937 base: https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-next patch link: https://lore.kernel.org/r/20260508230312.6108-1-andrejhirata%40usp.br patch subject: [PATCH v5] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock config: x86_64-rhel-9.4-rust (https://download.01.org/0day-ci/archive/20260513/202605130808.IJrao3wX-lkp@intel.com/config) compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261) rustc: rustc 1.88.0 (6b00bc388 2025-06-23) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260513/202605130808.IJrao3wX-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202605130808.IJrao3wX-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:247:40: error: expected ';' after return statement 247 | return smu_mode1_reset_is_support(smu) | ^ | ; drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:833:24: warning: unused variable 'vstate' [-Wunused-variable] 833 | struct amd_vce_state *vstate = NULL; | ^~~~~~ 1 warning and 1 error generated. vim +247 drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c 238 239 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) 240 { 241 struct smu_context *smu = adev->powerplay.pp_handle; 242 243 if (!is_support_sw_smu(adev)) 244 return false; 245 246 guard(mutex)(&adev->pm.mutex); > 247 return smu_mode1_reset_is_support(smu) 248 } 249 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock 2026-05-08 17:23 ` [PATCH v4] " Andre Jun Hirata 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata @ 2026-05-13 5:11 ` kernel test robot 1 sibling, 0 replies; 16+ messages in thread From: kernel test robot @ 2026-05-13 5:11 UTC (permalink / raw) To: Andre Jun Hirata, kenneth.feng, alexander.deucher, christian.koenig, airlied, simona Cc: oe-kbuild-all, amd-gfx, dri-devel, gabriel.dimant, guilhermesangabriel, Andre Jun Hirata Hi Andre, kernel test robot noticed the following build errors: [auto build test ERROR on drm-misc/drm-misc-next] [also build test ERROR on linus/master v7.1-rc3 next-20260508] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Andre-Jun-Hirata/drm-amd-pm-Use-guard-mutex-instead-of-manual-lock-unlock/20260513-062000 base: https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-next patch link: https://lore.kernel.org/r/20260508172345.6680-1-andrejhirata%40usp.br patch subject: [PATCH v4] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock config: x86_64-randconfig-072-20260513 (https://download.01.org/0day-ci/archive/20260513/202605131349.EV901kW3-lkp@intel.com/config) compiler: gcc-12 (Debian 12.4.0-5) 12.4.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260513/202605131349.EV901kW3-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202605131349.EV901kW3-lkp@intel.com/ All error/warnings (new ones prefixed by >>): drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_is_mode1_reset_supported': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:247:47: error: expected ';' before '}' token 247 | return smu_mode1_reset_is_support(smu) | ^ | ; 248 | } | ~ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_smu_i2c_bus_access': >> drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:405:16: error: expected expression before '=' token 405 | return = pp_funcs->smu_i2c_bus_access(pp_handle, | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_vce_clock_state': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:833:31: warning: unused variable 'vstate' [-Wunused-variable] 833 | struct amd_vce_state *vstate = NULL; | ^~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_pp_table': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1016:16: error: expected expression before '=' token 1016 | return = pp_funcs->get_pp_table(adev->powerplay.pp_handle, | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_set_fine_grain_clk_vol': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1031:16: error: expected expression before '=' token 1031 | return = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_display_mode_validation_clks': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1498:16: error: expected expression before '=' token 1498 | return = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_smu_i2c_bus_access': >> drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:407:1: warning: control reaches end of non-void function [-Wreturn-type] 407 | } | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_pp_table': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1018:1: warning: control reaches end of non-void function [-Wreturn-type] 1018 | } | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_set_fine_grain_clk_vol': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1035:1: warning: control reaches end of non-void function [-Wreturn-type] 1035 | } | ^ drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c: In function 'amdgpu_dpm_get_display_mode_validation_clks': drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c:1500:1: warning: control reaches end of non-void function [-Wreturn-type] 1500 | } | ^ vim +405 drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.c 393 394 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 395 bool acquire) 396 { 397 void *pp_handle = adev->powerplay.pp_handle; 398 const struct amd_pm_funcs *pp_funcs = 399 adev->powerplay.pp_funcs; 400 401 if (!pp_funcs || !pp_funcs->smu_i2c_bus_access) 402 return -EOPNOTSUPP; 403 404 guard(mutex)(&adev->pm.mutex); > 405 return = pp_funcs->smu_i2c_bus_access(pp_handle, 406 acquire); > 407 } 408 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-05-13 7:56 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-08 2:47 [PATCH RESEND] drm/amd/pm: Use guard(mutex) instead of manual lock+unlock Andre Hirata 2026-05-08 8:43 ` Christian König 2026-05-08 10:36 ` Andre Jun Hirata 2026-05-08 11:12 ` [PATCH v2] " Andre Jun Hirata 2026-05-08 12:44 ` Christian König 2026-05-08 14:21 ` [PATCH v3] " Andre Jun Hirata 2026-05-08 17:23 ` [PATCH v4] " Andre Jun Hirata 2026-05-08 23:03 ` [PATCH v5] " Andre Jun Hirata 2026-05-11 4:58 ` Wang, Yang(Kevin) 2026-05-11 12:42 ` [PATCH v6] " Andre Jun Hirata 2026-05-11 13:50 ` Lazar, Lijo 2026-05-12 23:04 ` [PATCH v7] " Andre Jun Hirata 2026-05-13 5:38 ` [PATCH v8] " Andre Jun Hirata 2026-05-13 4:39 ` [PATCH v5] " kernel test robot 2026-05-13 6:12 ` kernel test robot 2026-05-13 5:11 ` [PATCH v4] " kernel test robot
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