* [PATCH 01/13] drm/amdgpu: Add common NBIO doorbell entry helpers
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 02/13] drm/amdgpu: Add nbio v6_3_2 doorbell layout Hawking Zhang
` (11 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Add doorbell layout and field descriptions together
with common helpers to build and program nbio
doorbell entries.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 142 +++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 79 +++++++++++++
2 files changed, 221 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
index e4c8e98725f0..70b63fd3656f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
@@ -21,6 +21,7 @@
#include "amdgpu.h"
#include "amdgpu_ras.h"
+#include "soc15_common.h"
int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev)
{
@@ -94,3 +95,144 @@ void amdgpu_nbio_program_aspm(struct amdgpu_device *adev)
if (adev->nbio.funcs->program_aspm)
adev->nbio.funcs->program_aspm(adev);
}
+
+static int amdgpu_nbio_set_doorbell_field(u32 *reg, u32 mask, u32 value)
+{
+ u32 shift;
+
+ if (!mask)
+ return value ? -EOPNOTSUPP : 0;
+
+ shift = __ffs(mask);
+ if (value > (mask >> shift))
+ return -ERANGE;
+
+ *reg |= (value << shift) & mask;
+ return 0;
+}
+
+int amdgpu_nbio_build_doorbell_entry(
+ struct amdgpu_device *adev,
+ const struct amdgpu_nbio_doorbell_fields *fields,
+ u32 *ctrl, u32 *ctrl1)
+{
+ const struct amdgpu_nbio_doorbell_layout *layout;
+ int r;
+
+ if (!fields || !ctrl)
+ return -EINVAL;
+
+ layout = adev->nbio.doorbell_layout;
+ if (!layout)
+ return -EINVAL;
+
+ *ctrl = 0;
+ if (ctrl1)
+ *ctrl1 = 0;
+
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.enable,
+ fields->enable);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.awid,
+ fields->awid);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.fence_enable,
+ fields->fence_enable);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.range_offset,
+ fields->range_offset);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.range_size,
+ fields->range_size);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.disable_64bit,
+ fields->disable_64bit);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl,
+ layout->ctrl.deduct_range_offset,
+ fields->deduct_range_offset);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.drop,
+ fields->drop);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl, layout->ctrl.awaddr_31_28,
+ fields->awaddr_31_28);
+ if (r)
+ return r;
+
+ if (!ctrl1)
+ return 0;
+ if (!layout->has_ctrl1)
+ return -EOPNOTSUPP;
+
+ r = amdgpu_nbio_set_doorbell_field(ctrl1,
+ layout->ctrl1.target_port_type,
+ fields->target_port_type);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl1,
+ layout->ctrl1.target_die_id,
+ fields->target_die_id);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl1,
+ layout->ctrl1.target_port_id,
+ fields->target_port_id);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl1,
+ layout->ctrl1.override_poison_data,
+ fields->override_poison_data);
+ if (r)
+ return r;
+ r = amdgpu_nbio_set_doorbell_field(ctrl1,
+ layout->ctrl1.disable_4k_page_decode,
+ fields->disable_4k_page_decode);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+void amdgpu_nbio_program_doorbell_entry(
+ struct amdgpu_device *adev,
+ enum amdgpu_nbio_doorbell_client client,
+ u32 instance, const u32 *ctrl, const u32 *ctrl1)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ struct amdgpu_nbio_doorbell_entry *entry;
+
+ if (WARN_ON_ONCE(client >= AMDGPU_NBIO_DOORBELL_CLIENT_COUNT))
+ return;
+
+ entries = &adev->nbio.doorbell_entries[client];
+ if (WARN_ON_ONCE(instance >= entries->num_entries))
+ return;
+
+ entry = &entries->entry[instance];
+ if (WARN_ON_ONCE(!entry->ctrl_reg))
+ return;
+
+ /* A NULL CTRL disables and clears the entry. */
+ if (!ctrl) {
+ WREG32_SOC15_IP(NBIO, entry->ctrl_reg, 0);
+ if (entry->ctrl1_reg)
+ WREG32_SOC15_IP(NBIO, entry->ctrl1_reg, 0);
+ return;
+ }
+
+ if (WARN_ON_ONCE(ctrl1 && !entry->ctrl1_reg))
+ return;
+
+ WREG32_SOC15_IP(NBIO, entry->ctrl_reg, *ctrl);
+ if (ctrl1)
+ WREG32_SOC15_IP(NBIO, entry->ctrl1_reg, *ctrl1);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index a61f3a6e8ec7..2ac392934169 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -55,6 +55,73 @@ struct amdgpu_nbio_ras {
int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
};
+enum amdgpu_nbio_doorbell_client {
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE,
+ AMDGPU_NBIO_DOORBELL_CLIENT_COUNT,
+};
+
+struct amdgpu_nbio_doorbell_ctrl_layout {
+ u32 enable;
+ u32 awid;
+ u32 fence_enable;
+ u32 range_offset;
+ u32 range_size;
+ u32 disable_64bit;
+ u32 deduct_range_offset;
+ u32 drop;
+ u32 awaddr_31_28;
+};
+
+struct amdgpu_nbio_doorbell_ctrl1_layout {
+ u32 target_port_type;
+ u32 target_die_id;
+ u32 target_port_id;
+ u32 override_poison_data;
+ u32 disable_4k_page_decode;
+};
+
+struct amdgpu_nbio_doorbell_layout {
+ struct amdgpu_nbio_doorbell_ctrl_layout ctrl;
+ struct amdgpu_nbio_doorbell_ctrl1_layout ctrl1;
+ bool has_ctrl1;
+};
+
+struct amdgpu_nbio_doorbell_fields {
+ bool enable;
+ u32 awid;
+ u32 range_offset;
+ u32 range_size;
+ u32 awaddr_31_28;
+ u32 target_port_type;
+ u32 target_die_id;
+ u32 target_port_id;
+ bool fence_enable;
+ bool disable_64bit;
+ bool deduct_range_offset;
+ bool drop;
+ bool override_poison_data;
+ bool disable_4k_page_decode;
+};
+
+#define AMDGPU_NBIO_MAX_DOORBELL_INSTANCES 16
+
+struct amdgpu_nbio_doorbell_entry {
+ u32 port;
+ u32 ctrl_reg;
+ u32 ctrl1_reg;
+};
+
+struct amdgpu_nbio_doorbell_entries {
+ u32 num_entries;
+ struct amdgpu_nbio_doorbell_entry
+ entry[AMDGPU_NBIO_MAX_DOORBELL_INSTANCES];
+};
+
struct amdgpu_nbio_funcs {
const struct nbio_hdp_flush_reg *hdp_flush_reg;
u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
@@ -113,6 +180,9 @@ struct amdgpu_nbio {
struct ras_common_if *ras_if;
const struct amdgpu_nbio_funcs *funcs;
struct amdgpu_nbio_ras *ras;
+ const struct amdgpu_nbio_doorbell_layout *doorbell_layout;
+ struct amdgpu_nbio_doorbell_entries
+ doorbell_entries[AMDGPU_NBIO_DOORBELL_CLIENT_COUNT];
};
int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev);
@@ -123,4 +193,13 @@ bool amdgpu_nbio_is_replay_cnt_supported(struct amdgpu_device *adev);
void amdgpu_nbio_program_aspm(struct amdgpu_device *adev);
+int amdgpu_nbio_build_doorbell_entry(
+ struct amdgpu_device *adev,
+ const struct amdgpu_nbio_doorbell_fields *fields,
+ u32 *ctrl, u32 *ctrl1);
+void amdgpu_nbio_program_doorbell_entry(
+ struct amdgpu_device *adev,
+ enum amdgpu_nbio_doorbell_client client,
+ u32 instance, const u32 *ctrl, const u32 *ctrl1);
+
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 02/13] drm/amdgpu: Add nbio v6_3_2 doorbell layout
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
2026-09-05 10:05 ` [PATCH 01/13] drm/amdgpu: Add common NBIO doorbell entry helpers Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 03/13] drm/amdgpu: Use common doorbell helpers in nbio v6_3_2 Hawking Zhang
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Describe nbio v6_3_2 doorbell_entry_ctrl and
doorbell_entry_ctrl1 field layout from IP register
header and initialize gc, ih, vcn, and sdma
port and register assignments.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c | 100 +++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
index a40a13ca1011..4f5a5f310905 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
@@ -26,6 +26,57 @@
#include "amdgpu.h"
#include "nbio_v6_3_2.h"
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v6_3_2_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+ .ctrl1 = {
+ .target_port_type = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_PORT_TYPE),
+ .target_die_id = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_DIEID),
+ .target_port_id = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_TARGET_PORT_ID),
+ .override_poison_data = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA),
+ .disable_4k_page_decode = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1,
+ S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE),
+ },
+ .has_ctrl1 = true,
+};
+
static u32 nbio_v6_3_2_get_pcie_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
@@ -71,8 +122,57 @@ static void nbio_v6_3_2_mc_access_enable(struct amdgpu_device *adev,
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
}
+static void nbio_v6_3_2_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base, ctrl1_base;
+ u32 i;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v6_3_2_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+ ctrl1_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+ entries->entry[0].ctrl1_reg = ctrl1_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+ entries->entry[0].ctrl1_reg = ctrl1_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 4;
+ for (i = 0; i < entries->num_entries; i++) {
+ entries->entry[i].port = i + 2;
+ entries->entry[i].ctrl_reg = ctrl_base + (i + 2) * 2;
+ entries->entry[i].ctrl1_reg = ctrl1_base + (i + 2) * 2;
+ }
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 6;
+ entries->entry[0].ctrl_reg = ctrl_base + 6 * 2;
+ entries->entry[0].ctrl1_reg = ctrl1_base + 6 * 2;
+}
+
static void nbio_v6_3_2_init_registers(struct amdgpu_device *adev)
{
+ nbio_v6_3_2_init_doorbell_entry_registers(adev);
+
WREG32_SOC15(NBIO, 0, regXCD_DOORBELL_FENCE_1,
(0xff & ~(adev->gfx.xcc_mask)) <<
XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 03/13] drm/amdgpu: Use common doorbell helpers in nbio v6_3_2
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
2026-09-05 10:05 ` [PATCH 01/13] drm/amdgpu: Add common NBIO doorbell entry helpers Hawking Zhang
2026-09-05 10:05 ` [PATCH 02/13] drm/amdgpu: Add nbio v6_3_2 doorbell layout Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 04/13] drm/amdgpu: Add nbio v4_3 doorbell layout Hawking Zhang
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Build doorbell_entry_ctrl and doorbell_entry_ctrl1
values through the common field helper while retaining
the existing nbio callback interface and preserving
nbio v6_3_2 client routing values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c | 224 +++++++++--------------
1 file changed, 85 insertions(+), 139 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
index 4f5a5f310905..75477951353d 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
@@ -261,52 +261,44 @@ static void nbio_v6_3_2_ih_control(struct amdgpu_device *adev)
static void nbio_v6_3_2_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range = 0;
- u32 ih_doorbell_range1 = 0;
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 8);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
- S2A_DOORBELL_PORT1_TARGET_PORT_TYPE,
- 0x3);
- ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
- S2A_DOORBELL_PORT1_TARGET_DIEID,
- 0x0);
- ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
- S2A_DOORBELL_PORT1_TARGET_PORT_ID,
- 0x0);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ .target_port_type = 0x3,
+ };
+ u32 ctrl, ctrl1;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, ih_doorbell_range1);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, &ctrl1)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, &ctrl1);
}
static void nbio_v6_3_2_gc_doorbell_init(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1, 0x3);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0x3,
+ .awaddr_31_28 = 0x3,
+ .target_port_type = 0x3,
+ };
+ u32 ctrl, ctrl1;
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, &ctrl1)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, &ctrl1);
}
static void nbio_v6_3_2_sdma_doorbell_range(struct amdgpu_device *adev,
@@ -314,114 +306,68 @@ static void nbio_v6_3_2_sdma_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- if (instance == 0) {
- u32 doorbell_range = 0;
- u32 doorbell_range1 = 0;
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
- S2A_DOORBELL_PORT6_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
- S2A_DOORBELL_PORT6_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
- S2A_DOORBELL_PORT6_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
- S2A_DOORBELL_PORT6_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
- S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE,
- 0xe);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
- S2A_DOORBELL_PORT6_TARGET_PORT_TYPE,
- 0x3);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
- S2A_DOORBELL_PORT6_TARGET_DIEID,
- 0x0);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
- S2A_DOORBELL_PORT6_TARGET_PORT_ID,
- 0x0);
- }
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, doorbell_range1);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0xe,
+ .target_port_type = 0x3,
+ };
+ u32 ctrl, ctrl1;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, &ctrl1)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, &ctrl1);
}
static void nbio_v6_3_2_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{
- u32 doorbell_range = 0;
- u32 doorbell_range1 = 0;
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 11);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
- S2A_DOORBELL_PORT2_TARGET_PORT_TYPE,
- 0x3);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
- S2A_DOORBELL_PORT2_TARGET_DIEID,
- (instance / adev->vcn.num_inst_per_aid) ? 0x3 : 0x0);
- doorbell_range1 = REG_SET_FIELD(doorbell_range1,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
- S2A_DOORBELL_PORT2_TARGET_PORT_ID,
- 0x0);
+ static const u8 vcn_component[] = { 0x4, 0x7, 0x4, 0x7 };
+ static const u8 vcn_target_die[] = { 0, 0, 3, 3 };
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 11,
+ .target_port_type = 0x3,
+ };
+ u32 ctrl, ctrl1;
+
+ if (WARN_ON_ONCE((unsigned int)instance >=
+ ARRAY_SIZE(vcn_component)))
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance,
+ NULL, NULL);
+ return;
}
- switch (instance) {
- case 0:
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, doorbell_range1);
- break;
- case 1:
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1, doorbell_range1);
- break;
- case 2:
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1, doorbell_range1);
- break;
- case 3:
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1, doorbell_range1);
- break;
- default:
- dev_err(adev->dev,
- "amdgpu: invalid vcn instance set when program doorbell range\n");
- break;
- }
+ fields.awid = vcn_component[instance];
+ fields.awaddr_31_28 = fields.awid;
+ fields.target_die_id = vcn_target_die[instance];
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, &ctrl1)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance, &ctrl, &ctrl1);
}
static int nbio_v6_3_2_get_compute_partition_mode(struct amdgpu_device *adev)
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 04/13] drm/amdgpu: Add nbio v4_3 doorbell layout
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (2 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 03/13] drm/amdgpu: Use common doorbell helpers in nbio v6_3_2 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 05/13] drm/amdgpu: Use common doorbell helpers in nbio v4_3 Hawking Zhang
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Describe the nbio v4_3 doorbell entry ctrl
field layout and initialize the CP, IH, SDMA,
RLC, and VCN port and register assignments.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 77 ++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index a66e3073aed8..6d12324ce663 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -28,6 +28,81 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v4_3_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbio_v4_3_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v4_3_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 1;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 2;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 3;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 2;
+ entries->entry[0].port = 4;
+ entries->entry[0].ctrl_reg = ctrl_base + 4;
+ entries->entry[1].port = 5;
+ entries->entry[1].ctrl_reg = ctrl_base + 5;
+}
+
static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -337,6 +412,8 @@ const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = {
static void nbio_v4_3_init_registers(struct amdgpu_device *adev)
{
+ nbio_v4_3_init_doorbell_entry_registers(adev);
+
if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(4, 3, 0)) {
uint32_t data;
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 05/13] drm/amdgpu: Use common doorbell helpers in nbio v4_3
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (3 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 04/13] drm/amdgpu: Add nbio v4_3 doorbell layout Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 06/13] drm/amdgpu: Support doorbell range programming through smn Hawking Zhang
` (7 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Build and program the CP, RLC, IH, SDMA, and VCN
doorbell entries through the common NBIO helpers
while retaining the existing callback interface
and v4_3 client routing values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 188 ++++++++++++-------------
1 file changed, 88 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index 6d12324ce663..be98fee6fbf2 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -140,87 +140,86 @@ static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instan
bool use_doorbell, int doorbell_index,
int doorbell_size)
{
- if (instance == 0) {
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- 0x3);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index, int instance)
{
- u32 doorbell_range;
+ static const u8 vcn_component[] = { 0x4, 0x7 };
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl;
- if (instance)
- doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL);
- else
- doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWID,
- instance ? 0x7 : 0x4);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 8);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
- instance ? 0x7 : 0x4);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 0);
-
- if (instance)
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
+ if (WARN_ON_ONCE((unsigned int)instance >=
+ ARRAY_SIZE(vcn_component)))
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance,
+ NULL, NULL);
+ return;
+ }
+
+ fields.awid = vcn_component[instance];
+ fields.awaddr_31_28 = fields.awid;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, instance, &ctrl, NULL);
}
static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ fields.awid = 0x3;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL);
+
+ fields.awid = 0x6;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL);
}
static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -256,36 +255,25 @@ static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL);
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 8);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- } else
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
+ }
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
static void nbio_v4_3_ih_control(struct amdgpu_device *adev)
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 06/13] drm/amdgpu: Support doorbell range programming through smn
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (4 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 05/13] drm/amdgpu: Use common doorbell helpers in nbio v4_3 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 07/13] drm/amdgpu: Use common doorbell helpers in nbio v7_9 Hawking Zhang
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Some NBIO generations expose doorbell control register
instances through global SMN addresses. Extend the common
doorbell entry description and programming helper to
select this access path
The IP-specific mapping records the target register
instance while callers remain responsible for invoking
their doorbell callback for each required instance.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c | 24 ++++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 9 +++++++++
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
index 70b63fd3656f..55049a8635bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
@@ -221,18 +221,26 @@ void amdgpu_nbio_program_doorbell_entry(
if (WARN_ON_ONCE(!entry->ctrl_reg))
return;
- /* A NULL CTRL disables and clears the entry. */
- if (!ctrl) {
- WREG32_SOC15_IP(NBIO, entry->ctrl_reg, 0);
- if (entry->ctrl1_reg)
- WREG32_SOC15_IP(NBIO, entry->ctrl1_reg, 0);
+ if (entry->use_ext) {
+ /* CTRL1 programming is not needed when use_ext is set. */
+ if (WARN_ON_ONCE(entry->ctrl1_reg || ctrl1))
+ return;
+
+ WREG32_PCIE_EXT(
+ (adev->reg_offset[NBIO_HWIP][entry->reg_inst]
+ [entry->ctrl_reg_base_idx] + entry->ctrl_reg) * 4 +
+ amdgpu_reg_get_smn_base64(
+ adev, NBIO_HWIP, entry->reg_inst),
+ ctrl ? *ctrl : 0);
return;
}
if (WARN_ON_ONCE(ctrl1 && !entry->ctrl1_reg))
return;
- WREG32_SOC15_IP(NBIO, entry->ctrl_reg, *ctrl);
- if (ctrl1)
- WREG32_SOC15_IP(NBIO, entry->ctrl1_reg, *ctrl1);
+ /* A NULL CTRL disables and clears the entry. */
+ WREG32_SOC15_IP(NBIO, entry->ctrl_reg, ctrl ? *ctrl : 0);
+ if (entry->ctrl1_reg && (!ctrl || ctrl1))
+ WREG32_SOC15_IP(NBIO, entry->ctrl1_reg,
+ ctrl ? *ctrl1 : 0);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 2ac392934169..18418a331517 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -114,6 +114,15 @@ struct amdgpu_nbio_doorbell_entry {
u32 port;
u32 ctrl_reg;
u32 ctrl1_reg;
+ /*
+ * Some NBIO generations expose each register instance through a global
+ * SMN address. The caller invokes the doorbell callback for each required
+ * instance across the die; reg_inst identifies the instance represented
+ * by this entry. Extended entries only support a CTRL register.
+ */
+ bool use_ext;
+ u32 reg_inst;
+ u32 ctrl_reg_base_idx;
};
struct amdgpu_nbio_doorbell_entries {
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 07/13] drm/amdgpu: Use common doorbell helpers in nbio v7_9
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (5 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 06/13] drm/amdgpu: Support doorbell range programming through smn Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 08/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_5 Hawking Zhang
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Describe the nbio v7_9 S2A doorbell layout and
client-to-port mappings, then build and program
the IH, SDMA, and VCN entries through the common
NBIO helpers.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 377 +++++++++++++------------
1 file changed, 204 insertions(+), 173 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
index bdfd2917e3ca..6fe57075a954 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
@@ -31,6 +31,131 @@
#define NPS_MODE_MASK 0x000000FFL
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v7_9_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbio_v7_9_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ static const u8 sdma_port[] = { 1, 2, 5, 6 };
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base, dev_inst, local_inst;
+ int i;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v7_9_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(NBIO, 0,
+ regS2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 3;
+
+ /*
+ * Unlike IH, SDMA and VCN use global SMN addresses. Their callers invoke
+ * the callbacks once per available instance to cover all AIDs across the
+ * die.
+ */
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = adev->sdma.num_instances;
+ if (WARN_ON_ONCE(entries->num_entries >
+ AMDGPU_NBIO_MAX_DOORBELL_INSTANCES) ||
+ WARN_ON_ONCE(entries->num_entries &&
+ !adev->sdma.num_inst_per_aid)) {
+ entries->num_entries = 0;
+ return;
+ }
+ for (i = 0; i < entries->num_entries; i++) {
+ dev_inst = GET_INST(SDMA0, i);
+ local_inst = dev_inst % adev->sdma.num_inst_per_aid;
+ if (WARN_ON_ONCE(local_inst >= ARRAY_SIZE(sdma_port))) {
+ entries->num_entries = 0;
+ return;
+ }
+ entries->entry[i].port = sdma_port[local_inst];
+ entries->entry[i].ctrl_reg =
+ regS2A_DOORBELL_ENTRY_0_CTRL + sdma_port[local_inst];
+ entries->entry[i].use_ext = true;
+ entries->entry[i].reg_inst = adev->sdma.instance[i].aid_id;
+ entries->entry[i].ctrl_reg_base_idx =
+ regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX;
+ }
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = fls(adev->aid_mask);
+ if (WARN_ON_ONCE(entries->num_entries >
+ AMDGPU_NBIO_MAX_DOORBELL_INSTANCES)) {
+ entries->num_entries = 0;
+ return;
+ }
+ for_each_inst(i, adev->aid_mask) {
+ entries->entry[i].port = 4;
+ entries->entry[i].ctrl_reg = regS2A_DOORBELL_ENTRY_4_CTRL;
+ entries->entry[i].use_ext = true;
+ entries->entry[i].reg_inst = i;
+ entries->entry[i].ctrl_reg_base_idx =
+ regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX;
+ }
+}
+
+static u32 nbio_v7_9_build_doorbell_range(u32 range_offset,
+ u32 range_size, u32 fence_enable)
+{
+ u32 doorbell_range = 0;
+
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ DOORBELL0_CTRL_ENTRY_0, BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
+ range_offset);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ DOORBELL0_CTRL_ENTRY_0, BIF_DOORBELL0_RANGE_SIZE_ENTRY,
+ range_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ DOORBELL0_CTRL_ENTRY_0, DOORBELL0_FENCE_ENABLE_ENTRY,
+ fence_enable);
+
+ return doorbell_range;
+}
+
+static void nbio_v7_9_program_doorbell_range(struct amdgpu_device *adev,
+ u32 entry, u32 doorbell_range)
+{
+ WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0,
+ entry, doorbell_range);
+}
+
static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -75,160 +200,80 @@ static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
bool use_doorbell, int doorbell_index, int doorbell_size)
{
- u32 doorbell_range = 0, doorbell_ctrl = 0;
- int aid_id, dev_inst;
+ static const u8 sdma_awid[] = { 0xe, 0x8, 0x9, 0xa };
+ static const u8 sdma_awaddr[] = { 0x1, 0x2, 0x8, 0x9 };
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_size = doorbell_size,
+ };
+ u32 doorbell_range, ctrl;
+ int aid_id, dev_inst, local_inst;
dev_inst = GET_INST(SDMA0, instance);
aid_id = adev->sdma.instance[instance].aid_id;
+ local_inst = dev_inst % adev->sdma.num_inst_per_aid;
- if (use_doorbell == false)
+ if (WARN_ON_ONCE((unsigned int)local_inst >= ARRAY_SIZE(sdma_awid)))
return;
- doorbell_range =
- REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
- doorbell_range =
- REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
- doorbell_ctrl =
- REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE, 1);
- doorbell_ctrl =
- REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
-
- switch (dev_inst % adev->sdma.num_inst_per_aid) {
- case 0:
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
- 4 * aid_id, doorbell_range);
-
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0xe);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x1);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
- aid_id, doorbell_ctrl);
- break;
- case 1:
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
- 4 * aid_id, doorbell_range);
-
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0x8);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x2);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
- aid_id, doorbell_ctrl);
- break;
- case 2:
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
- 4 * aid_id, doorbell_range);
-
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0x9);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x8);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
- aid_id, doorbell_ctrl);
- break;
- case 3:
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
- 4 * aid_id, doorbell_range);
-
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0xa);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x9);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
- aid_id, doorbell_ctrl);
- break;
- default:
- break;
+ if (!use_doorbell) {
+ nbio_v7_9_program_doorbell_range(adev,
+ 1 + local_inst + 4 * aid_id, 0);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ doorbell_range = nbio_v7_9_build_doorbell_range(
+ doorbell_index, doorbell_size, 0);
+ fields.awid = sdma_awid[local_inst];
+ fields.range_offset = fields.awid;
+ fields.awaddr_31_28 = sdma_awaddr[local_inst];
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ nbio_v7_9_program_doorbell_range(adev,
+ 1 + local_inst + 4 * aid_id, doorbell_range);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
int doorbell_index, int instance)
{
- u32 doorbell_range = 0, doorbell_ctrl = 0;
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0x4,
+ .range_offset = 0x4,
+ .awaddr_31_28 = 0x4,
+ };
+ u32 doorbell_range, ctrl;
u32 aid_id = instance;
u32 range_size;
- if (use_doorbell) {
- range_size = (amdgpu_ip_version(adev, GC_HWIP, 0) ==
+ if (!use_doorbell) {
+ nbio_v7_9_program_doorbell_range(adev, 17 + aid_id, 0);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, aid_id,
+ NULL, NULL);
+ return;
+ }
+
+ range_size = (amdgpu_ip_version(adev, GC_HWIP, 0) ==
IP_VERSION(9, 5, 0)) ?
0xb : 0x9;
- doorbell_range = REG_SET_FIELD(doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_SIZE_ENTRY,
- range_size);
- if (aid_id)
- doorbell_range = REG_SET_FIELD(doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- DOORBELL0_FENCE_ENABLE_ENTRY,
- 0x4);
-
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE, 1);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0x4);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE, range_size);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
-
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
- aid_id, doorbell_range);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
- aid_id, doorbell_ctrl);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
- doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
-
- WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
- aid_id, doorbell_range);
- WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
- aid_id, doorbell_ctrl);
- }
+ doorbell_range = nbio_v7_9_build_doorbell_range(
+ doorbell_index, range_size, aid_id ? 0x4 : 0);
+ fields.range_size = range_size;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ nbio_v7_9_program_doorbell_range(adev, 17 + aid_id, doorbell_range);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, aid_id, &ctrl, NULL);
}
static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -265,44 +310,28 @@ static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_SIZE_ENTRY,
- 0x8);
-
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE, 1);
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID, 0);
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
- } else {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- DOORBELL0_CTRL_ENTRY_0,
- BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
- ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
- S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_size = 0x8,
+ };
+ u32 doorbell_range, ctrl;
+
+ if (!use_doorbell) {
+ nbio_v7_9_program_doorbell_range(adev, 0, 0);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
- WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
+ doorbell_range = nbio_v7_9_build_doorbell_range(
+ doorbell_index, 0x8, 0);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ nbio_v7_9_program_doorbell_range(adev, 0, doorbell_range);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
@@ -435,6 +464,8 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
u32 inst_mask;
int i;
+ nbio_v7_9_init_doorbell_entry_registers(adev);
+
WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
0xff & ~(adev->gfx.xcc_mask));
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 08/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_5
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (6 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 07/13] drm/amdgpu: Use common doorbell helpers in nbio v7_9 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 09/13] drm/amdgpu: Add nbif v4_10_0 ip headers Hawking Zhang
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Describe the nbio v7_11_5 S2A doorbell layout and
existing client-to-port mappings, then build and
program the CP, RLC, IH, SDMA, and VPE entries
through the common NBIO helpers.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_11_5.c | 256 +++++++++++++---------
1 file changed, 158 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_5.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_5.c
index 0ea6e091a24c..47db8f87d72f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_5.c
@@ -28,6 +28,83 @@
#include "nbio/nbio_7_11_5_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v7_11_5_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbio_v7_11_5_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v7_11_5_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 2;
+ entries->entry[0].ctrl_reg = ctrl_base + 4;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 6;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE];
+ entries->num_entries = 1;
+ entries->entry[0].port = 5;
+ entries->entry[0].ctrl_reg = ctrl_base + 10;
+}
+
static void nbio_v7_11_5_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -72,42 +149,31 @@ static void nbio_v7_11_5_sdma_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- u32 doorbell_range;
-
- if (instance == 0) {
- doorbell_range = RREG32_SOC15(NBIO, 0,
- regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- 0x3);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 0);
- }
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbio_v7_11_5_vpe_doorbell_range(struct amdgpu_device *adev,
@@ -115,48 +181,54 @@ static void nbio_v7_11_5_vpe_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- u32 doorbell_range;
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xf,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0xf,
+ };
+ u32 ctrl;
if (instance)
return;
- doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWID,
- 0xf);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE,
- 0xf);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- 0);
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance,
+ NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, &ctrl, NULL);
}
static void nbio_v7_11_5_gc_doorbell_init(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ fields.awid = 0x3;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL);
+
+ fields.awid = 0x6;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL);
}
static void nbio_v7_11_5_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -191,39 +263,25 @@ static void nbio_v7_11_5_enable_doorbell_selfring_aperture(struct amdgpu_device
static void nbio_v7_11_5_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range;
-
- ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 2);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- } else {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 0);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 2,
+ };
+ u32 ctrl;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
static void nbio_v7_11_5_ih_control(struct amdgpu_device *adev)
@@ -310,6 +368,8 @@ static void nbio_v7_11_5_init_registers(struct amdgpu_device *adev)
{
uint32_t data;
+ nbio_v7_11_5_init_doorbell_entry_registers(adev);
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 09/13] drm/amdgpu: Add nbif v4_10_0 ip headers
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (7 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 08/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_5 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 10/13] drm/amdgpu: Add nbio v7_11_4 support Hawking Zhang
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Add header files for nbif v4_10_0 register offsets
and shift masks
These register definitions are derived from nbif
v6_3_1 source file which uses the _nbif_4_10 suffix
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
.../asic_reg/nbif/nbif_4_10_0_offset.h | 103 ++++
.../asic_reg/nbif/nbif_4_10_0_sh_mask.h | 573 ++++++++++++++++++
2 files changed, 676 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_offset.h
new file mode 100644
index 000000000000..fe0e0d588c06
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_offset.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbif_4_10_0_OFFSET_HEADER
+#define _nbif_4_10_0_OFFSET_HEADER
+
+#define regBIF_BX_PF0_RSMU_INDEX 0x0000
+#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1
+#define regBIF_BX_PF0_RSMU_DATA 0x0001
+#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1
+#define regBIF_BX0_PCIE_INDEX 0x000c
+#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0
+#define regBIF_BX0_PCIE_DATA 0x000d
+#define regBIF_BX0_PCIE_DATA_BASE_IDX 0
+#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0006
+#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0007
+#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2
+#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0009
+#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0021
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0054
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE 0x00c3
+#define regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
+#define regBIF_BX0_INTERRUPT_CNTL 0x00f1
+#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2
+#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2
+#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2
+#define regBIF_BX0_BIF_FB_EN 0x0100
+#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL 0x4f0aeb
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1 0x4f0aec
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL 0x4f0aed
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1 0x4f0aee
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL 0x4f0aef
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1 0x4f0af0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL 0x4f0af1
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1 0x4f0af2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL 0x4f0af3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1 0x4f0af4
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL 0x4f0af5
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1 0x4f0af6
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX 3
+#define regRCC_DEV0_EPF2_STRAP2 0xd102
+#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 5
+#define regREGS_ROM_OFFSET_CTRL 0xcc23
+#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 5
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE 0x2ffc0de3
+#define regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_BASE_IDX 5
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_sh_mask.h
new file mode 100644
index 000000000000..d8164039a4d3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_4_10_0_sh_mask.h
@@ -0,0 +1,573 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbif_4_10_0_SH_MASK_HEADER
+#define _nbif_4_10_0_SH_MASK_HEADER
+
+//BIF_BX_PF0_RSMU_INDEX
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_DATA
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA
+#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_USB_PD_FUNC_DIS_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//BIF_BX0_INTERRUPT_CNTL
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX0_INTERRUPT_CNTL2
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L
+//BIF_BX0_BIF_FB_EN
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT 0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT 0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT 0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK 0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK 0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK 0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK 0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK 0x00000080L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F2__SHIFT 0x4
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F2_MASK 0x00000010L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L
+//REGS_ROM_OFFSET_CTRL
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 10/13] drm/amdgpu: Add nbio v7_11_4 support
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (8 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 09/13] drm/amdgpu: Add nbif v4_10_0 ip headers Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 11/13] drm/amdgpu: Drop nbio v7_11_x support from nbif v6_3_1 Hawking Zhang
` (2 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
nbio v7_11_4 uses different bif doorbell port registers than
nbif v6_3_1, and different HDP flush and memory coherency
registers than nbio v7_11_5.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c | 391 ++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.h | 32 ++
3 files changed, 425 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 7b08814a24da..776b1f56ef61 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -91,7 +91,8 @@ amdgpu-y += \
nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \
sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \
nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \
- cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o nbio_v6_3_2.o nbio_v7_11_5.o
+ cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o nbio_v6_3_2.o nbio_v7_11_5.o \
+ nbio_v7_11_4.o
# add DF block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
new file mode 100644
index 000000000000..8bae45c9ddfd
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nbio_v7_11_4.h"
+
+#include "nbif/nbif_4_10_0_offset.h"
+#include "nbif/nbif_4_10_0_sh_mask.h"
+#include <uapi/linux/kfd_ioctl.h>
+
+static void nbio_v7_11_4_remap_hdp_registers(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
+ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
+}
+
+static u32 nbio_v7_11_4_get_rev_id(struct amdgpu_device *adev)
+{
+ u32 tmp;
+
+ tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+ tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
+ tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
+
+ return tmp;
+}
+
+static void nbio_v7_11_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
+{
+ if (enable)
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+ BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+ BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+ else
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+}
+
+static u32 nbio_v7_11_4_get_memsize(struct amdgpu_device *adev)
+{
+ return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
+}
+
+static void nbio_v7_11_4_sdma_doorbell_range(struct amdgpu_device *adev,
+ int instance, bool use_doorbell,
+ int doorbell_index,
+ int doorbell_size)
+{
+ if (instance == 0) {
+ u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_ENABLE,
+ 0x1);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_AWID,
+ 0xe);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_RANGE_OFFSET,
+ doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_RANGE_SIZE,
+ doorbell_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
+ 0x3);
+ } else {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ S2A_DOORBELL_PORT2_RANGE_SIZE,
+ 0);
+ }
+
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ doorbell_range);
+ }
+}
+
+static void nbio_v7_11_4_vcn_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index,
+ int instance)
+{
+ u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
+
+ if (instance)
+ return;
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_ENABLE,
+ 0x1);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_AWID,
+ 0x4);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_RANGE_OFFSET,
+ doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_RANGE_SIZE,
+ 8);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
+ 0x4);
+ } else {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ S2A_DOORBELL_PORT4_RANGE_SIZE,
+ 0);
+ }
+
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
+ doorbell_range);
+}
+
+static void nbio_v7_11_4_vpe_doorbell_range(struct amdgpu_device *adev,
+ int instance, bool use_doorbell,
+ int doorbell_index,
+ int doorbell_size)
+{
+ if (instance)
+ return;
+
+ u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
+
+ if (use_doorbell) {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_ENABLE,
+ 0x1);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_AWID,
+ 0xf);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_RANGE_OFFSET,
+ doorbell_index);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_RANGE_SIZE,
+ doorbell_size);
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE,
+ 0xf);
+ } else {
+ doorbell_range = REG_SET_FIELD(doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
+ S2A_DOORBELL_PORT5_RANGE_SIZE,
+ 0);
+ }
+
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+}
+
+static void nbio_v7_11_4_gc_doorbell_init(struct amdgpu_device *adev)
+{
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+}
+
+static void nbio_v7_11_4_enable_doorbell_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+ WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
+ BIF_DOORBELL_APER_EN, enable ? 1 : 0);
+}
+
+static void
+nbio_v7_11_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+ bool enable)
+{
+ u32 tmp = 0;
+
+ if (enable) {
+ tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_EN, 1) |
+ REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+ REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+ DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+ lower_32_bits(adev->doorbell.base));
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+ upper_32_bits(adev->doorbell.base));
+ }
+
+ WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
+}
+
+static void nbio_v7_11_4_ih_doorbell_range(struct amdgpu_device *adev,
+ bool use_doorbell, int doorbell_index)
+{
+ u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
+
+ if (use_doorbell) {
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_ENABLE,
+ 0x1);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_AWID,
+ 0x0);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_RANGE_OFFSET,
+ doorbell_index);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_RANGE_SIZE,
+ 2);
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
+ 0x0);
+ } else {
+ ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+ GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ S2A_DOORBELL_PORT1_RANGE_SIZE,
+ 0);
+ }
+
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ ih_doorbell_range);
+}
+
+static void nbio_v7_11_4_ih_control(struct amdgpu_device *adev)
+{
+ u32 interrupt_cntl;
+
+ /* setup interrupt control */
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+
+ interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
+ /*
+ * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+ * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+ */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+ IH_DUMMY_RD_OVERRIDE, 0);
+
+ /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
+ interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+ IH_REQ_NONSNOOP_EN, 0);
+
+ WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
+}
+
+static void
+nbio_v7_11_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
+{
+}
+
+static void
+nbio_v7_11_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
+{
+}
+
+static void
+nbio_v7_11_4_get_clockgating_state(struct amdgpu_device *adev,
+ u64 *flags)
+{
+}
+
+static u32 nbio_v7_11_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
+}
+
+static u32 nbio_v7_11_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
+}
+
+static u32 nbio_v7_11_4_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX);
+}
+
+static u32 nbio_v7_11_4_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA);
+}
+
+const struct nbio_hdp_flush_reg nbio_v7_11_4_hdp_flush_reg = {
+ .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
+ .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
+ .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
+ .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
+ .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
+ .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
+ .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
+ .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
+ .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
+ .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
+ .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
+ .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
+};
+
+static void nbio_v7_11_4_init_registers(struct amdgpu_device *adev)
+{
+ uint32_t data;
+
+ data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
+ data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
+ WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
+}
+
+static u32 nbio_v7_11_4_get_rom_offset(struct amdgpu_device *adev)
+{
+ u32 data, rom_offset;
+
+ data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL);
+ rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET);
+
+ return rom_offset;
+}
+
+#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
+
+static void nbio_v7_11_4_set_reg_remap(struct amdgpu_device *adev)
+{
+ if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
+ adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
+ adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
+ } else {
+ adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
+ regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
+ adev->rmmio_remap.bus_addr = 0;
+ }
+}
+
+const struct amdgpu_nbio_funcs nbio_v7_11_4_funcs = {
+ .get_hdp_flush_req_offset = nbio_v7_11_4_get_hdp_flush_req_offset,
+ .get_hdp_flush_done_offset = nbio_v7_11_4_get_hdp_flush_done_offset,
+ .get_pcie_index_offset = nbio_v7_11_4_get_pcie_index_offset,
+ .get_pcie_data_offset = nbio_v7_11_4_get_pcie_data_offset,
+ .get_rev_id = nbio_v7_11_4_get_rev_id,
+ .mc_access_enable = nbio_v7_11_4_mc_access_enable,
+ .get_memsize = nbio_v7_11_4_get_memsize,
+ .sdma_doorbell_range = nbio_v7_11_4_sdma_doorbell_range,
+ .vcn_doorbell_range = nbio_v7_11_4_vcn_doorbell_range,
+ .vpe_doorbell_range = nbio_v7_11_4_vpe_doorbell_range,
+ .gc_doorbell_init = nbio_v7_11_4_gc_doorbell_init,
+ .enable_doorbell_aperture = nbio_v7_11_4_enable_doorbell_aperture,
+ .enable_doorbell_selfring_aperture = nbio_v7_11_4_enable_doorbell_selfring_aperture,
+ .ih_doorbell_range = nbio_v7_11_4_ih_doorbell_range,
+ .update_medium_grain_clock_gating = nbio_v7_11_4_update_medium_grain_clock_gating,
+ .update_medium_grain_light_sleep = nbio_v7_11_4_update_medium_grain_light_sleep,
+ .get_clockgating_state = nbio_v7_11_4_get_clockgating_state,
+ .ih_control = nbio_v7_11_4_ih_control,
+ .init_registers = nbio_v7_11_4_init_registers,
+ .remap_hdp_registers = nbio_v7_11_4_remap_hdp_registers,
+ .get_rom_offset = nbio_v7_11_4_get_rom_offset,
+ .set_reg_remap = nbio_v7_11_4_set_reg_remap,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.h b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.h
new file mode 100644
index 000000000000..2757fb8ccfa9
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2026 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __NBIO_V7_11_4_H__
+#define __NBIO_V7_11_4_H__
+
+#include "soc15_common.h"
+
+extern const struct nbio_hdp_flush_reg nbio_v7_11_4_hdp_flush_reg;
+extern const struct amdgpu_nbio_funcs nbio_v7_11_4_funcs;
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 11/13] drm/amdgpu: Drop nbio v7_11_x support from nbif v6_3_1
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (9 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 10/13] drm/amdgpu: Add nbio v7_11_4 support Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 12/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_4 Hawking Zhang
2026-09-05 10:05 ` [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1 Hawking Zhang
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
nbio v7_11_4 and v7_11_5 now have dedicated implementations.
Select nbio v7_11_4 function and HDP flush tables during IP
discovery, and remove the version-specific register offsets
and doorbell handling from nbif v6_3_1.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 +-
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 89 +++----------------
2 files changed, 19 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 7710a8ed3d44..905332144836 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -45,6 +45,7 @@
#include "nbio_v7_4.h"
#include "nbio_v7_9.h"
#include "nbio_v7_11.h"
+#include "nbio_v7_11_4.h"
#include "nbio_v7_11_5.h"
#include "hdp_v4_0.h"
#include "vega10_ih.h"
@@ -3794,10 +3795,13 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
break;
case IP_VERSION(6, 3, 1):
- case IP_VERSION(7, 11, 4):
adev->nbio.funcs = &nbif_v6_3_1_funcs;
adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
break;
+ case IP_VERSION(7, 11, 4):
+ adev->nbio.funcs = &nbio_v7_11_4_funcs;
+ adev->nbio.hdp_flush_reg = &nbio_v7_11_4_hdp_flush_reg;
+ break;
case IP_VERSION(7, 11, 5):
adev->nbio.funcs = &nbio_v7_11_5_funcs;
adev->nbio.hdp_flush_reg = &nbio_v7_11_5_hdp_flush_reg;
diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index a74b17a47fd2..766cfbde55aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -30,33 +30,6 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6
-#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3
-#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021
-#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2
-
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -69,10 +42,7 @@ static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp;
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10);
- else
- tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+ tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -130,12 +100,8 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT2_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10,
- doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- doorbell_range);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+ doorbell_range);
}
}
@@ -146,8 +112,6 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
u32 doorbell_range;
if (instance) {
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return;
doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
} else {
doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
@@ -180,15 +144,10 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT4_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10,
- doorbell_range);
- } else {
- if (instance)
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
- }
+ if (instance)
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ else
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
}
static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
@@ -229,24 +188,14 @@ static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
0);
}
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4) ||
- amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range);
- } else {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- }
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
}
static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d);
- } else {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
- }
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
}
static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -311,12 +260,8 @@ static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
S2A_DOORBELL_PORT1_RANGE_SIZE,
0);
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10,
- ih_doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- ih_doorbell_range);
+ WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+ ih_doorbell_range);
}
static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)
@@ -371,18 +316,12 @@ static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX);
- else
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
}
static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
- if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4))
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA);
- else
- return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
+ return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
}
const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = {
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 12/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_4
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (10 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 11/13] drm/amdgpu: Drop nbio v7_11_x support from nbif v6_3_1 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-05 10:05 ` [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1 Hawking Zhang
12 siblings, 0 replies; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Build and program doorbell entry control values through the common
NBIO helpers while preserving the existing nbio v7_11_4 client
routing and field values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c | 307 +++++++++++++---------
1 file changed, 184 insertions(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
index 8bae45c9ddfd..9e60613addc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11_4.c
@@ -27,6 +27,89 @@
#include "nbif/nbif_4_10_0_sh_mask.h"
#include <uapi/linux/kfd_ioctl.h>
+static const struct amdgpu_nbio_doorbell_layout
+nbio_v7_11_4_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbio_v7_11_4_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbio_v7_11_4_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 2;
+ entries->entry[0].ctrl_reg = ctrl_base + 4;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 6;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 1;
+ entries->entry[0].port = 4;
+ entries->entry[0].ctrl_reg = ctrl_base + 8;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE];
+ entries->num_entries = 1;
+ entries->entry[0].port = 5;
+ entries->entry[0].ctrl_reg = ctrl_base + 10;
+}
+
static void nbio_v7_11_4_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -66,81 +149,62 @@ static void nbio_v7_11_4_sdma_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- if (instance == 0) {
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- 0x3);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 0);
- }
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbio_v7_11_4_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0x4,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ .awaddr_31_28 = 0x4,
+ };
+ u32 ctrl;
if (instance)
return;
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWID,
- 0x4);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 8);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
- 0x4);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 0);
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, 0,
+ NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, 0, &ctrl, NULL);
}
static void nbio_v7_11_4_vpe_doorbell_range(struct amdgpu_device *adev,
@@ -148,46 +212,54 @@ static void nbio_v7_11_4_vpe_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xf,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0xf,
+ };
+ u32 ctrl;
+
if (instance)
return;
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWID,
- 0xf);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE,
- 0xf);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- 0);
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance,
+ NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, &ctrl, NULL);
}
static void nbio_v7_11_4_gc_doorbell_init(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ fields.awid = 0x3;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL);
+
+ fields.awid = 0x6;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL);
}
static void nbio_v7_11_4_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -223,38 +295,25 @@ nbio_v7_11_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
static void nbio_v7_11_4_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 2);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- } else {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 0);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 2,
+ };
+ u32 ctrl;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- ih_doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
static void nbio_v7_11_4_ih_control(struct amdgpu_device *adev)
@@ -336,6 +395,8 @@ static void nbio_v7_11_4_init_registers(struct amdgpu_device *adev)
{
uint32_t data;
+ nbio_v7_11_4_init_doorbell_entry_registers(adev);
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1
2026-09-05 10:05 [PATCH 00/13] drm/amdgpu: Simplify nbio doorbell range programming Hawking Zhang
` (11 preceding siblings ...)
2026-09-05 10:05 ` [PATCH 12/13] drm/amdgpu: Use common doorbell helpers in nbio v7_11_4 Hawking Zhang
@ 2026-09-05 10:05 ` Hawking Zhang
2026-09-07 3:56 ` Gao, Likun
12 siblings, 1 reply; 15+ messages in thread
From: Hawking Zhang @ 2026-09-05 10:05 UTC (permalink / raw)
To: amd-gfx, Likun Gao; +Cc: Hawking Zhang
Build and program doorbell entry control values through the common
NBIO helpers while preserving the existing nbif v6_3_1 client
routing and field values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 317 +++++++++++++----------
1 file changed, 187 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index 766cfbde55aa..ce05f40f548a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -30,6 +30,91 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
+static const struct amdgpu_nbio_doorbell_layout
+nbif_v6_3_1_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbif_v6_3_1_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbif_v6_3_1_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 1;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 2;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 3;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 2;
+ entries->entry[0].port = 4;
+ entries->entry[0].ctrl_reg = ctrl_base + 4;
+ entries->entry[1].port = 5;
+ entries->entry[1].ctrl_reg = ctrl_base + 5;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE];
+ entries->num_entries = 1;
+ entries->entry[0].port = 5;
+ entries->entry[0].ctrl_reg = ctrl_base + 5;
+}
+
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev)
{
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -70,84 +155,59 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- if (instance == 0) {
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- 0x3);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{
- u32 doorbell_range;
-
- if (instance) {
- doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
- } else {
- doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl, entry = !!instance;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, entry,
+ NULL, NULL);
+ return;
}
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWID,
- instance ? 0x7 : 0x4);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 8);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
- instance ? 0x7 : 0x4);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 0);
+ fields.awid = instance ? 0x7 : 0x4;
+ fields.awaddr_31_28 = fields.awid;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
- if (instance)
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, entry, &ctrl, NULL);
}
static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
@@ -155,47 +215,54 @@ static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xf,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0xf,
+ };
+ u32 ctrl;
+
if (instance)
return;
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWID,
- 0xf);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE,
- 0xf);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- 0);
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance,
+ NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, &ctrl, NULL);
}
static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev)
{
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ fields.awid = 0x3;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL);
+
+ fields.awid = 0x6;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL);
}
static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev,
@@ -231,37 +298,25 @@ nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index)
{
- u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 8);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- } else
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- ih_doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
+ }
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev)
@@ -343,6 +398,8 @@ static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev)
{
uint32_t data;
+ nbif_v6_3_1_init_doorbell_entry_registers(adev);
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* RE: [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1
2026-09-05 10:05 ` [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1 Hawking Zhang
@ 2026-09-07 3:56 ` Gao, Likun
0 siblings, 0 replies; 15+ messages in thread
From: Gao, Likun @ 2026-09-07 3:56 UTC (permalink / raw)
To: Zhang, Hawking, amd-gfx@lists.freedesktop.org
AMD General
Series is Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Regards,
Likun
-----Original Message-----
From: Zhang, Hawking <Hawking.Zhang@amd.com>
Sent: Saturday, September 5, 2026 6:06 PM
To: amd-gfx@lists.freedesktop.org; Gao, Likun <Likun.Gao@amd.com>
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 13/13] drm/amdgpu: Use common doorbell helpers in nbif v6_3_1
Build and program doorbell entry control values through the common NBIO helpers while preserving the existing nbif v6_3_1 client routing and field values.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 317 +++++++++++++----------
1 file changed, 187 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index 766cfbde55aa..ce05f40f548a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -30,6 +30,91 @@
#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
#include <uapi/linux/kfd_ioctl.h>
+static const struct amdgpu_nbio_doorbell_layout
+nbif_v6_3_1_doorbell_layout = {
+ .ctrl = {
+ .enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_ENABLE),
+ .awid = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWID),
+ .fence_enable = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_FENCE_ENABLE),
+ .range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_OFFSET),
+ .range_size = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_RANGE_SIZE),
+ .disable_64bit = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS),
+ .deduct_range_offset = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET),
+ .drop = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_DROP_EN),
+ .awaddr_31_28 = REG_FIELD_MASK(
+ GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL,
+ S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE),
+ },
+};
+
+static void nbif_v6_3_1_init_doorbell_entry_registers(
+ struct amdgpu_device *adev)
+{
+ struct amdgpu_nbio_doorbell_entries *entries;
+ u32 ctrl_base;
+
+ memset(adev->nbio.doorbell_entries, 0,
+ sizeof(adev->nbio.doorbell_entries));
+ adev->nbio.doorbell_layout = &nbif_v6_3_1_doorbell_layout;
+
+ ctrl_base = SOC15_REG_OFFSET(
+ NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL);
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP];
+ entries->num_entries = 1;
+ entries->entry[0].port = 0;
+ entries->entry[0].ctrl_reg = ctrl_base;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH];
+ entries->num_entries = 1;
+ entries->entry[0].port = 1;
+ entries->entry[0].ctrl_reg = ctrl_base + 1;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA];
+ entries->num_entries = 1;
+ entries->entry[0].port = 2;
+ entries->entry[0].ctrl_reg = ctrl_base + 2;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC];
+ entries->num_entries = 1;
+ entries->entry[0].port = 3;
+ entries->entry[0].ctrl_reg = ctrl_base + 3;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN];
+ entries->num_entries = 2;
+ entries->entry[0].port = 4;
+ entries->entry[0].ctrl_reg = ctrl_base + 4;
+ entries->entry[1].port = 5;
+ entries->entry[1].ctrl_reg = ctrl_base + 5;
+
+ entries = &adev->nbio.doorbell_entries[
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE];
+ entries->num_entries = 1;
+ entries->entry[0].port = 5;
+ entries->entry[0].ctrl_reg = ctrl_base + 5; }
+
static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) {
WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -70,84 +155,59 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
- if (instance == 0) {
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWID,
- 0xe);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
- 0x3);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- S2A_DOORBELL_PORT2_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
- doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xe,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ if (instance != 0)
+ return;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance,
+ NULL, NULL);
+ return;
}
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_SDMA, instance, &ctrl, NULL);
}
static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{
- u32 doorbell_range;
-
- if (instance) {
- doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
- } else {
- doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl, entry = !!instance;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, entry,
+ NULL, NULL);
+ return;
}
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWID,
- instance ? 0x7 : 0x4);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 8);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE,
- instance ? 0x7 : 0x4);
- } else
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL,
- S2A_DOORBELL_PORT4_RANGE_SIZE,
- 0);
+ fields.awid = instance ? 0x7 : 0x4;
+ fields.awaddr_31_28 = fields.awid;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
- if (instance)
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
- else
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VCN, entry, &ctrl, NULL);
}
static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, @@ -155,47 +215,54 @@ static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev,
int doorbell_index,
int doorbell_size)
{
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awid = 0xf,
+ .range_offset = doorbell_index,
+ .range_size = doorbell_size,
+ .awaddr_31_28 = 0xf,
+ };
+ u32 ctrl;
+
if (instance)
return;
- u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL);
-
- if (use_doorbell) {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_ENABLE,
- 0x1);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWID,
- 0xf);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_OFFSET,
- doorbell_index);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- doorbell_size);
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE,
- 0xf);
- } else {
- doorbell_range = REG_SET_FIELD(doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL,
- S2A_DOORBELL_PORT5_RANGE_SIZE,
- 0);
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance,
+ NULL, NULL);
+ return;
}
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_VPE, instance, &ctrl, NULL);
}
static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) {
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d);
+ struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .awaddr_31_28 = 0x3,
+ };
+ u32 ctrl;
+
+ fields.awid = 0x3;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_CP, 0, &ctrl, NULL);
+
+ fields.awid = 0x6;
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_RLC, 0, &ctrl, NULL);
}
static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -231,37 +298,25 @@ nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index) {
- u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL);
-
- if (use_doorbell) {
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_ENABLE,
- 0x1);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWID,
- 0x0);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_OFFSET,
- doorbell_index);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 8);
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
- 0x0);
- } else
- ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
- GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- S2A_DOORBELL_PORT1_RANGE_SIZE,
- 0);
-
- WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
- ih_doorbell_range);
+ const struct amdgpu_nbio_doorbell_fields fields = {
+ .enable = true,
+ .range_offset = doorbell_index,
+ .range_size = 8,
+ };
+ u32 ctrl;
+
+ if (!use_doorbell) {
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, NULL, NULL);
+ return;
+ }
+
+ if (WARN_ON_ONCE(amdgpu_nbio_build_doorbell_entry(
+ adev, &fields, &ctrl, NULL)))
+ return;
+
+ amdgpu_nbio_program_doorbell_entry(adev,
+ AMDGPU_NBIO_DOORBELL_CLIENT_IH, 0, &ctrl, NULL);
}
static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) @@ -343,6 +398,8 @@ static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) {
uint32_t data;
+ nbif_v6_3_1_init_doorbell_entry_registers(adev);
+
data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);
data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;
WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread