* [PATCH 1/5] drm/amd/display: Use dce_audio_create for DCE 6
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
@ 2026-01-18 17:31 ` Timur Kristóf
2026-02-02 14:50 ` Rodrigo Siqueira
2026-01-18 17:31 ` [PATCH 2/5] drm/amd/display: Delete unused dce_clk_mgr.c Timur Kristóf
` (4 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2026-01-18 17:31 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
Cc: Timur Kristóf
The only difference between DCE 6 and other DCE versions is
that DCE 6 doesn't support DCCG_AUDIO_DTO2_USE_512FBR_DTO.
Recently a check was added to dce_aud_wall_dto_setup() to
check that. So now DCE 6 can just use dce_aud_wall_dto_setup()
just like other DCE versions.
Clean up DCE 6 specific audio functions which were otherwise
identical to the rest.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
.../gpu/drm/amd/display/dc/dce/dce_audio.c | 131 ------------------
.../gpu/drm/amd/display/dc/dce/dce_audio.h | 9 --
.../dc/resource/dce60/dce60_resource.c | 2 +-
3 files changed, 1 insertion(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index fcad61c618a1..1276f19164b3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -1150,98 +1150,6 @@ void dce_aud_wall_dto_setup(
}
}
-#if defined(CONFIG_DRM_AMD_DC_SI)
-static void dce60_aud_wall_dto_setup(
- struct audio *audio,
- enum signal_type signal,
- const struct audio_crtc_info *crtc_info,
- const struct audio_pll_info *pll_info)
-{
- struct dce_audio *aud = DCE_AUD(audio);
-
- struct azalia_clock_info clock_info = { 0 };
-
- if (dc_is_hdmi_signal(signal)) {
- uint32_t src_sel;
-
- /*DTO0 Programming goal:
- -generate 24MHz, 128*Fs from 24MHz
- -use DTO0 when an active HDMI port is connected
- (optionally a DP is connected) */
-
- /* calculate DTO settings */
- get_azalia_clock_info_hdmi(
- crtc_info->requested_pixel_clock_100Hz,
- crtc_info->calculated_pixel_clock_100Hz,
- &clock_info);
-
- DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
- "calculated_pixel_clock_100Hz =%d\n"\
- "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
- crtc_info->requested_pixel_clock_100Hz,\
- crtc_info->calculated_pixel_clock_100Hz,\
- clock_info.audio_dto_module,\
- clock_info.audio_dto_phase);
-
- /* On TN/SI, Program DTO source select and DTO select before
- programming DTO modulo and DTO phase. These bits must be
- programmed first, otherwise there will be no HDMI audio at boot
- up. This is a HW sequence change (different from old ASICs).
- Caution when changing this programming sequence.
-
- HDMI enabled, using DTO0
- program master CRTC for DTO0 */
- src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
- REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
- DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
- DCCG_AUDIO_DTO_SEL, 0);
-
- /* module */
- REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
- DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
-
- /* phase */
- REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
- DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
- } else {
- /*DTO1 Programming goal:
- -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
- -default is to used DTO1, and switch to DTO0 when an audio
- master HDMI port is connected
- -use as default for DP
-
- calculate DTO settings */
- get_azalia_clock_info_dp(
- crtc_info->requested_pixel_clock_100Hz,
- pll_info,
- &clock_info);
-
- /* Program DTO select before programming DTO modulo and DTO
- phase. default to use DTO1 */
-
- REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
- DCCG_AUDIO_DTO_SEL, 1);
-
- /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
- * Cannot select 512fs for DP
- *
- * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
- */
-
- /* module */
- REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
- DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
-
- /* phase */
- REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
- DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
-
- /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
-
- }
-}
-#endif
-
static bool dce_aud_endpoint_valid(struct audio *audio)
{
uint32_t value;
@@ -1303,18 +1211,6 @@ static const struct audio_funcs funcs = {
.destroy = dce_aud_destroy,
};
-#if defined(CONFIG_DRM_AMD_DC_SI)
-static const struct audio_funcs dce60_funcs = {
- .endpoint_valid = dce_aud_endpoint_valid,
- .hw_init = dce_aud_hw_init,
- .wall_dto_setup = dce60_aud_wall_dto_setup,
- .az_enable = dce_aud_az_enable,
- .az_disable = dce_aud_az_disable,
- .az_configure = dce_aud_az_configure,
- .destroy = dce_aud_destroy,
-};
-#endif
-
void dce_aud_destroy(struct audio **audio)
{
struct dce_audio *aud = DCE_AUD(*audio);
@@ -1347,30 +1243,3 @@ struct audio *dce_audio_create(
audio->masks = masks;
return &audio->base;
}
-
-#if defined(CONFIG_DRM_AMD_DC_SI)
-struct audio *dce60_audio_create(
- struct dc_context *ctx,
- unsigned int inst,
- const struct dce_audio_registers *reg,
- const struct dce_audio_shift *shifts,
- const struct dce_audio_mask *masks
- )
-{
- struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
-
- if (audio == NULL) {
- ASSERT_CRITICAL(audio);
- return NULL;
- }
-
- audio->base.ctx = ctx;
- audio->base.inst = inst;
- audio->base.funcs = &dce60_funcs;
-
- audio->regs = reg;
- audio->shifts = shifts;
- audio->masks = masks;
- return &audio->base;
-}
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
index 1b7b8b079af4..3f1d161a0045 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
@@ -151,15 +151,6 @@ struct audio *dce_audio_create(
const struct dce_audio_shift *shifts,
const struct dce_audio_mask *masks);
-#if defined(CONFIG_DRM_AMD_DC_SI)
-struct audio *dce60_audio_create(
- struct dc_context *ctx,
- unsigned int inst,
- const struct dce_audio_registers *reg,
- const struct dce_audio_shift *shifts,
- const struct dce_audio_mask *masks);
-#endif
-
void dce_aud_destroy(struct audio **audio);
void dce_aud_hw_init(struct audio *audio);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
index f0152933bee2..e0fbb08e6985 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
@@ -495,7 +495,7 @@ static void read_dce_straps(
static struct audio *create_audio(
struct dc_context *ctx, unsigned int inst)
{
- return dce60_audio_create(ctx, inst,
+ return dce_audio_create(ctx, inst,
&audio_regs[inst], &audio_shift, &audio_mask);
}
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 1/5] drm/amd/display: Use dce_audio_create for DCE 6
2026-01-18 17:31 ` [PATCH 1/5] drm/amd/display: Use dce_audio_create for DCE 6 Timur Kristóf
@ 2026-02-02 14:50 ` Rodrigo Siqueira
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2026-02-02 14:50 UTC (permalink / raw)
To: Timur Kristóf, Alex Hung
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li
On 01/18, Timur Kristóf wrote:
> The only difference between DCE 6 and other DCE versions is
> that DCE 6 doesn't support DCCG_AUDIO_DTO2_USE_512FBR_DTO.
> Recently a check was added to dce_aud_wall_dto_setup() to
> check that. So now DCE 6 can just use dce_aud_wall_dto_setup()
> just like other DCE versions.
>
> Clean up DCE 6 specific audio functions which were otherwise
> identical to the rest.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../gpu/drm/amd/display/dc/dce/dce_audio.c | 131 ------------------
> .../gpu/drm/amd/display/dc/dce/dce_audio.h | 9 --
> .../dc/resource/dce60/dce60_resource.c | 2 +-
> 3 files changed, 1 insertion(+), 141 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> index fcad61c618a1..1276f19164b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> @@ -1150,98 +1150,6 @@ void dce_aud_wall_dto_setup(
> }
> }
>
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -static void dce60_aud_wall_dto_setup(
> - struct audio *audio,
> - enum signal_type signal,
> - const struct audio_crtc_info *crtc_info,
> - const struct audio_pll_info *pll_info)
> -{
> - struct dce_audio *aud = DCE_AUD(audio);
> -
> - struct azalia_clock_info clock_info = { 0 };
> -
> - if (dc_is_hdmi_signal(signal)) {
> - uint32_t src_sel;
> -
> - /*DTO0 Programming goal:
> - -generate 24MHz, 128*Fs from 24MHz
> - -use DTO0 when an active HDMI port is connected
> - (optionally a DP is connected) */
> -
> - /* calculate DTO settings */
> - get_azalia_clock_info_hdmi(
> - crtc_info->requested_pixel_clock_100Hz,
> - crtc_info->calculated_pixel_clock_100Hz,
> - &clock_info);
> -
> - DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
> - "calculated_pixel_clock_100Hz =%d\n"\
> - "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
> - crtc_info->requested_pixel_clock_100Hz,\
> - crtc_info->calculated_pixel_clock_100Hz,\
> - clock_info.audio_dto_module,\
> - clock_info.audio_dto_phase);
> -
> - /* On TN/SI, Program DTO source select and DTO select before
> - programming DTO modulo and DTO phase. These bits must be
> - programmed first, otherwise there will be no HDMI audio at boot
> - up. This is a HW sequence change (different from old ASICs).
> - Caution when changing this programming sequence.
> -
> - HDMI enabled, using DTO0
> - program master CRTC for DTO0 */
> - src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
> - REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
> - DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
> - DCCG_AUDIO_DTO_SEL, 0);
> -
> - /* module */
> - REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
> - DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
> -
> - /* phase */
> - REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
> - DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
> - } else {
> - /*DTO1 Programming goal:
> - -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
> - -default is to used DTO1, and switch to DTO0 when an audio
> - master HDMI port is connected
> - -use as default for DP
> -
> - calculate DTO settings */
> - get_azalia_clock_info_dp(
> - crtc_info->requested_pixel_clock_100Hz,
> - pll_info,
> - &clock_info);
> -
> - /* Program DTO select before programming DTO modulo and DTO
> - phase. default to use DTO1 */
> -
> - REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
> - DCCG_AUDIO_DTO_SEL, 1);
> -
> - /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
> - * Cannot select 512fs for DP
> - *
> - * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
> - */
> -
> - /* module */
> - REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
> - DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
> -
> - /* phase */
> - REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
> - DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
> -
> - /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
> -
> - }
> -}
> -#endif
> -
> static bool dce_aud_endpoint_valid(struct audio *audio)
> {
> uint32_t value;
> @@ -1303,18 +1211,6 @@ static const struct audio_funcs funcs = {
> .destroy = dce_aud_destroy,
> };
>
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -static const struct audio_funcs dce60_funcs = {
> - .endpoint_valid = dce_aud_endpoint_valid,
> - .hw_init = dce_aud_hw_init,
> - .wall_dto_setup = dce60_aud_wall_dto_setup,
> - .az_enable = dce_aud_az_enable,
> - .az_disable = dce_aud_az_disable,
> - .az_configure = dce_aud_az_configure,
> - .destroy = dce_aud_destroy,
> -};
> -#endif
> -
> void dce_aud_destroy(struct audio **audio)
> {
> struct dce_audio *aud = DCE_AUD(*audio);
> @@ -1347,30 +1243,3 @@ struct audio *dce_audio_create(
> audio->masks = masks;
> return &audio->base;
> }
> -
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -struct audio *dce60_audio_create(
> - struct dc_context *ctx,
> - unsigned int inst,
> - const struct dce_audio_registers *reg,
> - const struct dce_audio_shift *shifts,
> - const struct dce_audio_mask *masks
> - )
> -{
> - struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
> -
> - if (audio == NULL) {
> - ASSERT_CRITICAL(audio);
> - return NULL;
> - }
> -
> - audio->base.ctx = ctx;
> - audio->base.inst = inst;
> - audio->base.funcs = &dce60_funcs;
> -
> - audio->regs = reg;
> - audio->shifts = shifts;
> - audio->masks = masks;
> - return &audio->base;
> -}
> -#endif
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
> index 1b7b8b079af4..3f1d161a0045 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
> @@ -151,15 +151,6 @@ struct audio *dce_audio_create(
> const struct dce_audio_shift *shifts,
> const struct dce_audio_mask *masks);
>
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -struct audio *dce60_audio_create(
> - struct dc_context *ctx,
> - unsigned int inst,
> - const struct dce_audio_registers *reg,
> - const struct dce_audio_shift *shifts,
> - const struct dce_audio_mask *masks);
> -#endif
> -
> void dce_aud_destroy(struct audio **audio);
>
> void dce_aud_hw_init(struct audio *audio);
> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
> index f0152933bee2..e0fbb08e6985 100644
> --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c
> @@ -495,7 +495,7 @@ static void read_dce_straps(
> static struct audio *create_audio(
> struct dc_context *ctx, unsigned int inst)
> {
> - return dce60_audio_create(ctx, inst,
> + return dce_audio_create(ctx, inst,
> &audio_regs[inst], &audio_shift, &audio_mask);
Very nice clean-up.
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
> }
>
> --
> 2.52.0
>
--
Rodrigo Siqueira
https://siqueira.tech
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/5] drm/amd/display: Delete unused dce_clk_mgr.c
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
2026-01-18 17:31 ` [PATCH 1/5] drm/amd/display: Use dce_audio_create for DCE 6 Timur Kristóf
@ 2026-01-18 17:31 ` Timur Kristóf
2026-02-02 14:54 ` Rodrigo Siqueira
2026-01-18 17:31 ` [PATCH 3/5] drm/amd/display: Remove unused dce60_clk_mgr register definitions Timur Kristóf
` (3 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2026-01-18 17:31 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
Cc: Timur Kristóf
This file was not compiled or included anywhere and not
modified for years. And it has duplicate function
definitions of many functions that are defined in
other files.
That leads to a lot of confusion (for both developers
and for code editors), eg. when searching for a definition
of a function it can end up on one of the functions in
this file instead of the real implementations.
I suspect that it was forgotten that this should be
deleted after the various clock manager functions were
split into hardware generation specific files.
Delete it now.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
.../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 967 ------------------
1 file changed, 967 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
deleted file mode 100644
index e7acd6eec1fd..000000000000
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ /dev/null
@@ -1,967 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include <linux/slab.h>
-
-#include "dce_clk_mgr.h"
-
-#include "reg_helper.h"
-#include "dmcu.h"
-#include "core_types.h"
-#include "dal_asic_id.h"
-
-#define TO_DCE_CLK_MGR(clocks)\
- container_of(clocks, struct dce_clk_mgr, base)
-
-#define REG(reg) \
- (clk_mgr_dce->regs->reg)
-
-#undef FN
-#define FN(reg_name, field_name) \
- clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
-
-#define CTX \
- clk_mgr_dce->base.ctx
-#define DC_LOGGER \
- clk_mgr->ctx->logger
-
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-
-static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
-
-static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
-
-static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
-/*ClocksStateInvalid - should not be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/*ClocksStateLow*/
-{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
-/*ClocksStateNominal*/
-{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
-/*ClocksStatePerformance*/
-{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
-
-int dentist_get_divider_from_did(int did)
-{
- if (did < DENTIST_BASE_DID_1)
- did = DENTIST_BASE_DID_1;
- if (did > DENTIST_MAX_DID)
- did = DENTIST_MAX_DID;
-
- if (did < DENTIST_BASE_DID_2) {
- return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
- * (did - DENTIST_BASE_DID_1);
- } else if (did < DENTIST_BASE_DID_3) {
- return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
- * (did - DENTIST_BASE_DID_2);
- } else if (did < DENTIST_BASE_DID_4) {
- return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
- * (did - DENTIST_BASE_DID_3);
- } else {
- return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
- * (did - DENTIST_BASE_DID_4);
- }
-}
-
-/* SW will adjust DP REF Clock average value for all purposes
- * (DP DTO / DP Audio DTO and DP GTC)
- if clock is spread for all cases:
- -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
- calculations for DS_INCR/DS_MODULO (this is planned to be default case)
- -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
- calculations (not planned to be used, but average clock should still
- be valid)
- -if SS enabled on DP Ref clock and HW de-spreading disabled
- (should not be case with CIK) then SW should program all rates
- generated according to average value (case as with previous ASICs)
- */
-static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz)
-{
- if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
- struct fixed31_32 ss_percentage = dc_fixpt_div_int(
- dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
- clk_mgr_dce->dprefclk_ss_divider), 200);
- struct fixed31_32 adj_dp_ref_clk_khz;
-
- ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
- adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
- dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
- }
- return dp_ref_clk_khz;
-}
-
-static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- int dprefclk_wdivider;
- int dprefclk_src_sel;
- int dp_ref_clk_khz = 600000;
- int target_div;
-
- /* ASSERT DP Reference Clock source is from DFS*/
- REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
- ASSERT(dprefclk_src_sel == 0);
-
- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
- REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
-
- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
- target_div = dentist_get_divider_from_did(dprefclk_wdivider);
-
- /* Calculate the current DFS clock, in kHz.*/
- dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
- * clk_mgr_dce->dentist_vco_freq_khz) / target_div;
-
- return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz);
-}
-
-int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
-
- return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
-}
-
-/* unit: in_khz before mode set, get pixel clock from context. ASIC register
- * may not be programmed yet
- */
-static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
-{
- uint32_t max_pix_clk = 0;
- int i;
-
- for (i = 0; i < MAX_PIPES; i++) {
- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
- if (pipe_ctx->stream == NULL)
- continue;
-
- /* do not check under lay */
- if (pipe_ctx->top_pipe)
- continue;
-
- if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
- max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
-
- /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
- * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
- */
- if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
- pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
- max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
- }
-
- return max_pix_clk;
-}
-
-static enum dm_pp_clocks_state dce_get_required_clocks_state(
- struct clk_mgr *clk_mgr,
- struct dc_state *context)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- int i;
- enum dm_pp_clocks_state low_req_clk;
- int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
-
- /* Iterate from highest supported to lowest valid state, and update
- * lowest RequiredState with the lowest state that satisfies
- * all required clocks
- */
- for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
- if (context->bw_ctx.bw.dce.dispclk_khz >
- clk_mgr_dce->max_clks_by_state[i].display_clk_khz
- || max_pix_clk >
- clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
- break;
-
- low_req_clk = i + 1;
- if (low_req_clk > clk_mgr_dce->max_clks_state) {
- /* set max clock state for high phyclock, invalid on exceeding display clock */
- if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
- < context->bw_ctx.bw.dce.dispclk_khz)
- low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
- else
- low_req_clk = clk_mgr_dce->max_clks_state;
- }
-
- return low_req_clk;
-}
-
-static int dce_set_clock(
- struct clk_mgr *clk_mgr,
- int requested_clk_khz)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
- struct dc_bios *bp = clk_mgr->ctx->dc_bios;
- int actual_clock = requested_clk_khz;
- struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
-
- /* Make sure requested clock isn't lower than minimum threshold*/
- if (requested_clk_khz > 0)
- requested_clk_khz = max(requested_clk_khz,
- clk_mgr_dce->dentist_vco_freq_khz / 64);
-
- /* Prepare to program display clock*/
- pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
- pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
-
- if (clk_mgr_dce->dfs_bypass_active)
- pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
-
- bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
-
- if (clk_mgr_dce->dfs_bypass_active) {
- /* Cache the fixed display clock*/
- clk_mgr_dce->dfs_bypass_disp_clk =
- pxl_clk_params.dfs_bypass_display_clock;
- actual_clock = pxl_clk_params.dfs_bypass_display_clock;
- }
-
- /* from power down, we need mark the clock state as ClocksStateNominal
- * from HWReset, so when resume we will call pplib voltage regulator.*/
- if (requested_clk_khz == 0)
- clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
- if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
- dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
-
- return actual_clock;
-}
-
-int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct bp_set_dce_clock_parameters dce_clk_params;
- struct dc_bios *bp = clk_mgr->ctx->dc_bios;
- struct dc *core_dc = clk_mgr->ctx->dc;
- struct dmcu *dmcu = core_dc->res_pool->dmcu;
- int actual_clock = requested_clk_khz;
- /* Prepare to program display clock*/
- memset(&dce_clk_params, 0, sizeof(dce_clk_params));
-
- /* Make sure requested clock isn't lower than minimum threshold*/
- if (requested_clk_khz > 0)
- requested_clk_khz = max(requested_clk_khz,
- clk_mgr_dce->dentist_vco_freq_khz / 62);
-
- dce_clk_params.target_clock_frequency = requested_clk_khz;
- dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
- dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
-
- bp->funcs->set_dce_clock(bp, &dce_clk_params);
- actual_clock = dce_clk_params.target_clock_frequency;
-
- /* from power down, we need mark the clock state as ClocksStateNominal
- * from HWReset, so when resume we will call pplib voltage regulator.*/
- if (requested_clk_khz == 0)
- clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
- /*Program DP ref Clock*/
- /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
- dce_clk_params.target_clock_frequency = 0;
- dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-
- if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) &&
- ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev)))
- dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
- (dce_clk_params.pll_id ==
- CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
- else
- dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
-
- bp->funcs->set_dce_clock(bp, &dce_clk_params);
-
- if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
- if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
- if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
- dmcu->funcs->set_psr_wait_loop(dmcu,
- actual_clock / 1000 / 7);
- }
- }
-
- clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
- return actual_clock;
-}
-
-static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce)
-{
- struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
- struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
- struct integrated_info info = { { { 0 } } };
- struct dc_firmware_info fw_info = { { 0 } };
- int i;
-
- if (bp->integrated_info)
- info = *bp->integrated_info;
-
- clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
- if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
- bp->funcs->get_firmware_info(bp, &fw_info);
- clk_mgr_dce->dentist_vco_freq_khz =
- fw_info.smu_gpu_pll_output_freq;
- if (clk_mgr_dce->dentist_vco_freq_khz == 0)
- clk_mgr_dce->dentist_vco_freq_khz = 3600000;
- }
-
- /*update the maximum display clock for each power state*/
- for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
- enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
-
- switch (i) {
- case 0:
- clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
- break;
-
- case 1:
- clk_state = DM_PP_CLOCKS_STATE_LOW;
- break;
-
- case 2:
- clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
- break;
-
- case 3:
- clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
- break;
-
- default:
- clk_state = DM_PP_CLOCKS_STATE_INVALID;
- break;
- }
-
- /*Do not allow bad VBIOS/SBIOS to override with invalid values,
- * check for > 100MHz*/
- if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
- clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
- info.disp_clk_voltage[i].max_supported_clk;
- }
-
- if (!debug->disable_dfs_bypass && bp->integrated_info)
- if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
- clk_mgr_dce->dfs_bypass_enabled = true;
-}
-
-void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce)
-{
- struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
- int ss_info_num = bp->funcs->get_ss_entry_number(
- bp, AS_SIGNAL_TYPE_GPU_PLL);
-
- if (ss_info_num) {
- struct spread_spectrum_info info = { { 0 } };
- enum bp_result result = bp->funcs->get_spread_spectrum_info(
- bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
-
- /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
- * even if SS not enabled and in that case
- * SSInfo.spreadSpectrumPercentage !=0 would be sign
- * that SS is enabled
- */
- if (result == BP_RESULT_OK &&
- info.spread_spectrum_percentage != 0) {
- clk_mgr_dce->ss_on_dprefclk = true;
- clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
-
- if (info.type.CENTER_MODE == 0) {
- /* TODO: Currently for DP Reference clock we
- * need only SS percentage for
- * downspread */
- clk_mgr_dce->dprefclk_ss_percentage =
- info.spread_spectrum_percentage;
- }
-
- return;
- }
-
- result = bp->funcs->get_spread_spectrum_info(
- bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
-
- /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
- * even if SS not enabled and in that case
- * SSInfo.spreadSpectrumPercentage !=0 would be sign
- * that SS is enabled
- */
- if (result == BP_RESULT_OK &&
- info.spread_spectrum_percentage != 0) {
- clk_mgr_dce->ss_on_dprefclk = true;
- clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
-
- if (info.type.CENTER_MODE == 0) {
- /* Currently for DP Reference clock we
- * need only SS percentage for
- * downspread */
- clk_mgr_dce->dprefclk_ss_percentage =
- info.spread_spectrum_percentage;
- }
- if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
- clk_mgr_dce->dprefclk_ss_percentage = 0;
- }
- }
-}
-
-/**
- * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
- * @clk_mgr: clock manager base structure
- *
- * Reads from VBIOS the XGMI spread spectrum info and saves it within
- * the dce clock manager. This operation will overwrite the existing dprefclk
- * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also
- * sets the ->xgmi_enabled flag.
- */
-void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- enum bp_result result;
- struct spread_spectrum_info info = { { 0 } };
- struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
-
- clk_mgr_dce->xgmi_enabled = false;
-
- result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,
- 0, &info);
- if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) {
- clk_mgr_dce->xgmi_enabled = true;
- clk_mgr_dce->ss_on_dprefclk = true;
- clk_mgr_dce->dprefclk_ss_divider =
- info.spread_percentage_divider;
-
- if (info.type.CENTER_MODE == 0) {
- /* Currently for DP Reference clock we
- * need only SS percentage for
- * downspread */
- clk_mgr_dce->dprefclk_ss_percentage =
- info.spread_spectrum_percentage;
- }
- }
-}
-
-void dce110_fill_display_configs(
- const struct dc_state *context,
- struct dm_pp_display_configuration *pp_display_cfg)
-{
- int j;
- int num_cfgs = 0;
-
- for (j = 0; j < context->stream_count; j++) {
- int k;
-
- const struct dc_stream_state *stream = context->streams[j];
- struct dm_pp_single_disp_config *cfg =
- &pp_display_cfg->disp_configs[num_cfgs];
- const struct pipe_ctx *pipe_ctx = NULL;
-
- for (k = 0; k < MAX_PIPES; k++)
- if (stream == context->res_ctx.pipe_ctx[k].stream) {
- pipe_ctx = &context->res_ctx.pipe_ctx[k];
- break;
- }
-
- ASSERT(pipe_ctx != NULL);
-
- /* only notify active stream */
- if (stream->dpms_off)
- continue;
-
- num_cfgs++;
- cfg->signal = pipe_ctx->stream->signal;
- cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
- cfg->src_height = stream->src.height;
- cfg->src_width = stream->src.width;
- cfg->ddi_channel_mapping =
- stream->link->ddi_channel_mapping.raw;
- cfg->transmitter =
- stream->link->link_enc->transmitter;
- cfg->link_settings.lane_count =
- stream->link->cur_link_settings.lane_count;
- cfg->link_settings.link_rate =
- stream->link->cur_link_settings.link_rate;
- cfg->link_settings.link_spread =
- stream->link->cur_link_settings.link_spread;
- cfg->sym_clock = stream->phy_pix_clk;
- /* Round v_refresh*/
- cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
- cfg->v_refresh /= stream->timing.h_total;
- cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
- / stream->timing.v_total;
- }
-
- pp_display_cfg->display_count = num_cfgs;
-}
-
-static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
-{
- uint8_t j;
- uint32_t min_vertical_blank_time = -1;
-
- for (j = 0; j < context->stream_count; j++) {
- struct dc_stream_state *stream = context->streams[j];
- uint32_t vertical_blank_in_pixels = 0;
- uint32_t vertical_blank_time = 0;
-
- vertical_blank_in_pixels = stream->timing.h_total *
- (stream->timing.v_total
- - stream->timing.v_addressable);
-
- vertical_blank_time = vertical_blank_in_pixels
- * 10000 / stream->timing.pix_clk_100hz;
-
- if (min_vertical_blank_time > vertical_blank_time)
- min_vertical_blank_time = vertical_blank_time;
- }
-
- return min_vertical_blank_time;
-}
-
-static int determine_sclk_from_bounding_box(
- const struct dc *dc,
- int required_sclk)
-{
- int i;
-
- /*
- * Some asics do not give us sclk levels, so we just report the actual
- * required sclk
- */
- if (dc->sclk_lvls.num_levels == 0)
- return required_sclk;
-
- for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
- if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
- return dc->sclk_lvls.clocks_in_khz[i];
- }
- /*
- * even maximum level could not satisfy requirement, this
- * is unexpected at this stage, should have been caught at
- * validation time
- */
- ASSERT(0);
- return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
-}
-
-static void dce_pplib_apply_display_requirements(
- struct dc *dc,
- struct dc_state *context)
-{
- struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-
- pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
-
- dce110_fill_display_configs(context, pp_display_cfg);
-
- if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
- dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-}
-
-static void dce11_pplib_apply_display_requirements(
- struct dc *dc,
- struct dc_state *context)
-{
- struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-
- pp_display_cfg->all_displays_in_sync =
- context->bw_ctx.bw.dce.all_displays_in_sync;
- pp_display_cfg->nb_pstate_switch_disable =
- context->bw_ctx.bw.dce.nbp_state_change_enable == false;
- pp_display_cfg->cpu_cc6_disable =
- context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
- pp_display_cfg->cpu_pstate_disable =
- context->bw_ctx.bw.dce.cpup_state_change_enable == false;
- pp_display_cfg->cpu_pstate_separation_time =
- context->bw_ctx.bw.dce.blackout_recovery_time_us;
-
- pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
- / MEMORY_TYPE_MULTIPLIER_CZ;
-
- pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
- dc,
- context->bw_ctx.bw.dce.sclk_khz);
-
- /*
- * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
- * This is not required for less than 5 displays,
- * thus don't request decfclk in dc to avoid impact
- * on power saving.
- *
- */
- pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
- pp_display_cfg->min_engine_clock_khz : 0;
-
- pp_display_cfg->min_engine_clock_deep_sleep_khz
- = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
-
- pp_display_cfg->avail_mclk_switch_time_us =
- dce110_get_min_vblank_time_us(context);
- /* TODO: dce11.2*/
- pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-
- pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
-
- dce110_fill_display_configs(context, pp_display_cfg);
-
- /* TODO: is this still applicable?*/
- if (pp_display_cfg->display_count == 1) {
- const struct dc_crtc_timing *timing =
- &context->streams[0]->timing;
-
- pp_display_cfg->crtc_index =
- pp_display_cfg->disp_configs[0].pipe_idx;
- pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
- }
-
- if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
- dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-}
-
-static void dce_update_clocks(struct clk_mgr *clk_mgr,
- struct dc_state *context,
- bool safe_to_lower)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct dm_pp_power_level_change_request level_change_req;
- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
- /*TODO: W/A for dal3 linux, investigate why this works */
- if (!clk_mgr_dce->dfs_bypass_active)
- patched_disp_clk = patched_disp_clk * 115 / 100;
-
- level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
- /* get max clock state from PPLIB */
- if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
- || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
- if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
- clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
- }
-
- if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
- patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk);
- clk_mgr->clks.dispclk_khz = patched_disp_clk;
- }
- dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-}
-
-static void dce11_update_clocks(struct clk_mgr *clk_mgr,
- struct dc_state *context,
- bool safe_to_lower)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct dm_pp_power_level_change_request level_change_req;
- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
- /*TODO: W/A for dal3 linux, investigate why this works */
- if (!clk_mgr_dce->dfs_bypass_active)
- patched_disp_clk = patched_disp_clk * 115 / 100;
-
- level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
- /* get max clock state from PPLIB */
- if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
- || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
- if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
- clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
- }
-
- if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
- context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
- clk_mgr->clks.dispclk_khz = patched_disp_clk;
- }
- dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-}
-
-static void dce112_update_clocks(struct clk_mgr *clk_mgr,
- struct dc_state *context,
- bool safe_to_lower)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct dm_pp_power_level_change_request level_change_req;
- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
- /*TODO: W/A for dal3 linux, investigate why this works */
- if (!clk_mgr_dce->dfs_bypass_active)
- patched_disp_clk = patched_disp_clk * 115 / 100;
-
- level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
- /* get max clock state from PPLIB */
- if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
- || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
- if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
- clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
- }
-
- if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
- patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk);
- clk_mgr->clks.dispclk_khz = patched_disp_clk;
- }
- dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-}
-
-static void dce12_update_clocks(struct clk_mgr *clk_mgr,
- struct dc_state *context,
- bool safe_to_lower)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
- struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
- int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
- /*TODO: W/A for dal3 linux, investigate why this works */
- if (!clk_mgr_dce->dfs_bypass_active)
- patched_disp_clk = patched_disp_clk * 115 / 100;
-
- if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
- clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
- /*
- * When xGMI is enabled, the display clk needs to be adjusted
- * with the WAFL link's SS percentage.
- */
- if (clk_mgr_dce->xgmi_enabled)
- patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss(
- clk_mgr_dce, patched_disp_clk);
- clock_voltage_req.clocks_in_khz = patched_disp_clk;
- clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk);
-
- dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
- }
-
- if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) {
- clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
- clock_voltage_req.clocks_in_khz = max_pix_clk;
- clk_mgr->clks.phyclk_khz = max_pix_clk;
-
- dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
- }
- dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-}
-
-static const struct clk_mgr_funcs dce120_funcs = {
- .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
- .update_clocks = dce12_update_clocks
-};
-
-static const struct clk_mgr_funcs dce112_funcs = {
- .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
- .update_clocks = dce112_update_clocks
-};
-
-static const struct clk_mgr_funcs dce110_funcs = {
- .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
- .update_clocks = dce11_update_clocks,
-};
-
-static const struct clk_mgr_funcs dce_funcs = {
- .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
- .update_clocks = dce_update_clocks
-};
-
-static void dce_clk_mgr_construct(
- struct dce_clk_mgr *clk_mgr_dce,
- struct dc_context *ctx,
- const struct clk_mgr_registers *regs,
- const struct clk_mgr_shift *clk_shift,
- const struct clk_mgr_mask *clk_mask)
-{
- struct clk_mgr *base = &clk_mgr_dce->base;
- struct dm_pp_static_clock_info static_clk_info = {0};
-
- base->ctx = ctx;
- base->funcs = &dce_funcs;
-
- clk_mgr_dce->regs = regs;
- clk_mgr_dce->clk_mgr_shift = clk_shift;
- clk_mgr_dce->clk_mgr_mask = clk_mask;
-
- clk_mgr_dce->dfs_bypass_disp_clk = 0;
-
- clk_mgr_dce->dprefclk_ss_percentage = 0;
- clk_mgr_dce->dprefclk_ss_divider = 1000;
- clk_mgr_dce->ss_on_dprefclk = false;
-
-
- if (dm_pp_get_static_clocks(ctx, &static_clk_info))
- clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
- else
- clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
- clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-
- dce_clock_read_integrated_info(clk_mgr_dce);
- dce_clock_read_ss_info(clk_mgr_dce);
-}
-
-struct clk_mgr *dce_clk_mgr_create(
- struct dc_context *ctx,
- const struct clk_mgr_registers *regs,
- const struct clk_mgr_shift *clk_shift,
- const struct clk_mgr_mask *clk_mask)
-{
- struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
-
- if (clk_mgr_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- memcpy(clk_mgr_dce->max_clks_by_state,
- dce80_max_clks_by_state,
- sizeof(dce80_max_clks_by_state));
-
- dce_clk_mgr_construct(
- clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
-
- return &clk_mgr_dce->base;
-}
-
-struct clk_mgr *dce110_clk_mgr_create(
- struct dc_context *ctx,
- const struct clk_mgr_registers *regs,
- const struct clk_mgr_shift *clk_shift,
- const struct clk_mgr_mask *clk_mask)
-{
- struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
-
- if (clk_mgr_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- memcpy(clk_mgr_dce->max_clks_by_state,
- dce110_max_clks_by_state,
- sizeof(dce110_max_clks_by_state));
-
- dce_clk_mgr_construct(
- clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
-
- clk_mgr_dce->base.funcs = &dce110_funcs;
-
- return &clk_mgr_dce->base;
-}
-
-struct clk_mgr *dce112_clk_mgr_create(
- struct dc_context *ctx,
- const struct clk_mgr_registers *regs,
- const struct clk_mgr_shift *clk_shift,
- const struct clk_mgr_mask *clk_mask)
-{
- struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
-
- if (clk_mgr_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- memcpy(clk_mgr_dce->max_clks_by_state,
- dce112_max_clks_by_state,
- sizeof(dce112_max_clks_by_state));
-
- dce_clk_mgr_construct(
- clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
-
- clk_mgr_dce->base.funcs = &dce112_funcs;
-
- return &clk_mgr_dce->base;
-}
-
-struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx)
-{
- struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
-
- if (clk_mgr_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- memcpy(clk_mgr_dce->max_clks_by_state,
- dce120_max_clks_by_state,
- sizeof(dce120_max_clks_by_state));
-
- dce_clk_mgr_construct(
- clk_mgr_dce, ctx, NULL, NULL, NULL);
-
- clk_mgr_dce->dprefclk_khz = 600000;
- clk_mgr_dce->base.funcs = &dce120_funcs;
-
- return &clk_mgr_dce->base;
-}
-
-struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx)
-{
- struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce),
- GFP_KERNEL);
-
- if (clk_mgr_dce == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
-
- memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state,
- sizeof(dce120_max_clks_by_state));
-
- dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL);
-
- clk_mgr_dce->dprefclk_khz = 625000;
- clk_mgr_dce->base.funcs = &dce120_funcs;
-
- return &clk_mgr_dce->base;
-}
-
-void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr)
-{
- struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr);
-
- kfree(clk_mgr_dce);
- *clk_mgr = NULL;
-}
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/5] drm/amd/display: Delete unused dce_clk_mgr.c
2026-01-18 17:31 ` [PATCH 2/5] drm/amd/display: Delete unused dce_clk_mgr.c Timur Kristóf
@ 2026-02-02 14:54 ` Rodrigo Siqueira
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2026-02-02 14:54 UTC (permalink / raw)
To: Timur Kristóf, Alex Hung
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li
On 01/18, Timur Kristóf wrote:
> This file was not compiled or included anywhere and not
> modified for years. And it has duplicate function
> definitions of many functions that are defined in
> other files.
>
> That leads to a lot of confusion (for both developers
> and for code editors), eg. when searching for a definition
> of a function it can end up on one of the functions in
> this file instead of the real implementations.
>
> I suspect that it was forgotten that this should be
> deleted after the various clock manager functions were
> split into hardware generation specific files.
> Delete it now.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 967 ------------------
> 1 file changed, 967 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
> deleted file mode 100644
> index e7acd6eec1fd..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
> +++ /dev/null
> @@ -1,967 +0,0 @@
> -/*
> - * Copyright 2012-16 Advanced Micro Devices, Inc.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -#include <linux/slab.h>
> -
> -#include "dce_clk_mgr.h"
> -
> -#include "reg_helper.h"
> -#include "dmcu.h"
> -#include "core_types.h"
> -#include "dal_asic_id.h"
> -
> -#define TO_DCE_CLK_MGR(clocks)\
> - container_of(clocks, struct dce_clk_mgr, base)
> -
> -#define REG(reg) \
> - (clk_mgr_dce->regs->reg)
> -
> -#undef FN
> -#define FN(reg_name, field_name) \
> - clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
> -
> -#define CTX \
> - clk_mgr_dce->base.ctx
> -#define DC_LOGGER \
> - clk_mgr->ctx->logger
> -
> -/* Max clock values for each state indexed by "enum clocks_state": */
> -static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
> -/* ClocksStateInvalid - should not be used */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateLow */
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> -/* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> -/* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> -
> -static const struct state_dependent_clocks dce110_max_clks_by_state[] = {
> -/*ClocksStateInvalid - should not be used*/
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
> -/*ClocksStateLow*/
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 },
> -/*ClocksStateNominal*/
> -{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 },
> -/*ClocksStatePerformance*/
> -{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } };
> -
> -static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
> -/*ClocksStateInvalid - should not be used*/
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
> -{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
> -/*ClocksStateLow*/
> -{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
> -/*ClocksStateNominal*/
> -{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
> -/*ClocksStatePerformance*/
> -{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
> -
> -static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
> -/*ClocksStateInvalid - should not be used*/
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/*ClocksStateLow*/
> -{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
> -/*ClocksStateNominal*/
> -{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
> -/*ClocksStatePerformance*/
> -{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
> -
> -int dentist_get_divider_from_did(int did)
> -{
> - if (did < DENTIST_BASE_DID_1)
> - did = DENTIST_BASE_DID_1;
> - if (did > DENTIST_MAX_DID)
> - did = DENTIST_MAX_DID;
> -
> - if (did < DENTIST_BASE_DID_2) {
> - return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
> - * (did - DENTIST_BASE_DID_1);
> - } else if (did < DENTIST_BASE_DID_3) {
> - return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
> - * (did - DENTIST_BASE_DID_2);
> - } else if (did < DENTIST_BASE_DID_4) {
> - return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
> - * (did - DENTIST_BASE_DID_3);
> - } else {
> - return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
> - * (did - DENTIST_BASE_DID_4);
> - }
> -}
> -
> -/* SW will adjust DP REF Clock average value for all purposes
> - * (DP DTO / DP Audio DTO and DP GTC)
> - if clock is spread for all cases:
> - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
> - calculations for DS_INCR/DS_MODULO (this is planned to be default case)
> - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW
> - calculations (not planned to be used, but average clock should still
> - be valid)
> - -if SS enabled on DP Ref clock and HW de-spreading disabled
> - (should not be case with CIK) then SW should program all rates
> - generated according to average value (case as with previous ASICs)
> - */
> -static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz)
> -{
> - if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) {
> - struct fixed31_32 ss_percentage = dc_fixpt_div_int(
> - dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage,
> - clk_mgr_dce->dprefclk_ss_divider), 200);
> - struct fixed31_32 adj_dp_ref_clk_khz;
> -
> - ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
> - adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
> - dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
> - }
> - return dp_ref_clk_khz;
> -}
> -
> -static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - int dprefclk_wdivider;
> - int dprefclk_src_sel;
> - int dp_ref_clk_khz = 600000;
> - int target_div;
> -
> - /* ASSERT DP Reference Clock source is from DFS*/
> - REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
> - ASSERT(dprefclk_src_sel == 0);
> -
> - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently
> - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/
> - REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
> -
> - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
> - target_div = dentist_get_divider_from_did(dprefclk_wdivider);
> -
> - /* Calculate the current DFS clock, in kHz.*/
> - dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
> - * clk_mgr_dce->dentist_vco_freq_khz) / target_div;
> -
> - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz);
> -}
> -
> -int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> -
> - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz);
> -}
> -
> -/* unit: in_khz before mode set, get pixel clock from context. ASIC register
> - * may not be programmed yet
> - */
> -static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
> -{
> - uint32_t max_pix_clk = 0;
> - int i;
> -
> - for (i = 0; i < MAX_PIPES; i++) {
> - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
> -
> - if (pipe_ctx->stream == NULL)
> - continue;
> -
> - /* do not check under lay */
> - if (pipe_ctx->top_pipe)
> - continue;
> -
> - if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
> - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
> -
> - /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
> - * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
> - */
> - if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
> - pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
> - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
> - }
> -
> - return max_pix_clk;
> -}
> -
> -static enum dm_pp_clocks_state dce_get_required_clocks_state(
> - struct clk_mgr *clk_mgr,
> - struct dc_state *context)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - int i;
> - enum dm_pp_clocks_state low_req_clk;
> - int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
> -
> - /* Iterate from highest supported to lowest valid state, and update
> - * lowest RequiredState with the lowest state that satisfies
> - * all required clocks
> - */
> - for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
> - if (context->bw_ctx.bw.dce.dispclk_khz >
> - clk_mgr_dce->max_clks_by_state[i].display_clk_khz
> - || max_pix_clk >
> - clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz)
> - break;
> -
> - low_req_clk = i + 1;
> - if (low_req_clk > clk_mgr_dce->max_clks_state) {
> - /* set max clock state for high phyclock, invalid on exceeding display clock */
> - if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz
> - < context->bw_ctx.bw.dce.dispclk_khz)
> - low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
> - else
> - low_req_clk = clk_mgr_dce->max_clks_state;
> - }
> -
> - return low_req_clk;
> -}
> -
> -static int dce_set_clock(
> - struct clk_mgr *clk_mgr,
> - int requested_clk_khz)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
> - struct dc_bios *bp = clk_mgr->ctx->dc_bios;
> - int actual_clock = requested_clk_khz;
> - struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;
> -
> - /* Make sure requested clock isn't lower than minimum threshold*/
> - if (requested_clk_khz > 0)
> - requested_clk_khz = max(requested_clk_khz,
> - clk_mgr_dce->dentist_vco_freq_khz / 64);
> -
> - /* Prepare to program display clock*/
> - pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
> - pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
> -
> - if (clk_mgr_dce->dfs_bypass_active)
> - pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
> -
> - bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
> -
> - if (clk_mgr_dce->dfs_bypass_active) {
> - /* Cache the fixed display clock*/
> - clk_mgr_dce->dfs_bypass_disp_clk =
> - pxl_clk_params.dfs_bypass_display_clock;
> - actual_clock = pxl_clk_params.dfs_bypass_display_clock;
> - }
> -
> - /* from power down, we need mark the clock state as ClocksStateNominal
> - * from HWReset, so when resume we will call pplib voltage regulator.*/
> - if (requested_clk_khz == 0)
> - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> -
> - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
> - dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
> -
> - return actual_clock;
> -}
> -
> -int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct bp_set_dce_clock_parameters dce_clk_params;
> - struct dc_bios *bp = clk_mgr->ctx->dc_bios;
> - struct dc *core_dc = clk_mgr->ctx->dc;
> - struct dmcu *dmcu = core_dc->res_pool->dmcu;
> - int actual_clock = requested_clk_khz;
> - /* Prepare to program display clock*/
> - memset(&dce_clk_params, 0, sizeof(dce_clk_params));
> -
> - /* Make sure requested clock isn't lower than minimum threshold*/
> - if (requested_clk_khz > 0)
> - requested_clk_khz = max(requested_clk_khz,
> - clk_mgr_dce->dentist_vco_freq_khz / 62);
> -
> - dce_clk_params.target_clock_frequency = requested_clk_khz;
> - dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
> - dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
> -
> - bp->funcs->set_dce_clock(bp, &dce_clk_params);
> - actual_clock = dce_clk_params.target_clock_frequency;
> -
> - /* from power down, we need mark the clock state as ClocksStateNominal
> - * from HWReset, so when resume we will call pplib voltage regulator.*/
> - if (requested_clk_khz == 0)
> - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> -
> - /*Program DP ref Clock*/
> - /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
> - dce_clk_params.target_clock_frequency = 0;
> - dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
> -
> - if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) &&
> - ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev)))
> - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
> - (dce_clk_params.pll_id ==
> - CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
> - else
> - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
> -
> - bp->funcs->set_dce_clock(bp, &dce_clk_params);
> -
> - if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
> - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
> - if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
> - dmcu->funcs->set_psr_wait_loop(dmcu,
> - actual_clock / 1000 / 7);
> - }
> - }
> -
> - clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
> - return actual_clock;
> -}
> -
> -static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce)
> -{
> - struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
> - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
> - struct integrated_info info = { { { 0 } } };
> - struct dc_firmware_info fw_info = { { 0 } };
> - int i;
> -
> - if (bp->integrated_info)
> - info = *bp->integrated_info;
> -
> - clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
> - if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
> - bp->funcs->get_firmware_info(bp, &fw_info);
> - clk_mgr_dce->dentist_vco_freq_khz =
> - fw_info.smu_gpu_pll_output_freq;
> - if (clk_mgr_dce->dentist_vco_freq_khz == 0)
> - clk_mgr_dce->dentist_vco_freq_khz = 3600000;
> - }
> -
> - /*update the maximum display clock for each power state*/
> - for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
> - enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID;
> -
> - switch (i) {
> - case 0:
> - clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW;
> - break;
> -
> - case 1:
> - clk_state = DM_PP_CLOCKS_STATE_LOW;
> - break;
> -
> - case 2:
> - clk_state = DM_PP_CLOCKS_STATE_NOMINAL;
> - break;
> -
> - case 3:
> - clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE;
> - break;
> -
> - default:
> - clk_state = DM_PP_CLOCKS_STATE_INVALID;
> - break;
> - }
> -
> - /*Do not allow bad VBIOS/SBIOS to override with invalid values,
> - * check for > 100MHz*/
> - if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
> - clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
> - info.disp_clk_voltage[i].max_supported_clk;
> - }
> -
> - if (!debug->disable_dfs_bypass && bp->integrated_info)
> - if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
> - clk_mgr_dce->dfs_bypass_enabled = true;
> -}
> -
> -void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce)
> -{
> - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
> - int ss_info_num = bp->funcs->get_ss_entry_number(
> - bp, AS_SIGNAL_TYPE_GPU_PLL);
> -
> - if (ss_info_num) {
> - struct spread_spectrum_info info = { { 0 } };
> - enum bp_result result = bp->funcs->get_spread_spectrum_info(
> - bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
> -
> - /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS
> - * even if SS not enabled and in that case
> - * SSInfo.spreadSpectrumPercentage !=0 would be sign
> - * that SS is enabled
> - */
> - if (result == BP_RESULT_OK &&
> - info.spread_spectrum_percentage != 0) {
> - clk_mgr_dce->ss_on_dprefclk = true;
> - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
> -
> - if (info.type.CENTER_MODE == 0) {
> - /* TODO: Currently for DP Reference clock we
> - * need only SS percentage for
> - * downspread */
> - clk_mgr_dce->dprefclk_ss_percentage =
> - info.spread_spectrum_percentage;
> - }
> -
> - return;
> - }
> -
> - result = bp->funcs->get_spread_spectrum_info(
> - bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info);
> -
> - /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS
> - * even if SS not enabled and in that case
> - * SSInfo.spreadSpectrumPercentage !=0 would be sign
> - * that SS is enabled
> - */
> - if (result == BP_RESULT_OK &&
> - info.spread_spectrum_percentage != 0) {
> - clk_mgr_dce->ss_on_dprefclk = true;
> - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider;
> -
> - if (info.type.CENTER_MODE == 0) {
> - /* Currently for DP Reference clock we
> - * need only SS percentage for
> - * downspread */
> - clk_mgr_dce->dprefclk_ss_percentage =
> - info.spread_spectrum_percentage;
> - }
> - if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
> - clk_mgr_dce->dprefclk_ss_percentage = 0;
> - }
> - }
> -}
> -
> -/**
> - * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
> - * @clk_mgr: clock manager base structure
> - *
> - * Reads from VBIOS the XGMI spread spectrum info and saves it within
> - * the dce clock manager. This operation will overwrite the existing dprefclk
> - * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also
> - * sets the ->xgmi_enabled flag.
> - */
> -void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - enum bp_result result;
> - struct spread_spectrum_info info = { { 0 } };
> - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
> -
> - clk_mgr_dce->xgmi_enabled = false;
> -
> - result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,
> - 0, &info);
> - if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) {
> - clk_mgr_dce->xgmi_enabled = true;
> - clk_mgr_dce->ss_on_dprefclk = true;
> - clk_mgr_dce->dprefclk_ss_divider =
> - info.spread_percentage_divider;
> -
> - if (info.type.CENTER_MODE == 0) {
> - /* Currently for DP Reference clock we
> - * need only SS percentage for
> - * downspread */
> - clk_mgr_dce->dprefclk_ss_percentage =
> - info.spread_spectrum_percentage;
> - }
> - }
> -}
> -
> -void dce110_fill_display_configs(
> - const struct dc_state *context,
> - struct dm_pp_display_configuration *pp_display_cfg)
> -{
> - int j;
> - int num_cfgs = 0;
> -
> - for (j = 0; j < context->stream_count; j++) {
> - int k;
> -
> - const struct dc_stream_state *stream = context->streams[j];
> - struct dm_pp_single_disp_config *cfg =
> - &pp_display_cfg->disp_configs[num_cfgs];
> - const struct pipe_ctx *pipe_ctx = NULL;
> -
> - for (k = 0; k < MAX_PIPES; k++)
> - if (stream == context->res_ctx.pipe_ctx[k].stream) {
> - pipe_ctx = &context->res_ctx.pipe_ctx[k];
> - break;
> - }
> -
> - ASSERT(pipe_ctx != NULL);
> -
> - /* only notify active stream */
> - if (stream->dpms_off)
> - continue;
> -
> - num_cfgs++;
> - cfg->signal = pipe_ctx->stream->signal;
> - cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
> - cfg->src_height = stream->src.height;
> - cfg->src_width = stream->src.width;
> - cfg->ddi_channel_mapping =
> - stream->link->ddi_channel_mapping.raw;
> - cfg->transmitter =
> - stream->link->link_enc->transmitter;
> - cfg->link_settings.lane_count =
> - stream->link->cur_link_settings.lane_count;
> - cfg->link_settings.link_rate =
> - stream->link->cur_link_settings.link_rate;
> - cfg->link_settings.link_spread =
> - stream->link->cur_link_settings.link_spread;
> - cfg->sym_clock = stream->phy_pix_clk;
> - /* Round v_refresh*/
> - cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
> - cfg->v_refresh /= stream->timing.h_total;
> - cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
> - / stream->timing.v_total;
> - }
> -
> - pp_display_cfg->display_count = num_cfgs;
> -}
> -
> -static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
> -{
> - uint8_t j;
> - uint32_t min_vertical_blank_time = -1;
> -
> - for (j = 0; j < context->stream_count; j++) {
> - struct dc_stream_state *stream = context->streams[j];
> - uint32_t vertical_blank_in_pixels = 0;
> - uint32_t vertical_blank_time = 0;
> -
> - vertical_blank_in_pixels = stream->timing.h_total *
> - (stream->timing.v_total
> - - stream->timing.v_addressable);
> -
> - vertical_blank_time = vertical_blank_in_pixels
> - * 10000 / stream->timing.pix_clk_100hz;
> -
> - if (min_vertical_blank_time > vertical_blank_time)
> - min_vertical_blank_time = vertical_blank_time;
> - }
> -
> - return min_vertical_blank_time;
> -}
> -
> -static int determine_sclk_from_bounding_box(
> - const struct dc *dc,
> - int required_sclk)
> -{
> - int i;
> -
> - /*
> - * Some asics do not give us sclk levels, so we just report the actual
> - * required sclk
> - */
> - if (dc->sclk_lvls.num_levels == 0)
> - return required_sclk;
> -
> - for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
> - if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
> - return dc->sclk_lvls.clocks_in_khz[i];
> - }
> - /*
> - * even maximum level could not satisfy requirement, this
> - * is unexpected at this stage, should have been caught at
> - * validation time
> - */
> - ASSERT(0);
> - return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
> -}
> -
> -static void dce_pplib_apply_display_requirements(
> - struct dc *dc,
> - struct dc_state *context)
> -{
> - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
> -
> - pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
> -
> - dce110_fill_display_configs(context, pp_display_cfg);
> -
> - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
> -}
> -
> -static void dce11_pplib_apply_display_requirements(
> - struct dc *dc,
> - struct dc_state *context)
> -{
> - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
> -
> - pp_display_cfg->all_displays_in_sync =
> - context->bw_ctx.bw.dce.all_displays_in_sync;
> - pp_display_cfg->nb_pstate_switch_disable =
> - context->bw_ctx.bw.dce.nbp_state_change_enable == false;
> - pp_display_cfg->cpu_cc6_disable =
> - context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
> - pp_display_cfg->cpu_pstate_disable =
> - context->bw_ctx.bw.dce.cpup_state_change_enable == false;
> - pp_display_cfg->cpu_pstate_separation_time =
> - context->bw_ctx.bw.dce.blackout_recovery_time_us;
> -
> - pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
> - / MEMORY_TYPE_MULTIPLIER_CZ;
> -
> - pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
> - dc,
> - context->bw_ctx.bw.dce.sclk_khz);
> -
> - /*
> - * As workaround for >4x4K lightup set dcfclock to min_engine_clock value.
> - * This is not required for less than 5 displays,
> - * thus don't request decfclk in dc to avoid impact
> - * on power saving.
> - *
> - */
> - pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ?
> - pp_display_cfg->min_engine_clock_khz : 0;
> -
> - pp_display_cfg->min_engine_clock_deep_sleep_khz
> - = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
> -
> - pp_display_cfg->avail_mclk_switch_time_us =
> - dce110_get_min_vblank_time_us(context);
> - /* TODO: dce11.2*/
> - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
> -
> - pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz;
> -
> - dce110_fill_display_configs(context, pp_display_cfg);
> -
> - /* TODO: is this still applicable?*/
> - if (pp_display_cfg->display_count == 1) {
> - const struct dc_crtc_timing *timing =
> - &context->streams[0]->timing;
> -
> - pp_display_cfg->crtc_index =
> - pp_display_cfg->disp_configs[0].pipe_idx;
> - pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
> - }
> -
> - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
> -}
> -
> -static void dce_update_clocks(struct clk_mgr *clk_mgr,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct dm_pp_power_level_change_request level_change_req;
> - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> - /*TODO: W/A for dal3 linux, investigate why this works */
> - if (!clk_mgr_dce->dfs_bypass_active)
> - patched_disp_clk = patched_disp_clk * 115 / 100;
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
> - patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk);
> - clk_mgr->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
> -}
> -
> -static void dce11_update_clocks(struct clk_mgr *clk_mgr,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct dm_pp_power_level_change_request level_change_req;
> - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> - /*TODO: W/A for dal3 linux, investigate why this works */
> - if (!clk_mgr_dce->dfs_bypass_active)
> - patched_disp_clk = patched_disp_clk * 115 / 100;
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
> - context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
> - clk_mgr->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
> -}
> -
> -static void dce112_update_clocks(struct clk_mgr *clk_mgr,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct dm_pp_power_level_change_request level_change_req;
> - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> - /*TODO: W/A for dal3 linux, investigate why this works */
> - if (!clk_mgr_dce->dfs_bypass_active)
> - patched_disp_clk = patched_disp_clk * 115 / 100;
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
> - patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk);
> - clk_mgr->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
> -}
> -
> -static void dce12_update_clocks(struct clk_mgr *clk_mgr,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
> - struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
> - int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
> - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
> -
> - /*TODO: W/A for dal3 linux, investigate why this works */
> - if (!clk_mgr_dce->dfs_bypass_active)
> - patched_disp_clk = patched_disp_clk * 115 / 100;
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
> - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
> - /*
> - * When xGMI is enabled, the display clk needs to be adjusted
> - * with the WAFL link's SS percentage.
> - */
> - if (clk_mgr_dce->xgmi_enabled)
> - patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss(
> - clk_mgr_dce, patched_disp_clk);
> - clock_voltage_req.clocks_in_khz = patched_disp_clk;
> - clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk);
> -
> - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
> - }
> -
> - if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) {
> - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
> - clock_voltage_req.clocks_in_khz = max_pix_clk;
> - clk_mgr->clks.phyclk_khz = max_pix_clk;
> -
> - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
> - }
> - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
> -}
> -
> -static const struct clk_mgr_funcs dce120_funcs = {
> - .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
> - .update_clocks = dce12_update_clocks
> -};
> -
> -static const struct clk_mgr_funcs dce112_funcs = {
> - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
> - .update_clocks = dce112_update_clocks
> -};
> -
> -static const struct clk_mgr_funcs dce110_funcs = {
> - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
> - .update_clocks = dce11_update_clocks,
> -};
> -
> -static const struct clk_mgr_funcs dce_funcs = {
> - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
> - .update_clocks = dce_update_clocks
> -};
> -
> -static void dce_clk_mgr_construct(
> - struct dce_clk_mgr *clk_mgr_dce,
> - struct dc_context *ctx,
> - const struct clk_mgr_registers *regs,
> - const struct clk_mgr_shift *clk_shift,
> - const struct clk_mgr_mask *clk_mask)
> -{
> - struct clk_mgr *base = &clk_mgr_dce->base;
> - struct dm_pp_static_clock_info static_clk_info = {0};
> -
> - base->ctx = ctx;
> - base->funcs = &dce_funcs;
> -
> - clk_mgr_dce->regs = regs;
> - clk_mgr_dce->clk_mgr_shift = clk_shift;
> - clk_mgr_dce->clk_mgr_mask = clk_mask;
> -
> - clk_mgr_dce->dfs_bypass_disp_clk = 0;
> -
> - clk_mgr_dce->dprefclk_ss_percentage = 0;
> - clk_mgr_dce->dprefclk_ss_divider = 1000;
> - clk_mgr_dce->ss_on_dprefclk = false;
> -
> -
> - if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> - clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state;
> - else
> - clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> -
> - dce_clock_read_integrated_info(clk_mgr_dce);
> - dce_clock_read_ss_info(clk_mgr_dce);
> -}
> -
> -struct clk_mgr *dce_clk_mgr_create(
> - struct dc_context *ctx,
> - const struct clk_mgr_registers *regs,
> - const struct clk_mgr_shift *clk_shift,
> - const struct clk_mgr_mask *clk_mask)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
> -
> - if (clk_mgr_dce == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> -
> - memcpy(clk_mgr_dce->max_clks_by_state,
> - dce80_max_clks_by_state,
> - sizeof(dce80_max_clks_by_state));
> -
> - dce_clk_mgr_construct(
> - clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
> -
> - return &clk_mgr_dce->base;
> -}
> -
> -struct clk_mgr *dce110_clk_mgr_create(
> - struct dc_context *ctx,
> - const struct clk_mgr_registers *regs,
> - const struct clk_mgr_shift *clk_shift,
> - const struct clk_mgr_mask *clk_mask)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
> -
> - if (clk_mgr_dce == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> -
> - memcpy(clk_mgr_dce->max_clks_by_state,
> - dce110_max_clks_by_state,
> - sizeof(dce110_max_clks_by_state));
> -
> - dce_clk_mgr_construct(
> - clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
> -
> - clk_mgr_dce->base.funcs = &dce110_funcs;
> -
> - return &clk_mgr_dce->base;
> -}
> -
> -struct clk_mgr *dce112_clk_mgr_create(
> - struct dc_context *ctx,
> - const struct clk_mgr_registers *regs,
> - const struct clk_mgr_shift *clk_shift,
> - const struct clk_mgr_mask *clk_mask)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
> -
> - if (clk_mgr_dce == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> -
> - memcpy(clk_mgr_dce->max_clks_by_state,
> - dce112_max_clks_by_state,
> - sizeof(dce112_max_clks_by_state));
> -
> - dce_clk_mgr_construct(
> - clk_mgr_dce, ctx, regs, clk_shift, clk_mask);
> -
> - clk_mgr_dce->base.funcs = &dce112_funcs;
> -
> - return &clk_mgr_dce->base;
> -}
> -
> -struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
> -
> - if (clk_mgr_dce == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> -
> - memcpy(clk_mgr_dce->max_clks_by_state,
> - dce120_max_clks_by_state,
> - sizeof(dce120_max_clks_by_state));
> -
> - dce_clk_mgr_construct(
> - clk_mgr_dce, ctx, NULL, NULL, NULL);
> -
> - clk_mgr_dce->dprefclk_khz = 600000;
> - clk_mgr_dce->base.funcs = &dce120_funcs;
> -
> - return &clk_mgr_dce->base;
> -}
> -
> -struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce),
> - GFP_KERNEL);
> -
> - if (clk_mgr_dce == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> -
> - memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state,
> - sizeof(dce120_max_clks_by_state));
> -
> - dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL);
> -
> - clk_mgr_dce->dprefclk_khz = 625000;
> - clk_mgr_dce->base.funcs = &dce120_funcs;
> -
> - return &clk_mgr_dce->base;
> -}
> -
> -void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr)
> -{
> - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr);
> -
> - kfree(clk_mgr_dce);
> - *clk_mgr = NULL;
> -}
> --
> 2.52.0
>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/5] drm/amd/display: Remove unused dce60_clk_mgr register definitions
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
2026-01-18 17:31 ` [PATCH 1/5] drm/amd/display: Use dce_audio_create for DCE 6 Timur Kristóf
2026-01-18 17:31 ` [PATCH 2/5] drm/amd/display: Delete unused dce_clk_mgr.c Timur Kristóf
@ 2026-01-18 17:31 ` Timur Kristóf
2026-02-03 23:43 ` Rodrigo Siqueira
2026-01-18 17:31 ` [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c Timur Kristóf
` (2 subsequent siblings)
5 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2026-01-18 17:31 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
Cc: Timur Kristóf
It turned out that these were actually not necessary.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 30 ++-----------------
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 11 -------
2 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
index 69dd80d9f738..1fdf344efe1a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
@@ -43,30 +43,6 @@
#include "dce/dce_6_0_d.h"
#include "dce/dce_6_0_sh_mask.h"
-#define REG(reg) \
- (clk_mgr->regs->reg)
-
-#undef FN
-#define FN(reg_name, field_name) \
- clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
-
-/* set register offset */
-#define SR(reg_name)\
- .reg_name = mm ## reg_name
-
-static const struct clk_mgr_registers disp_clk_regs = {
- CLK_COMMON_REG_LIST_DCE60_BASE()
-};
-
-static const struct clk_mgr_shift disp_clk_shift = {
- CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)
-};
-
-static const struct clk_mgr_mask disp_clk_mask = {
- CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)
-};
-
-
/* Max clock values for each state indexed by "enum clocks_state": */
static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
/* ClocksStateInvalid - should not be used */
@@ -155,9 +131,9 @@ void dce60_clk_mgr_construct(
dce60_max_clks_by_state,
sizeof(dce60_max_clks_by_state));
- clk_mgr->regs = &disp_clk_regs;
- clk_mgr->clk_mgr_shift = &disp_clk_shift;
- clk_mgr->clk_mgr_mask = &disp_clk_mask;
+ clk_mgr->regs = NULL;
+ clk_mgr->clk_mgr_shift = NULL;
+ clk_mgr->clk_mgr_mask = NULL;
clk_mgr->base.funcs = &dce60_funcs;
base->clks.max_supported_dispclk_khz =
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index bac8febad69a..836a28134d41 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -89,11 +89,6 @@ enum dentist_divider_range {
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
.DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
-#if defined(CONFIG_DRM_AMD_DC_SI)
-#define CLK_COMMON_REG_LIST_DCE60_BASE() \
- SR(DENTIST_DISPCLK_CNTL)
-#endif
-
#define CLK_COMMON_REG_LIST_DCN_BASE() \
SR(DENTIST_DISPCLK_CNTL)
@@ -119,12 +114,6 @@ enum dentist_divider_range {
CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
-#if defined(CONFIG_DRM_AMD_DC_SI)
-#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
- CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
- CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
-#endif
-
#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 3/5] drm/amd/display: Remove unused dce60_clk_mgr register definitions
2026-01-18 17:31 ` [PATCH 3/5] drm/amd/display: Remove unused dce60_clk_mgr register definitions Timur Kristóf
@ 2026-02-03 23:43 ` Rodrigo Siqueira
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2026-02-03 23:43 UTC (permalink / raw)
To: Timur Kristóf, Alex Hung
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li
On 01/18, Timur Kristóf wrote:
> It turned out that these were actually not necessary.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 30 ++-----------------
> .../amd/display/dc/inc/hw/clk_mgr_internal.h | 11 -------
> 2 files changed, 3 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> index 69dd80d9f738..1fdf344efe1a 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> @@ -43,30 +43,6 @@
> #include "dce/dce_6_0_d.h"
> #include "dce/dce_6_0_sh_mask.h"
>
> -#define REG(reg) \
> - (clk_mgr->regs->reg)
> -
> -#undef FN
> -#define FN(reg_name, field_name) \
> - clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
> -
> -/* set register offset */
> -#define SR(reg_name)\
> - .reg_name = mm ## reg_name
> -
> -static const struct clk_mgr_registers disp_clk_regs = {
> - CLK_COMMON_REG_LIST_DCE60_BASE()
> -};
> -
> -static const struct clk_mgr_shift disp_clk_shift = {
> - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)
> -};
> -
> -static const struct clk_mgr_mask disp_clk_mask = {
> - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)
> -};
> -
> -
> /* Max clock values for each state indexed by "enum clocks_state": */
> static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> /* ClocksStateInvalid - should not be used */
> @@ -155,9 +131,9 @@ void dce60_clk_mgr_construct(
> dce60_max_clks_by_state,
> sizeof(dce60_max_clks_by_state));
>
> - clk_mgr->regs = &disp_clk_regs;
> - clk_mgr->clk_mgr_shift = &disp_clk_shift;
> - clk_mgr->clk_mgr_mask = &disp_clk_mask;
> + clk_mgr->regs = NULL;
> + clk_mgr->clk_mgr_shift = NULL;
> + clk_mgr->clk_mgr_mask = NULL;
After looking into the next commit, I got why you did this change. Maybe
for future patches, expand the commit message and mention that this is a
transition step. Anyway:
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
> clk_mgr->base.funcs = &dce60_funcs;
>
> base->clks.max_supported_dispclk_khz =
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> index bac8febad69a..836a28134d41 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
> @@ -89,11 +89,6 @@ enum dentist_divider_range {
> .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
> .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
>
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -#define CLK_COMMON_REG_LIST_DCE60_BASE() \
> - SR(DENTIST_DISPCLK_CNTL)
> -#endif
> -
> #define CLK_COMMON_REG_LIST_DCN_BASE() \
> SR(DENTIST_DISPCLK_CNTL)
>
> @@ -119,12 +114,6 @@ enum dentist_divider_range {
> CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
> CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
>
> -#if defined(CONFIG_DRM_AMD_DC_SI)
> -#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
> - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
> - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
> -#endif
> -
> #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
> CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
> CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
> --
> 2.52.0
>
--
Rodrigo Siqueira
https://siqueira.tech
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
` (2 preceding siblings ...)
2026-01-18 17:31 ` [PATCH 3/5] drm/amd/display: Remove unused dce60_clk_mgr register definitions Timur Kristóf
@ 2026-01-18 17:31 ` Timur Kristóf
2026-01-30 18:47 ` Alex Hung
` (2 more replies)
2026-01-18 17:31 ` [PATCH 5/5] drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers Timur Kristóf
2026-02-09 15:48 ` [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Rodrigo Siqueira
5 siblings, 3 replies; 19+ messages in thread
From: Timur Kristóf @ 2026-01-18 17:31 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
Cc: Timur Kristóf
dce60_clk_mgr was basically identical to dce_clk_mgr other than
a few minor details. They can be all handled in the same file,
reducing duplicated code and easing the maintenance burden for
old DCE versions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
.../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++--
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------
.../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -----
4 files changed, 52 insertions(+), 202 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 15cf13ec5302..9206eb8b0365 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -34,7 +34,6 @@
#include "dce110/dce110_clk_mgr.h"
#include "dce112/dce112_clk_mgr.h"
#include "dce120/dce120_clk_mgr.h"
-#include "dce60/dce60_clk_mgr.h"
#include "dcn10/rv1_clk_mgr.h"
#include "dcn10/rv2_clk_mgr.h"
#include "dcn20/dcn20_clk_mgr.h"
@@ -150,16 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
switch (asic_id.chip_family) {
#if defined(CONFIG_DRM_AMD_DC_SI)
- case FAMILY_SI: {
- struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
-
- if (clk_mgr == NULL) {
- BREAK_TO_DEBUGGER();
- return NULL;
- }
- dce60_clk_mgr_construct(ctx, clk_mgr);
- return &clk_mgr->base;
- }
+ case FAMILY_SI:
#endif
case FAMILY_CI:
case FAMILY_KV: {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index 6131ede2db7a..d02d03c154b3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
+/* Max clock values for each state indexed by "enum clocks_state": */
+static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
+/* ClocksStateInvalid - should not be used */
+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
+/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
+{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
+/* ClocksStateLow */
+{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
+/* ClocksStateNominal */
+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
+/* ClocksStatePerformance */
+{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
/* Max clock values for each state indexed by "enum clocks_state": */
static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
@@ -126,8 +138,25 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r
return dp_ref_clk_khz;
}
+static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
+{
+ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+ struct dc_context *ctx = clk_mgr_base->ctx;
+ int dp_ref_clk_khz = 0;
+
+ if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
+ dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
+ else
+ dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
+
+ return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
+}
+
int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
{
+ if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4)
+ return dce60_get_dp_ref_freq_khz(clk_mgr_base);
+
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
int dprefclk_wdivider;
int dprefclk_src_sel;
@@ -441,27 +470,37 @@ void dce_clk_mgr_construct(
struct clk_mgr *base = &clk_mgr->base;
struct dm_pp_static_clock_info static_clk_info = {0};
- memcpy(clk_mgr->max_clks_by_state,
- dce80_max_clks_by_state,
- sizeof(dce80_max_clks_by_state));
+ if (ctx->dce_version <= DCE_VERSION_6_4)
+ memcpy(clk_mgr->max_clks_by_state,
+ dce60_max_clks_by_state,
+ sizeof(dce60_max_clks_by_state));
+ else
+ memcpy(clk_mgr->max_clks_by_state,
+ dce80_max_clks_by_state,
+ sizeof(dce80_max_clks_by_state));
+
base->ctx = ctx;
base->funcs = &dce_funcs;
- clk_mgr->regs = &disp_clk_regs;
- clk_mgr->clk_mgr_shift = &disp_clk_shift;
- clk_mgr->clk_mgr_mask = &disp_clk_mask;
- clk_mgr->dfs_bypass_disp_clk = 0;
+ if (ctx->dce_version >= DCE_VERSION_8_0) {
+ clk_mgr->regs = &disp_clk_regs;
+ clk_mgr->clk_mgr_shift = &disp_clk_shift;
+ clk_mgr->clk_mgr_mask = &disp_clk_mask;
+ }
+ clk_mgr->dfs_bypass_disp_clk = 0;
clk_mgr->dprefclk_ss_percentage = 0;
clk_mgr->dprefclk_ss_divider = 1000;
clk_mgr->ss_on_dprefclk = false;
- if (dm_pp_get_static_clocks(ctx, &static_clk_info))
- clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
- else
- clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
- clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
+ if (ctx->dce_version >= DCE_VERSION_8_0) {
+ if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+ clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
+ else
+ clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
+ clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
+ }
base->clks.max_supported_dispclk_khz =
clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
@@ -469,4 +508,3 @@ void dce_clk_mgr_construct(
dce_clock_read_integrated_info(clk_mgr);
dce_clock_read_ss_info(clk_mgr);
}
-
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
deleted file mode 100644
index 1fdf344efe1a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#include "dccg.h"
-#include "clk_mgr_internal.h"
-#include "dce100/dce_clk_mgr.h"
-#include "dce110/dce110_clk_mgr.h"
-#include "dce60_clk_mgr.h"
-#include "reg_helper.h"
-#include "dmcu.h"
-#include "core_types.h"
-#include "dal_asic_id.h"
-
-/*
- * Currently the register shifts and masks in this file are used for dce60
- * which has no DPREFCLK_CNTL register
- * TODO: remove this when DENTIST_DISPCLK_CNTL
- * is moved to dccg, where it belongs
- */
-#include "dce/dce_6_0_d.h"
-#include "dce/dce_6_0_sh_mask.h"
-
-/* Max clock values for each state indexed by "enum clocks_state": */
-static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
-/* ClocksStateInvalid - should not be used */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
-{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
-/* ClocksStateLow */
-{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
-/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
-/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
-
-static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
-{
- struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- struct dc_context *ctx = clk_mgr_base->ctx;
- int dp_ref_clk_khz = 0;
-
- if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
- dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
- else
- dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
-
- return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
-}
-
-static void dce60_pplib_apply_display_requirements(
- struct dc *dc,
- struct dc_state *context)
-{
- struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
-
- dce110_fill_display_configs(context, pp_display_cfg);
-
- if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
- dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
-}
-
-static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
- struct dc_state *context,
- bool safe_to_lower)
-{
- struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
- struct dm_pp_power_level_change_request level_change_req;
- const int max_disp_clk =
- clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
- int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
-
- level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
- /* get max clock state from PPLIB */
- if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
- || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
- if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
- clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
- }
-
- if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
- patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
- clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
- }
- dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
-}
-
-
-
-
-
-
-
-
-static struct clk_mgr_funcs dce60_funcs = {
- .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
- .update_clocks = dce60_update_clocks
-};
-
-void dce60_clk_mgr_construct(
- struct dc_context *ctx,
- struct clk_mgr_internal *clk_mgr)
-{
- struct clk_mgr *base = &clk_mgr->base;
-
- dce_clk_mgr_construct(ctx, clk_mgr);
-
- memcpy(clk_mgr->max_clks_by_state,
- dce60_max_clks_by_state,
- sizeof(dce60_max_clks_by_state));
-
- clk_mgr->regs = NULL;
- clk_mgr->clk_mgr_shift = NULL;
- clk_mgr->clk_mgr_mask = NULL;
- clk_mgr->base.funcs = &dce60_funcs;
-
- base->clks.max_supported_dispclk_khz =
- clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
deleted file mode 100644
index eca3e5168089..000000000000
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_
-#define DAL_DC_DCE_DCE60_CLK_MGR_H_
-
-#include "dc.h"
-
-void dce60_clk_mgr_construct(
- struct dc_context *ctx,
- struct clk_mgr_internal *clk_mgr_dce);
-
-#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-01-18 17:31 ` [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c Timur Kristóf
@ 2026-01-30 18:47 ` Alex Hung
2026-02-03 23:45 ` Rodrigo Siqueira
2026-02-09 17:21 ` Alex Hung
2 siblings, 0 replies; 19+ messages in thread
From: Alex Hung @ 2026-01-30 18:47 UTC (permalink / raw)
To: Timur Kristóf, amd-gfx, Alexander.Deucher, Mario Limonciello,
Ivan Lipski, harry.wentland, Leo Li
On 1/18/26 10:31, Timur Kristóf wrote:
> dce60_clk_mgr was basically identical to dce_clk_mgr other than
> a few minor details. They can be all handled in the same file,
> reducing duplicated code and easing the maintenance burden for
> old DCE versions.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
> .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++--
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -----
> 4 files changed, 52 insertions(+), 202 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index 15cf13ec5302..9206eb8b0365 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -34,7 +34,6 @@
> #include "dce110/dce110_clk_mgr.h"
> #include "dce112/dce112_clk_mgr.h"
> #include "dce120/dce120_clk_mgr.h"
> -#include "dce60/dce60_clk_mgr.h"
> #include "dcn10/rv1_clk_mgr.h"
> #include "dcn10/rv2_clk_mgr.h"
> #include "dcn20/dcn20_clk_mgr.h"
> @@ -150,16 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
>
> switch (asic_id.chip_family) {
> #if defined(CONFIG_DRM_AMD_DC_SI)
The macro can be removed since it doesn't do anything anymore.
> - case FAMILY_SI: {
> - struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
> -
> - if (clk_mgr == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> - dce60_clk_mgr_construct(ctx, clk_mgr);
> - return &clk_mgr->base;
> - }
> + case FAMILY_SI:
> #endif
> case FAMILY_CI:
> case FAMILY_KV: {
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 6131ede2db7a..d02d03c154b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = {
> CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> };
>
> +/* Max clock values for each state indexed by "enum clocks_state": */
> +static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> +/* ClocksStateInvalid - should not be used */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateLow */
> +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> +/* ClocksStateNominal */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +/* ClocksStatePerformance */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
>
> /* Max clock values for each state indexed by "enum clocks_state": */
> static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
> @@ -126,8 +138,25 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r
> return dp_ref_clk_khz;
> }
>
> +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> +{
> + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> + struct dc_context *ctx = clk_mgr_base->ctx;
> + int dp_ref_clk_khz = 0;
> +
> + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> + else
> + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> +
> + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> +}
> +
> int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> {
> + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4)
> + return dce60_get_dp_ref_freq_khz(clk_mgr_base);
> +
This should be moved down after variable declarations
> struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> int dprefclk_wdivider;
> int dprefclk_src_sel;
> @@ -441,27 +470,37 @@ void dce_clk_mgr_construct(
> struct clk_mgr *base = &clk_mgr->base;
> struct dm_pp_static_clock_info static_clk_info = {0};
>
> - memcpy(clk_mgr->max_clks_by_state,
> - dce80_max_clks_by_state,
> - sizeof(dce80_max_clks_by_state));
> + if (ctx->dce_version <= DCE_VERSION_6_4)
> + memcpy(clk_mgr->max_clks_by_state,
> + dce60_max_clks_by_state,
> + sizeof(dce60_max_clks_by_state));
> + else
> + memcpy(clk_mgr->max_clks_by_state,
> + dce80_max_clks_by_state,
> + sizeof(dce80_max_clks_by_state));
> +
>
> base->ctx = ctx;
> base->funcs = &dce_funcs;
>
> - clk_mgr->regs = &disp_clk_regs;
> - clk_mgr->clk_mgr_shift = &disp_clk_shift;
> - clk_mgr->clk_mgr_mask = &disp_clk_mask;
> - clk_mgr->dfs_bypass_disp_clk = 0;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + clk_mgr->regs = &disp_clk_regs;
> + clk_mgr->clk_mgr_shift = &disp_clk_shift;
> + clk_mgr->clk_mgr_mask = &disp_clk_mask;
> + }
>
> + clk_mgr->dfs_bypass_disp_clk = 0;
> clk_mgr->dprefclk_ss_percentage = 0;
> clk_mgr->dprefclk_ss_divider = 1000;
> clk_mgr->ss_on_dprefclk = false;
>
> - if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> - clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> - else
> - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> + clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> + else
> + clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> + clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + }
>
> base->clks.max_supported_dispclk_khz =
> clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> @@ -469,4 +508,3 @@ void dce_clk_mgr_construct(
> dce_clock_read_integrated_info(clk_mgr);
> dce_clock_read_ss_info(clk_mgr);
> }
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> deleted file mode 100644
> index 1fdf344efe1a..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#include "dccg.h"
> -#include "clk_mgr_internal.h"
> -#include "dce100/dce_clk_mgr.h"
> -#include "dce110/dce110_clk_mgr.h"
> -#include "dce60_clk_mgr.h"
> -#include "reg_helper.h"
> -#include "dmcu.h"
> -#include "core_types.h"
> -#include "dal_asic_id.h"
> -
> -/*
> - * Currently the register shifts and masks in this file are used for dce60
> - * which has no DPREFCLK_CNTL register
> - * TODO: remove this when DENTIST_DISPCLK_CNTL
> - * is moved to dccg, where it belongs
> - */
> -#include "dce/dce_6_0_d.h"
> -#include "dce/dce_6_0_sh_mask.h"
> -
> -/* Max clock values for each state indexed by "enum clocks_state": */
> -static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> -/* ClocksStateInvalid - should not be used */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateLow */
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> -/* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> -/* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> -
> -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> -{
> - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dc_context *ctx = clk_mgr_base->ctx;
> - int dp_ref_clk_khz = 0;
> -
> - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> - dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> - else
> - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> -
> - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> -}
> -
> -static void dce60_pplib_apply_display_requirements(
> - struct dc *dc,
> - struct dc_state *context)
> -{
> - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
> -
> - dce110_fill_display_configs(context, pp_display_cfg);
> -
> - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
> -}
> -
> -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dm_pp_power_level_change_request level_change_req;
> - const int max_disp_clk =
> - clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> - int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
> - patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
> - clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
> -}
> -
> -
> -
> -
> -
> -
> -
> -
> -static struct clk_mgr_funcs dce60_funcs = {
> - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
> - .update_clocks = dce60_update_clocks
> -};
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr)
> -{
> - struct clk_mgr *base = &clk_mgr->base;
> -
> - dce_clk_mgr_construct(ctx, clk_mgr);
> -
> - memcpy(clk_mgr->max_clks_by_state,
> - dce60_max_clks_by_state,
> - sizeof(dce60_max_clks_by_state));
> -
> - clk_mgr->regs = NULL;
> - clk_mgr->clk_mgr_shift = NULL;
> - clk_mgr->clk_mgr_mask = NULL;
> - clk_mgr->base.funcs = &dce60_funcs;
> -
> - base->clks.max_supported_dispclk_khz =
> - clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> -}
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> deleted file mode 100644
> index eca3e5168089..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_
> -#define DAL_DC_DCE_DCE60_CLK_MGR_H_
> -
> -#include "dc.h"
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr_dce);
> -
> -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-01-18 17:31 ` [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c Timur Kristóf
2026-01-30 18:47 ` Alex Hung
@ 2026-02-03 23:45 ` Rodrigo Siqueira
2026-02-09 17:21 ` Alex Hung
2 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2026-02-03 23:45 UTC (permalink / raw)
To: Timur Kristóf
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
On 01/18, Timur Kristóf wrote:
> dce60_clk_mgr was basically identical to dce_clk_mgr other than
> a few minor details. They can be all handled in the same file,
> reducing duplicated code and easing the maintenance burden for
> old DCE versions.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
> .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++--
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -----
> 4 files changed, 52 insertions(+), 202 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index 15cf13ec5302..9206eb8b0365 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -34,7 +34,6 @@
> #include "dce110/dce110_clk_mgr.h"
> #include "dce112/dce112_clk_mgr.h"
> #include "dce120/dce120_clk_mgr.h"
> -#include "dce60/dce60_clk_mgr.h"
> #include "dcn10/rv1_clk_mgr.h"
> #include "dcn10/rv2_clk_mgr.h"
> #include "dcn20/dcn20_clk_mgr.h"
> @@ -150,16 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
>
> switch (asic_id.chip_family) {
> #if defined(CONFIG_DRM_AMD_DC_SI)
> - case FAMILY_SI: {
> - struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
> -
> - if (clk_mgr == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> - dce60_clk_mgr_construct(ctx, clk_mgr);
> - return &clk_mgr->base;
> - }
> + case FAMILY_SI:
> #endif
> case FAMILY_CI:
> case FAMILY_KV: {
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 6131ede2db7a..d02d03c154b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = {
> CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> };
>
> +/* Max clock values for each state indexed by "enum clocks_state": */
> +static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> +/* ClocksStateInvalid - should not be used */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateLow */
> +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> +/* ClocksStateNominal */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +/* ClocksStatePerformance */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
>
> /* Max clock values for each state indexed by "enum clocks_state": */
> static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
> @@ -126,8 +138,25 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r
> return dp_ref_clk_khz;
> }
>
> +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> +{
> + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> + struct dc_context *ctx = clk_mgr_base->ctx;
> + int dp_ref_clk_khz = 0;
> +
> + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> + else
> + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> +
> + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> +}
> +
> int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> {
> + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4)
> + return dce60_get_dp_ref_freq_khz(clk_mgr_base);
> +
> struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> int dprefclk_wdivider;
> int dprefclk_src_sel;
> @@ -441,27 +470,37 @@ void dce_clk_mgr_construct(
> struct clk_mgr *base = &clk_mgr->base;
> struct dm_pp_static_clock_info static_clk_info = {0};
>
> - memcpy(clk_mgr->max_clks_by_state,
> - dce80_max_clks_by_state,
> - sizeof(dce80_max_clks_by_state));
> + if (ctx->dce_version <= DCE_VERSION_6_4)
> + memcpy(clk_mgr->max_clks_by_state,
> + dce60_max_clks_by_state,
> + sizeof(dce60_max_clks_by_state));
> + else
> + memcpy(clk_mgr->max_clks_by_state,
> + dce80_max_clks_by_state,
> + sizeof(dce80_max_clks_by_state));
> +
>
> base->ctx = ctx;
> base->funcs = &dce_funcs;
>
> - clk_mgr->regs = &disp_clk_regs;
> - clk_mgr->clk_mgr_shift = &disp_clk_shift;
> - clk_mgr->clk_mgr_mask = &disp_clk_mask;
> - clk_mgr->dfs_bypass_disp_clk = 0;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + clk_mgr->regs = &disp_clk_regs;
> + clk_mgr->clk_mgr_shift = &disp_clk_shift;
> + clk_mgr->clk_mgr_mask = &disp_clk_mask;
> + }
>
> + clk_mgr->dfs_bypass_disp_clk = 0;
> clk_mgr->dprefclk_ss_percentage = 0;
> clk_mgr->dprefclk_ss_divider = 1000;
> clk_mgr->ss_on_dprefclk = false;
>
> - if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> - clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> - else
> - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> + clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> + else
> + clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> + clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + }
>
> base->clks.max_supported_dispclk_khz =
> clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> @@ -469,4 +508,3 @@ void dce_clk_mgr_construct(
> dce_clock_read_integrated_info(clk_mgr);
> dce_clock_read_ss_info(clk_mgr);
> }
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> deleted file mode 100644
> index 1fdf344efe1a..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#include "dccg.h"
> -#include "clk_mgr_internal.h"
> -#include "dce100/dce_clk_mgr.h"
> -#include "dce110/dce110_clk_mgr.h"
> -#include "dce60_clk_mgr.h"
> -#include "reg_helper.h"
> -#include "dmcu.h"
> -#include "core_types.h"
> -#include "dal_asic_id.h"
> -
> -/*
> - * Currently the register shifts and masks in this file are used for dce60
> - * which has no DPREFCLK_CNTL register
> - * TODO: remove this when DENTIST_DISPCLK_CNTL
> - * is moved to dccg, where it belongs
> - */
> -#include "dce/dce_6_0_d.h"
> -#include "dce/dce_6_0_sh_mask.h"
> -
> -/* Max clock values for each state indexed by "enum clocks_state": */
> -static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> -/* ClocksStateInvalid - should not be used */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateLow */
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> -/* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> -/* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> -
> -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> -{
> - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dc_context *ctx = clk_mgr_base->ctx;
> - int dp_ref_clk_khz = 0;
> -
> - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> - dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> - else
> - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> -
> - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> -}
> -
> -static void dce60_pplib_apply_display_requirements(
> - struct dc *dc,
> - struct dc_state *context)
> -{
> - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
> -
> - dce110_fill_display_configs(context, pp_display_cfg);
> -
> - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
> -}
> -
> -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dm_pp_power_level_change_request level_change_req;
> - const int max_disp_clk =
> - clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> - int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
> - patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
> - clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
> -}
> -
> -
> -
> -
> -
> -
> -
> -
> -static struct clk_mgr_funcs dce60_funcs = {
> - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
> - .update_clocks = dce60_update_clocks
> -};
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr)
> -{
> - struct clk_mgr *base = &clk_mgr->base;
> -
> - dce_clk_mgr_construct(ctx, clk_mgr);
> -
> - memcpy(clk_mgr->max_clks_by_state,
> - dce60_max_clks_by_state,
> - sizeof(dce60_max_clks_by_state));
> -
> - clk_mgr->regs = NULL;
> - clk_mgr->clk_mgr_shift = NULL;
> - clk_mgr->clk_mgr_mask = NULL;
> - clk_mgr->base.funcs = &dce60_funcs;
> -
> - base->clks.max_supported_dispclk_khz =
> - clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> -}
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> deleted file mode 100644
> index eca3e5168089..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_
> -#define DAL_DC_DCE_DCE60_CLK_MGR_H_
> -
> -#include "dc.h"
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr_dce);
> -
> -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */
> --
> 2.52.0
>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-01-18 17:31 ` [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c Timur Kristóf
2026-01-30 18:47 ` Alex Hung
2026-02-03 23:45 ` Rodrigo Siqueira
@ 2026-02-09 17:21 ` Alex Hung
2026-02-09 22:11 ` Timur Kristóf
2 siblings, 1 reply; 19+ messages in thread
From: Alex Hung @ 2026-02-09 17:21 UTC (permalink / raw)
To: Timur Kristóf, amd-gfx, Alexander.Deucher, Mario Limonciello,
Ivan Lipski, harry.wentland, Leo Li
Hi Timur,
I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI is
not set, or with the following change to Makefile. Can you check?
diff --git drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 60021671b386..57d492b90986 100644
--- drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -30,17 +30,6 @@ AMD_DAL_CLK_MGR = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR)
-ifdef CONFIG_DRM_AMD_DC_SI
-###############################################################################
-# DCE 60
-###############################################################################
-CLK_MGR_DCE60 = dce60_clk_mgr.o
-
-AMD_DAL_CLK_MGR_DCE60 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60)
-endif
-
###############################################################################
# DCE 100 and DCE8x
###############################################################################
On 1/18/26 10:31, Timur Kristóf wrote:
> dce60_clk_mgr was basically identical to dce_clk_mgr other than
> a few minor details. They can be all handled in the same file,
> reducing duplicated code and easing the maintenance burden for
> old DCE versions.
>
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
> .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++--
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -----
> 4 files changed, 52 insertions(+), 202 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index 15cf13ec5302..9206eb8b0365 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -34,7 +34,6 @@
> #include "dce110/dce110_clk_mgr.h"
> #include "dce112/dce112_clk_mgr.h"
> #include "dce120/dce120_clk_mgr.h"
> -#include "dce60/dce60_clk_mgr.h"
> #include "dcn10/rv1_clk_mgr.h"
> #include "dcn10/rv2_clk_mgr.h"
> #include "dcn20/dcn20_clk_mgr.h"
> @@ -150,16 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
>
> switch (asic_id.chip_family) {
> #if defined(CONFIG_DRM_AMD_DC_SI)
> - case FAMILY_SI: {
> - struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
> -
> - if (clk_mgr == NULL) {
> - BREAK_TO_DEBUGGER();
> - return NULL;
> - }
> - dce60_clk_mgr_construct(ctx, clk_mgr);
> - return &clk_mgr->base;
> - }
> + case FAMILY_SI:
> #endif
> case FAMILY_CI:
> case FAMILY_KV: {
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> index 6131ede2db7a..d02d03c154b3 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = {
> CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> };
>
> +/* Max clock values for each state indexed by "enum clocks_state": */
> +static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> +/* ClocksStateInvalid - should not be used */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> +/* ClocksStateLow */
> +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> +/* ClocksStateNominal */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> +/* ClocksStatePerformance */
> +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
>
> /* Max clock values for each state indexed by "enum clocks_state": */
> static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
> @@ -126,8 +138,25 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r
> return dp_ref_clk_khz;
> }
>
> +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> +{
> + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> + struct dc_context *ctx = clk_mgr_base->ctx;
> + int dp_ref_clk_khz = 0;
> +
> + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> + else
> + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> +
> + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> +}
> +
> int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> {
> + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4)
> + return dce60_get_dp_ref_freq_khz(clk_mgr_base);
> +
> struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> int dprefclk_wdivider;
> int dprefclk_src_sel;
> @@ -441,27 +470,37 @@ void dce_clk_mgr_construct(
> struct clk_mgr *base = &clk_mgr->base;
> struct dm_pp_static_clock_info static_clk_info = {0};
>
> - memcpy(clk_mgr->max_clks_by_state,
> - dce80_max_clks_by_state,
> - sizeof(dce80_max_clks_by_state));
> + if (ctx->dce_version <= DCE_VERSION_6_4)
> + memcpy(clk_mgr->max_clks_by_state,
> + dce60_max_clks_by_state,
> + sizeof(dce60_max_clks_by_state));
> + else
> + memcpy(clk_mgr->max_clks_by_state,
> + dce80_max_clks_by_state,
> + sizeof(dce80_max_clks_by_state));
> +
>
> base->ctx = ctx;
> base->funcs = &dce_funcs;
>
> - clk_mgr->regs = &disp_clk_regs;
> - clk_mgr->clk_mgr_shift = &disp_clk_shift;
> - clk_mgr->clk_mgr_mask = &disp_clk_mask;
> - clk_mgr->dfs_bypass_disp_clk = 0;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + clk_mgr->regs = &disp_clk_regs;
> + clk_mgr->clk_mgr_shift = &disp_clk_shift;
> + clk_mgr->clk_mgr_mask = &disp_clk_mask;
> + }
>
> + clk_mgr->dfs_bypass_disp_clk = 0;
> clk_mgr->dprefclk_ss_percentage = 0;
> clk_mgr->dprefclk_ss_divider = 1000;
> clk_mgr->ss_on_dprefclk = false;
>
> - if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> - clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> - else
> - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + if (ctx->dce_version >= DCE_VERSION_8_0) {
> + if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> + clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
> + else
> + clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> + clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> + }
>
> base->clks.max_supported_dispclk_khz =
> clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> @@ -469,4 +508,3 @@ void dce_clk_mgr_construct(
> dce_clock_read_integrated_info(clk_mgr);
> dce_clock_read_ss_info(clk_mgr);
> }
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> deleted file mode 100644
> index 1fdf344efe1a..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> +++ /dev/null
> @@ -1,142 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#include "dccg.h"
> -#include "clk_mgr_internal.h"
> -#include "dce100/dce_clk_mgr.h"
> -#include "dce110/dce110_clk_mgr.h"
> -#include "dce60_clk_mgr.h"
> -#include "reg_helper.h"
> -#include "dmcu.h"
> -#include "core_types.h"
> -#include "dal_asic_id.h"
> -
> -/*
> - * Currently the register shifts and masks in this file are used for dce60
> - * which has no DPREFCLK_CNTL register
> - * TODO: remove this when DENTIST_DISPCLK_CNTL
> - * is moved to dccg, where it belongs
> - */
> -#include "dce/dce_6_0_d.h"
> -#include "dce/dce_6_0_sh_mask.h"
> -
> -/* Max clock values for each state indexed by "enum clocks_state": */
> -static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> -/* ClocksStateInvalid - should not be used */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> -/* ClocksStateLow */
> -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> -/* ClocksStateNominal */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> -/* ClocksStatePerformance */
> -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> -
> -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> -{
> - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dc_context *ctx = clk_mgr_base->ctx;
> - int dp_ref_clk_khz = 0;
> -
> - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> - dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
> - else
> - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> -
> - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> -}
> -
> -static void dce60_pplib_apply_display_requirements(
> - struct dc *dc,
> - struct dc_state *context)
> -{
> - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
> -
> - dce110_fill_display_configs(context, pp_display_cfg);
> -
> - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
> - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
> -}
> -
> -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
> - struct dc_state *context,
> - bool safe_to_lower)
> -{
> - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
> - struct dm_pp_power_level_change_request level_change_req;
> - const int max_disp_clk =
> - clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> - int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
> -
> - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
> - /* get max clock state from PPLIB */
> - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
> - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
> - if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
> - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
> - }
> -
> - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
> - patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);
> - clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
> - }
> - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
> -}
> -
> -
> -
> -
> -
> -
> -
> -
> -static struct clk_mgr_funcs dce60_funcs = {
> - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
> - .update_clocks = dce60_update_clocks
> -};
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr)
> -{
> - struct clk_mgr *base = &clk_mgr->base;
> -
> - dce_clk_mgr_construct(ctx, clk_mgr);
> -
> - memcpy(clk_mgr->max_clks_by_state,
> - dce60_max_clks_by_state,
> - sizeof(dce60_max_clks_by_state));
> -
> - clk_mgr->regs = NULL;
> - clk_mgr->clk_mgr_shift = NULL;
> - clk_mgr->clk_mgr_mask = NULL;
> - clk_mgr->base.funcs = &dce60_funcs;
> -
> - base->clks.max_supported_dispclk_khz =
> - clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
> -}
> -
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> deleted file mode 100644
> index eca3e5168089..000000000000
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> +++ /dev/null
> @@ -1,36 +0,0 @@
> -/*
> - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the "Software"),
> - * to deal in the Software without restriction, including without limitation
> - * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> - * and/or sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - *
> - * Authors: AMD
> - *
> - */
> -
> -
> -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_
> -#define DAL_DC_DCE_DCE60_CLK_MGR_H_
> -
> -#include "dc.h"
> -
> -void dce60_clk_mgr_construct(
> - struct dc_context *ctx,
> - struct clk_mgr_internal *clk_mgr_dce);
> -
> -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-02-09 17:21 ` Alex Hung
@ 2026-02-09 22:11 ` Timur Kristóf
2026-02-15 5:06 ` Alex Hung
0 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2026-02-09 22:11 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
On Monday, February 9, 2026 6:21:38 PM Central European Standard Time Alex
Hung wrote:
> Hi Timur,
>
> I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI is
> not set, or with the following change to Makefile. Can you check?
Hi Alex,
I didn't see any problem when I submitted the patch, but it's possible that I
overlooked something. I will fix it in the second version.
Thanks,
Timur
>
> diff --git drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> index 60021671b386..57d492b90986 100644
> --- drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> +++ drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> @@ -30,17 +30,6 @@ AMD_DAL_CLK_MGR = $(addprefix
> $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR))
> AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR)
>
>
> -ifdef CONFIG_DRM_AMD_DC_SI
> -###########################################################################
> #### -# DCE 60
> -###########################################################################
> #### -CLK_MGR_DCE60 = dce60_clk_mgr.o
> -
> -AMD_DAL_CLK_MGR_DCE60 = $(addprefix
> $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60))
> -
> -AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60)
> -endif
> -
>
> ###########################################################################
> #### # DCE 100 and DCE8x
>
> ###########################################################################
> ####
> On 1/18/26 10:31, Timur Kristóf wrote:
> > dce60_clk_mgr was basically identical to dce_clk_mgr other than
> > a few minor details. They can be all handled in the same file,
> > reducing duplicated code and easing the maintenance burden for
> > old DCE versions.
> >
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > ---
> >
> > .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
> > .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 ++++++--
> > .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 142 ------------------
> > .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -----
> > 4 files changed, 52 insertions(+), 202 deletions(-)
> > delete mode 100644
> > drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c delete
> > mode 100644
> > drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h>
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index
> > 15cf13ec5302..9206eb8b0365 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> > @@ -34,7 +34,6 @@
> >
> > #include "dce110/dce110_clk_mgr.h"
> > #include "dce112/dce112_clk_mgr.h"
> > #include "dce120/dce120_clk_mgr.h"
> >
> > -#include "dce60/dce60_clk_mgr.h"
> >
> > #include "dcn10/rv1_clk_mgr.h"
> > #include "dcn10/rv2_clk_mgr.h"
> > #include "dcn20/dcn20_clk_mgr.h"
> >
> > @@ -150,16 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context
> > *ctx, struct pp_smu_funcs *p>
> > switch (asic_id.chip_family) {
> >
> > #if defined(CONFIG_DRM_AMD_DC_SI)
> >
> > - case FAMILY_SI: {
> > - struct clk_mgr_internal *clk_mgr =
kzalloc(sizeof(*clk_mgr),
> > GFP_KERNEL); -
> > - if (clk_mgr == NULL) {
> > - BREAK_TO_DEBUGGER();
> > - return NULL;
> > - }
> > - dce60_clk_mgr_construct(ctx, clk_mgr);
> > - return &clk_mgr->base;
> > - }
> >
> > + case FAMILY_SI:
> > #endif
> >
> > case FAMILY_CI:
> > case FAMILY_KV: {
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index
> > 6131ede2db7a..d02d03c154b3 100644
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
> > @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = {
> >
> > CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
> >
> > };
> >
> > +/* Max clock values for each state indexed by "enum clocks_state": */
> > +static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> > +/* ClocksStateInvalid - should not be used */
> > +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> > +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> > +{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> > +/* ClocksStateLow */
> > +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> > +/* ClocksStateNominal */
> > +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> > +/* ClocksStatePerformance */
> > +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> >
> > /* Max clock values for each state indexed by "enum clocks_state": */
> > static const struct state_dependent_clocks dce80_max_clks_by_state[] = {
> >
> > @@ -126,8 +138,25 @@ int dce_adjust_dp_ref_freq_for_ss(struct
> > clk_mgr_internal *clk_mgr_dce, int dp_r>
> > return dp_ref_clk_khz;
> >
> > }
> >
> > +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> > +{
> > + struct clk_mgr_internal *clk_mgr =
TO_CLK_MGR_INTERNAL(clk_mgr_base);
> > + struct dc_context *ctx = clk_mgr_base->ctx;
> > + int dp_ref_clk_khz = 0;
> > +
> > + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> > + dp_ref_clk_khz =
> > ctx->dc_bios->fw_info.default_display_engine_pll_frequency; + else
> > + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> > +
> > + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> > +}
> > +
> >
> > int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> > {
> >
> > + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4)
> > + return dce60_get_dp_ref_freq_khz(clk_mgr_base);
> > +
> >
> > struct clk_mgr_internal *clk_mgr =
TO_CLK_MGR_INTERNAL(clk_mgr_base);
> > int dprefclk_wdivider;
> > int dprefclk_src_sel;
> >
> > @@ -441,27 +470,37 @@ void dce_clk_mgr_construct(
> >
> > struct clk_mgr *base = &clk_mgr->base;
> > struct dm_pp_static_clock_info static_clk_info = {0};
> >
> > - memcpy(clk_mgr->max_clks_by_state,
> > - dce80_max_clks_by_state,
> > - sizeof(dce80_max_clks_by_state));
> > + if (ctx->dce_version <= DCE_VERSION_6_4)
> > + memcpy(clk_mgr->max_clks_by_state,
> > + dce60_max_clks_by_state,
> > + sizeof(dce60_max_clks_by_state));
> > + else
> > + memcpy(clk_mgr->max_clks_by_state,
> > + dce80_max_clks_by_state,
> > + sizeof(dce80_max_clks_by_state));
> > +
> >
> > base->ctx = ctx;
> > base->funcs = &dce_funcs;
> >
> > - clk_mgr->regs = &disp_clk_regs;
> > - clk_mgr->clk_mgr_shift = &disp_clk_shift;
> > - clk_mgr->clk_mgr_mask = &disp_clk_mask;
> > - clk_mgr->dfs_bypass_disp_clk = 0;
> > + if (ctx->dce_version >= DCE_VERSION_8_0) {
> > + clk_mgr->regs = &disp_clk_regs;
> > + clk_mgr->clk_mgr_shift = &disp_clk_shift;
> > + clk_mgr->clk_mgr_mask = &disp_clk_mask;
> > + }
> >
> > + clk_mgr->dfs_bypass_disp_clk = 0;
> >
> > clk_mgr->dprefclk_ss_percentage = 0;
> > clk_mgr->dprefclk_ss_divider = 1000;
> > clk_mgr->ss_on_dprefclk = false;
> >
> > - if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> > - clk_mgr->max_clks_state =
static_clk_info.max_clocks_state;
> > - else
> > - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
> > - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
> > + if (ctx->dce_version >= DCE_VERSION_8_0) {
> > + if (dm_pp_get_static_clocks(ctx, &static_clk_info))
> > + clk_mgr->max_clks_state =
static_clk_info.max_clocks_state;
> > + else
> > + clk_mgr->max_clks_state =
DM_PP_CLOCKS_STATE_NOMINAL;
> > + clk_mgr->cur_min_clks_state =
DM_PP_CLOCKS_STATE_INVALID;
> > + }
> >
> > base->clks.max_supported_dispclk_khz =
> >
> > clk_mgr-
>max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk
> > _khz;
> >
> > @@ -469,4 +508,3 @@ void dce_clk_mgr_construct(
> >
> > dce_clock_read_integrated_info(clk_mgr);
> > dce_clock_read_ss_info(clk_mgr);
> >
> > }
> >
> > -
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c deleted
> > file mode 100644
> > index 1fdf344efe1a..000000000000
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> > +++ /dev/null
> > @@ -1,142 +0,0 @@
> > -/*
> > - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> > - *
> > - * Permission is hereby granted, free of charge, to any person obtaining
> > a
> > - * copy of this software and associated documentation files (the
> > "Software"), - * to deal in the Software without restriction, including
> > without limitation - * the rights to use, copy, modify, merge, publish,
> > distribute, sublicense, - * and/or sell copies of the Software, and to
> > permit persons to whom the - * Software is furnished to do so, subject to
> > the following conditions: - *
> > - * The above copyright notice and this permission notice shall be
> > included in - * all copies or substantial portions of the Software.
> > - *
> > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND
> > NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR
> > AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY,
> > WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM,
> > OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER
> > DEALINGS IN THE SOFTWARE.
> > - *
> > - * Authors: AMD
> > - *
> > - */
> > -
> > -
> > -#include "dccg.h"
> > -#include "clk_mgr_internal.h"
> > -#include "dce100/dce_clk_mgr.h"
> > -#include "dce110/dce110_clk_mgr.h"
> > -#include "dce60_clk_mgr.h"
> > -#include "reg_helper.h"
> > -#include "dmcu.h"
> > -#include "core_types.h"
> > -#include "dal_asic_id.h"
> > -
> > -/*
> > - * Currently the register shifts and masks in this file are used for
> > dce60
> > - * which has no DPREFCLK_CNTL register
> > - * TODO: remove this when DENTIST_DISPCLK_CNTL
> > - * is moved to dccg, where it belongs
> > - */
> > -#include "dce/dce_6_0_d.h"
> > -#include "dce/dce_6_0_sh_mask.h"
> > -
> > -/* Max clock values for each state indexed by "enum clocks_state": */
> > -static const struct state_dependent_clocks dce60_max_clks_by_state[] = {
> > -/* ClocksStateInvalid - should not be used */
> > -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> > -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
> > -{ .display_clk_khz = 0, .pixel_clk_khz = 0 },
> > -/* ClocksStateLow */
> > -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
> > -/* ClocksStateNominal */
> > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
> > -/* ClocksStatePerformance */
> > -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
> > -
> > -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
> > -{
> > - struct clk_mgr_internal *clk_mgr =
TO_CLK_MGR_INTERNAL(clk_mgr_base);
> > - struct dc_context *ctx = clk_mgr_base->ctx;
> > - int dp_ref_clk_khz = 0;
> > -
> > - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
> > - dp_ref_clk_khz =
> > ctx->dc_bios->fw_info.default_display_engine_pll_frequency; - else
> > - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
> > -
> > - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
> > -}
> > -
> > -static void dce60_pplib_apply_display_requirements(
> > - struct dc *dc,
> > - struct dc_state *context)
> > -{
> > - struct dm_pp_display_configuration *pp_display_cfg =
> > &context->pp_display_cfg; -
> > - dce110_fill_display_configs(context, pp_display_cfg);
> > -
> > - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg,
> > sizeof(*pp_display_cfg)) != 0)
> > - dm_pp_apply_display_requirements(dc->ctx,
pp_display_cfg);
> > -}
> > -
> > -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,
> > - struct dc_state *context,
> > - bool safe_to_lower)
> > -{
> > - struct clk_mgr_internal *clk_mgr_dce =
> > TO_CLK_MGR_INTERNAL(clk_mgr_base);
> > - struct dm_pp_power_level_change_request level_change_req;
> > - const int max_disp_clk =
> > - clk_mgr_dce-
>max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_
> > clk_khz; - int patched_disp_clk = MIN(max_disp_clk,
> > context->bw_ctx.bw.dce.dispclk_khz); -
> > - level_change_req.power_level =
> > dce_get_required_clocks_state(clk_mgr_base, context); - /* get max
clock
> > state from PPLIB */
> > - if ((level_change_req.power_level < clk_mgr_dce-
>cur_min_clks_state &&
> > safe_to_lower) - ||
level_change_req.power_level >
> > clk_mgr_dce->cur_min_clks_state) { - if
> > (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx,
> > &level_change_req)) - clk_mgr_dce-
>cur_min_clks_state =
> > level_change_req.power_level; - }
> > -
> > - if (should_set_clock(safe_to_lower, patched_disp_clk,
> > clk_mgr_base->clks.dispclk_khz)) { - patched_disp_clk =
> > dce_set_clock(clk_mgr_base, patched_disp_clk);
> > - clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
> > - }
> > - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc,
context);
> > -}
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -
> > -static struct clk_mgr_funcs dce60_funcs = {
> > - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,
> > - .update_clocks = dce60_update_clocks
> > -};
> > -
> > -void dce60_clk_mgr_construct(
> > - struct dc_context *ctx,
> > - struct clk_mgr_internal *clk_mgr)
> > -{
> > - struct clk_mgr *base = &clk_mgr->base;
> > -
> > - dce_clk_mgr_construct(ctx, clk_mgr);
> > -
> > - memcpy(clk_mgr->max_clks_by_state,
> > - dce60_max_clks_by_state,
> > - sizeof(dce60_max_clks_by_state));
> > -
> > - clk_mgr->regs = NULL;
> > - clk_mgr->clk_mgr_shift = NULL;
> > - clk_mgr->clk_mgr_mask = NULL;
> > - clk_mgr->base.funcs = &dce60_funcs;
> > -
> > - base->clks.max_supported_dispclk_khz =
> > - clk_mgr-
>max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_
> > khz; -}
> > -
> > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h deleted
> > file mode 100644
> > index eca3e5168089..000000000000
> > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> > +++ /dev/null
> > @@ -1,36 +0,0 @@
> > -/*
> > - * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
> > - *
> > - * Permission is hereby granted, free of charge, to any person obtaining
> > a
> > - * copy of this software and associated documentation files (the
> > "Software"), - * to deal in the Software without restriction, including
> > without limitation - * the rights to use, copy, modify, merge, publish,
> > distribute, sublicense, - * and/or sell copies of the Software, and to
> > permit persons to whom the - * Software is furnished to do so, subject to
> > the following conditions: - *
> > - * The above copyright notice and this permission notice shall be
> > included in - * all copies or substantial portions of the Software.
> > - *
> > - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND
> > NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR
> > AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY,
> > WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM,
> > OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER
> > DEALINGS IN THE SOFTWARE.
> > - *
> > - * Authors: AMD
> > - *
> > - */
> > -
> > -
> > -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_
> > -#define DAL_DC_DCE_DCE60_CLK_MGR_H_
> > -
> > -#include "dc.h"
> > -
> > -void dce60_clk_mgr_construct(
> > - struct dc_context *ctx,
> > - struct clk_mgr_internal *clk_mgr_dce);
> > -
> > -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-02-09 22:11 ` Timur Kristóf
@ 2026-02-15 5:06 ` Alex Hung
2026-02-16 15:19 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Alex Hung @ 2026-02-15 5:06 UTC (permalink / raw)
To: Timur Kristóf, amd-gfx, Alexander.Deucher, Mario Limonciello,
Ivan Lipski, harry.wentland, Leo Li
On 2/9/26 15:11, Timur Kristóf wrote:
> On Monday, February 9, 2026 6:21:38 PM Central European Standard Time Alex
> Hung wrote:
>> Hi Timur,
>>
>> I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI is
>> not set, or with the following change to Makefile. Can you check?
> Hi Alex,
>
> I didn't see any problem when I submitted the patch, but it's possible that I
> overlooked something. I will fix it in the second version.
>
> Thanks,
> Timur
I can fix them them manually.
This series is Reviewed-by: Alex Hung <alex.hung@amd.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-02-15 5:06 ` Alex Hung
@ 2026-02-16 15:19 ` Timur Kristóf
2026-02-16 17:49 ` Alex Hung
0 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2026-02-16 15:19 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
On 2026. február 15., vasárnap 6:06:33 közép-európai téli idő Alex Hung wrote:
> On 2/9/26 15:11, Timur Kristóf wrote:
> > On Monday, February 9, 2026 6:21:38 PM Central European Standard Time Alex
> >
> > Hung wrote:
> >> Hi Timur,
> >>
> >> I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI is
> >> not set, or with the following change to Makefile. Can you check?
> >
> > Hi Alex,
> >
> > I didn't see any problem when I submitted the patch, but it's possible
> > that I overlooked something. I will fix it in the second version.
> >
> > Thanks,
> > Timur
>
> I can fix them them manually.
>
> This series is Reviewed-by: Alex Hung <alex.hung@amd.com>
Thank you Alex.
I will send a second version of this series where I fix this and the other
feedback that I received.
Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-02-16 15:19 ` Timur Kristóf
@ 2026-02-16 17:49 ` Alex Hung
2026-02-16 18:22 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Alex Hung @ 2026-02-16 17:49 UTC (permalink / raw)
To: Timur Kristóf, amd-gfx, Alexander.Deucher, Mario Limonciello,
Ivan Lipski, harry.wentland, Leo Li
On 2/16/26 08:19, Timur Kristóf wrote:
> On 2026. február 15., vasárnap 6:06:33 közép-európai téli idő Alex Hung wrote:
>> On 2/9/26 15:11, Timur Kristóf wrote:
>>> On Monday, February 9, 2026 6:21:38 PM Central European Standard Time Alex
>>>
>>> Hung wrote:
>>>> Hi Timur,
>>>>
>>>> I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI is
>>>> not set, or with the following change to Makefile. Can you check?
>>>
>>> Hi Alex,
>>>
>>> I didn't see any problem when I submitted the patch, but it's possible
>>> that I overlooked something. I will fix it in the second version.
>>>
>>> Thanks,
>>> Timur
>>
>> I can fix them them manually.
>>
>> This series is Reviewed-by: Alex Hung <alex.hung@amd.com>
>
> Thank you Alex.
>
> I will send a second version of this series where I fix this and the other
> feedback that I received.
I pushed this series to amd-staging-drm-next and you can send a new series.
>
> Timur
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
2026-02-16 17:49 ` Alex Hung
@ 2026-02-16 18:22 ` Timur Kristóf
0 siblings, 0 replies; 19+ messages in thread
From: Timur Kristóf @ 2026-02-16 18:22 UTC (permalink / raw)
To: Alex Hung
Cc: amd-gfx list, Deucher, Alexander, Mario Limonciello, Ivan Lipski,
Harry Wentland, Leo Li
[-- Attachment #1: Type: text/plain, Size: 1354 bytes --]
Alex Hung <alex.hung@amd.com> ezt írta (időpont: 2026. febr. 16., Hét
18:49):
>
>
> On 2/16/26 08:19, Timur Kristóf wrote:
> > On 2026. február 15., vasárnap 6:06:33 közép-európai téli idő Alex Hung
> wrote:
> >> On 2/9/26 15:11, Timur Kristóf wrote:
> >>> On Monday, February 9, 2026 6:21:38 PM Central European Standard Time
> Alex
> >>>
> >>> Hung wrote:
> >>>> Hi Timur,
> >>>>
> >>>> I just found this patch won't build unless that CONFIG_DRM_AMD_DC_SI
> is
> >>>> not set, or with the following change to Makefile. Can you check?
> >>>
> >>> Hi Alex,
> >>>
> >>> I didn't see any problem when I submitted the patch, but it's possible
> >>> that I overlooked something. I will fix it in the second version.
> >>>
> >>> Thanks,
> >>> Timur
> >>
> >> I can fix them them manually.
> >>
> >> This series is Reviewed-by: Alex Hung <alex.hung@amd.com>
> >
> > Thank you Alex.
> >
> > I will send a second version of this series where I fix this and the
> other
> > feedback that I received.
>
> I pushed this series to amd-staging-drm-next and you can send a new series.
>
Hi Alex,
I would strongly prefer to have the other series "drm/amd/display: Fix and
cleanup analog encoders" merged before this one in order to make it easier
to backport that one.
> >
> > Timur
> >
> >
>
>
[-- Attachment #2: Type: text/html, Size: 2347 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 5/5] drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
` (3 preceding siblings ...)
2026-01-18 17:31 ` [PATCH 4/5] drm/amd/display: Handle DCE 6 in dce_clk_mgr.c Timur Kristóf
@ 2026-01-18 17:31 ` Timur Kristóf
2026-02-09 15:48 ` [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Rodrigo Siqueira
5 siblings, 0 replies; 19+ messages in thread
From: Timur Kristóf @ 2026-01-18 17:31 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Alex Hung
Cc: Timur Kristóf
The dce60_register_irq_handlers function was basically identical
to dce110_register_irq_handlers. They can use the same function,
reducing duplicated code and easing the maintenance burden for
old DCE versions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 ++++--------------
1 file changed, 35 insertions(+), 130 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 655c9fcb078a..ca6aea1b0e35 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4354,105 +4354,6 @@ static int register_hpd_handlers(struct amdgpu_device *adev)
return 0;
}
-#if defined(CONFIG_DRM_AMD_DC_SI)
-/* Register IRQ sources and initialize IRQ callbacks */
-static int dce60_register_irq_handlers(struct amdgpu_device *adev)
-{
- struct dc *dc = adev->dm.dc;
- struct common_irq_params *c_irq_params;
- struct dc_interrupt_params int_params = {0};
- int r;
- int i;
- unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
-
- int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
- int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
-
- /*
- * Actions of amdgpu_irq_add_id():
- * 1. Register a set() function with base driver.
- * Base driver will call set() function to enable/disable an
- * interrupt in DC hardware.
- * 2. Register amdgpu_dm_irq_handler().
- * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
- * coming from DC hardware.
- * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
- * for acknowledging and handling.
- */
-
- /* Use VBLANK interrupt */
- for (i = 0; i < adev->mode_info.num_crtc; i++) {
- r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
- if (r) {
- drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");
- return r;
- }
-
- int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
- int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i + 1, 0);
-
- if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
- int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||
- int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) {
- drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n");
- return -EINVAL;
- }
-
- c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
-
- c_irq_params->adev = adev;
- c_irq_params->irq_src = int_params.irq_source;
-
- if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
- dm_crtc_high_irq, c_irq_params))
- return -ENOMEM;
- }
-
- /* Use GRPH_PFLIP interrupt */
- for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
- i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
- r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
- if (r) {
- drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n");
- return r;
- }
-
- int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
- int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i, 0);
-
- if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
- int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST ||
- int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) {
- drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n");
- return -EINVAL;
- }
-
- c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
-
- c_irq_params->adev = adev;
- c_irq_params->irq_src = int_params.irq_source;
-
- if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
- dm_pflip_high_irq, c_irq_params))
- return -ENOMEM;
- }
-
- /* HPD */
- r = amdgpu_irq_add_id(adev, client_id,
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
- if (r) {
- drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n");
- return r;
- }
-
- r = register_hpd_handlers(adev);
-
- return r;
-}
-#endif
-
/* Register IRQ sources and initialize IRQ callbacks */
static int dce110_register_irq_handlers(struct amdgpu_device *adev)
{
@@ -4461,7 +4362,12 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
struct dc_interrupt_params int_params = {0};
int r;
int i;
+ unsigned int src_id;
unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
+ /* Use different interrupts for VBLANK on DCE 6 vs. newer. */
+ const unsigned int vblank_d1 =
+ adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0
+ ? VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 : 1;
if (adev->family >= AMDGPU_FAMILY_AI)
client_id = SOC15_IH_CLIENTID_DCE;
@@ -4482,8 +4388,9 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
*/
/* Use VBLANK interrupt */
- for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
- r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ src_id = vblank_d1 + i;
+ r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->crtc_irq);
if (r) {
drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n");
return r;
@@ -4491,7 +4398,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i, 0);
+ dc_interrupt_to_irq_source(dc, src_id, 0);
if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 ||
@@ -4510,33 +4417,36 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
return -ENOMEM;
}
- /* Use VUPDATE interrupt */
- for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
- r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
- if (r) {
- drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");
- return r;
- }
-
- int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
- int_params.irq_source =
- dc_interrupt_to_irq_source(dc, i, 0);
+ if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+ /* Use VUPDATE interrupt */
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+ src_id = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT + i * 2;
+ r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->vupdate_irq);
+ if (r) {
+ drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n");
+ return r;
+ }
- if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
- int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||
- int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {
- drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");
- return -EINVAL;
- }
+ int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
+ int_params.irq_source =
+ dc_interrupt_to_irq_source(dc, src_id, 0);
- c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
+ if (int_params.irq_source == DC_IRQ_SOURCE_INVALID ||
+ int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 ||
+ int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) {
+ drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n");
+ return -EINVAL;
+ }
- c_irq_params->adev = adev;
- c_irq_params->irq_src = int_params.irq_source;
+ c_irq_params = &adev->dm.vupdate_params[
+ int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
+ c_irq_params->adev = adev;
+ c_irq_params->irq_src = int_params.irq_source;
- if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
- dm_vupdate_high_irq, c_irq_params))
- return -ENOMEM;
+ if (!amdgpu_dm_irq_register_interrupt(adev, &int_params,
+ dm_vupdate_high_irq, c_irq_params))
+ return -ENOMEM;
+ }
}
/* Use GRPH_PFLIP interrupt */
@@ -5660,11 +5570,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
- if (dce60_register_irq_handlers(dm->adev)) {
- drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n");
- goto fail;
- }
- break;
#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
--
2.52.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code
2026-01-18 17:31 [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Timur Kristóf
` (4 preceding siblings ...)
2026-01-18 17:31 ` [PATCH 5/5] drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers Timur Kristóf
@ 2026-02-09 15:48 ` Rodrigo Siqueira
2026-02-09 17:25 ` Alex Hung
5 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Siqueira @ 2026-02-09 15:48 UTC (permalink / raw)
To: Alex Hung, ChiaHsuan Chung (Tom), Daniel Wheeler
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Timur Kristóf
On 01/18, Timur Kristóf wrote:
> Reduce code duplication and ease maintenance burden for old
> DCE versions. Clean up some code that was duplicated between
> DCE 6 and the rest of DCE.
>
> Timur Kristóf (5):
> drm/amd/display: Use dce_audio_create for DCE 6
> drm/amd/display: Delete unused dce_clk_mgr.c
> drm/amd/display: Remove unused dce60_clk_mgr register definitions
> drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
> drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers
>
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 +--
> .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
> .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 +-
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 166 ---
> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -
> .../gpu/drm/amd/display/dc/dce/dce_audio.c | 131 ---
> .../gpu/drm/amd/display/dc/dce/dce_audio.h | 9 -
> .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 967 ------------------
> .../amd/display/dc/inc/hw/clk_mgr_internal.h | 11 -
> .../dc/resource/dce60/dce60_resource.c | 2 +-
> 10 files changed, 88 insertions(+), 1475 deletions(-)
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
> delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
>
> --
> 2.52.0
>
I Alex, Dan, Tom,
Could you also include this series in this weekly promotion? Overall, it
looks good, but I believe the last patch needs thorough testing via
promotion since it can affect multiple GPUs.
Thanks
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code
2026-02-09 15:48 ` [PATCH 0/5] drm/amd/display: Clean up some DCE 6 code Rodrigo Siqueira
@ 2026-02-09 17:25 ` Alex Hung
0 siblings, 0 replies; 19+ messages in thread
From: Alex Hung @ 2026-02-09 17:25 UTC (permalink / raw)
To: Rodrigo Siqueira, ChiaHsuan Chung (Tom), Daniel Wheeler
Cc: amd-gfx, Alexander.Deucher, Mario Limonciello, Ivan Lipski,
harry.wentland, Leo Li, Timur Kristóf
On 2/9/26 08:48, Rodrigo Siqueira wrote:
> On 01/18, Timur Kristóf wrote:
>> Reduce code duplication and ease maintenance burden for old
>> DCE versions. Clean up some code that was duplicated between
>> DCE 6 and the rest of DCE.
>>
>> Timur Kristóf (5):
>> drm/amd/display: Use dce_audio_create for DCE 6
>> drm/amd/display: Delete unused dce_clk_mgr.c
>> drm/amd/display: Remove unused dce60_clk_mgr register definitions
>> drm/amd/display: Handle DCE 6 in dce_clk_mgr.c
>> drm/amd/display: Handle DCE 6 in dce110_register_irq_handlers
>>
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 +--
>> .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 12 +-
>> .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 64 +-
>> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 166 ---
>> .../display/dc/clk_mgr/dce60/dce60_clk_mgr.h | 36 -
>> .../gpu/drm/amd/display/dc/dce/dce_audio.c | 131 ---
>> .../gpu/drm/amd/display/dc/dce/dce_audio.h | 9 -
>> .../gpu/drm/amd/display/dc/dce/dce_clk_mgr.c | 967 ------------------
>> .../amd/display/dc/inc/hw/clk_mgr_internal.h | 11 -
>> .../dc/resource/dce60/dce60_resource.c | 2 +-
>> 10 files changed, 88 insertions(+), 1475 deletions(-)
>> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
>> delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h
>> delete mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
>>
>> --
>> 2.52.0
>>
>
> I Alex, Dan, Tom,
>
> Could you also include this series in this weekly promotion? Overall, it
> looks good, but I believe the last patch needs thorough testing via
> promotion since it can affect multiple GPUs.
>
> Thanks
>
This patchset was included in promotion test last week and no issues
were found.
However, I just realized patch 4 won't build without modifying a
Makefile (see my reply to Patch 4). I'd suggest to address all comments
to patch 4 in V2.
^ permalink raw reply [flat|nested] 19+ messages in thread