From: "Timur Kristóf" <timur.kristof@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
Alex Deucher <alexander.deucher@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu/pm: add missing revision check for CI
Date: Tue, 28 Apr 2026 12:20:46 +0200 [thread overview]
Message-ID: <3692901.dWV9SEqChM@timur-hyperion> (raw)
In-Reply-To: <20260427173103.1020723-1-alexander.deucher@amd.com>
Hi Alex,
On Monday, April 27, 2026 7:31:02 PM Central European Summer Time Alex Deucher
wrote:
> The ci_populate_all_memory_levels() workaround only
> applies to revision 0 SKUs.
This makes good sense. Looking at issue 1816, seems that the affected GPU is
revision 80, and looking at my Hawaii card, it seems to be also 80:
01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/
ATI] Hawaii XT / Grenada XT [Radeon R9 290X/390X] [1002:67b0] (rev 80) (prog-
if 00 [VGA controller])
Can you please add a few tags for additional context?
Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816
Fixes: 9f4b35411cfe ("drm/amd/powerplay: add CI asics support to smumgr (v3)")
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
> b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c index
> 69d8b05ef2457..6e89a032e3dcf 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
> @@ -1333,8 +1333,9 @@ static int ci_populate_all_memory_levels(struct
> pp_hwmgr *hwmgr)
>
> dev_id = adev->pdev->device;
>
> - if ((dpm_table->mclk_table.count >= 2)
> - && ((dev_id == 0x67B0) || (dev_id == 0x67B1))) {
> + if ((dpm_table->mclk_table.count >= 2) &&
> + ((dev_id == 0x67B0) || (dev_id == 0x67B1)) &&
> + (adev->pdev->revision == 0)) {
> smu_data->smc_state_table.MemoryLevel[1].MinVddci =
> smu_data-
>smc_state_table.MemoryLevel[0].MinVddci;
> smu_data->smc_state_table.MemoryLevel[1].MinMvdd =
It looks like amdgpu and radeon behave differently here: radeon overwrites the
MinVddc and MinVddcPhases vs. amdgpu overwrites MinVddci and MinMvdd.
Without knowing more details of what the workaround was trying to achieve,
it's hard to judge whether radeon or amdgpu was correct, but it would be nice
to make them consistent. If radeon was correct, could you adjust the amdgpu
code here to do the same? (Or vice versa if amdgpu was correct.)
With that, the series is:
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Thanks & best regards,
Timur
prev parent reply other threads:[~2026-04-28 10:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-27 17:31 [PATCH 1/2] drm/amdgpu/pm: add missing revision check for CI Alex Deucher
2026-04-27 17:31 ` [PATCH 2/2] drm/radeon: " Alex Deucher
2026-04-27 18:22 ` Russell, Kent
2026-04-28 10:29 ` Timur Kristóf
2026-04-28 10:20 ` Timur Kristóf [this message]
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