From: "Timur Kristóf" <timur.kristof@gmail.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx@lists.freedesktop.org, Alex Deucher <alexander.deucher@amd.com>
Subject: Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL
Date: Tue, 07 Jul 2026 17:14:00 +0200 [thread overview]
Message-ID: <4904707.vXUDI8C0e8@timur-hyperion> (raw)
In-Reply-To: <CADnq5_O-Ho6fq+8P=1jg3t0vRwSY1tCY_=erxgetKXUiA-Ma7g@mail.gmail.com>
On Tuesday, July 7, 2026 3:44:28 PM Central European Summer Time Alex Deucher
wrote:
> On Tue, Jul 7, 2026 at 4:06 AM Timur Kristóf <timur.kristof@gmail.com>
wrote:
> > On 2026. június 26., péntek 22:40:58 közép-európai nyári idő Alex Deucher
> >
> > wrote:
> > > This is needed to allocate occlusion counters across
> > > both gfx pipes.
> > >
> > > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > >
> > > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index
> > > d72ecf5dab09e..6ff7a8a700939
> > > 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct
> > > amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev);
> > >
> > > adev->gfx.config.pa_sc_tile_steering_override =
> > >
> > > gfx_v10_0_init_pa_sc_tile_steering_override(adev);
> > >
> > > + /* program DB_RING_CONTROL for multiple GFX pipes */
> > > + WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
> > > + (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
> >
> > Hi Alex,
> >
> > Why do you set this to zero when the number of pipes is more than 1?
> > Wouldn't it need to be the other way around and set to the number of pipes
> > (or number of rings)?
>
> The hardware default is 1. The other settings are as follows for this
> field: 0 - split occlusion counters between gfx pipes
> 1 - all occlusion counters to pipe 0
> 2 - all occlusion counters to pipe 1
>
I see, thanks!
Could you please mention that in a comment or maybe add an enum for the
possible values of that field?
With that, the series is:
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
> >
> > > /* XXX SH_MEM regs */
> > > /* where to put LDS, scratch, GPUVM in FSA64 space */
prev parent reply other threads:[~2026-07-07 15:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-26 20:40 [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL Alex Deucher
2026-06-26 20:40 ` [PATCH 2/4] drm/gfx11: " Alex Deucher
2026-06-26 20:41 ` [PATCH 3/4] drm/gfx12: " Alex Deucher
2026-06-26 20:41 ` [PATCH 4/4] drm/amdgpu/gfx11: enable gfx pipe1 hardware support Alex Deucher
2026-07-07 8:08 ` Timur Kristóf
2026-07-06 15:00 ` [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL Alex Deucher
2026-07-07 8:06 ` Timur Kristóf
2026-07-07 13:44 ` Alex Deucher
2026-07-07 15:14 ` Timur Kristóf [this message]
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