Re: [PATCH 4/4] drm/amdgpu/gfx11: enable gfx pipe1 hardware support

["Timur Kristóf" <timur.kristof@gmail.com>]

On 2026. június 26., péntek 22:41:01 közép-európai nyári idő Alex Deucher 
wrote:
> Enable gfx pipe1 hardware support.  This is only available
> on gfx11 chips using the F32 microcontroller.  Chips using
> the RS64 microcontroller are not able to use the second gfx
> pipe.  In practice this means the second pipe is only
> available on APUs. This explains the stability issues
> Pierre-Eric saw previously with this on Navi33.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5e7d0cd85c365..c0e34519b6b06
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -51,7 +51,7 @@
>  #include "mes_userqueue.h"
>  #include "amdgpu_userq_fence.h"
> 
> -#define GFX11_NUM_GFX_RINGS		1
> +#define GFX11_NUM_GFX_RINGS		2
>  #define GFX11_MEC_HPD_SIZE	2048
> 
>  #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
> @@ -1612,7 +1612,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block
> *ip_block) case IP_VERSION(11, 5, 4):
>  	case IP_VERSION(11, 5, 6):
>  		adev->gfx.me.num_me = 1;
> -		adev->gfx.me.num_pipe_per_me = 1;
> +		if (adev->gfx.rs64_enable)
> +			adev->gfx.me.num_pipe_per_me = 1;
> +		else
> +			adev->gfx.me.num_pipe_per_me = 2;
>  		adev->gfx.me.num_queue_per_pipe = 2;
>  		adev->gfx.mec.num_mec = 1;
>  		adev->gfx.mec.num_pipe_per_mec = 4;
> @@ -5355,6 +5358,7 @@ static void gfx_v11_0_ring_emit_gds_switch(struct
> amdgpu_ring *ring, static int gfx_v11_0_early_init(struct amdgpu_ip_block
> *ip_block) {
>  	struct amdgpu_device *adev = ip_block->adev;
> +	int r;
> 
>  	switch (amdgpu_user_queue) {
>  	case -1:
> @@ -5375,6 +5379,11 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block)
> 
>  	adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
> 
> +	gfx_v11_0_set_imu_funcs(adev);
> +	r = gfx_v11_0_init_microcode(adev);
> +	if (r)
> +		return r;
> +
>  	if (adev->gfx.disable_kq) {
>  		/* We need one GFX ring temporarily to set up
>  		 * the clear state.
> @@ -5382,7 +5391,11 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block) adev->gfx.num_gfx_rings = 1;
>  		adev->gfx.num_compute_rings = 0;
>  	} else {
> -		adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
> +		/* rs64 only supports one gfx pipe */
> +		if (adev->gfx.rs64_enable)
> +			adev->gfx.num_gfx_rings = 1;
> +		else
> +			adev->gfx.num_gfx_rings = 
GFX11_NUM_GFX_RINGS;

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Could you maybe move this code to a small helper function, eg. we could call 
it gfx_v11_0_calc_num_pipes_per_me() and call that from both places.

Thanks & best regards,
Timur


>  		adev->gfx.num_compute_rings = 
min(amdgpu_gfx_get_num_kcq(adev),
>  						  
AMDGPU_MAX_COMPUTE_RINGS);
>  	}
> @@ -5393,13 +5406,12 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block) gfx_v11_0_set_gds_init(adev);
>  	gfx_v11_0_set_rlc_funcs(adev);
>  	gfx_v11_0_set_mqd_funcs(adev);
> -	gfx_v11_0_set_imu_funcs(adev);
> 
>  	gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
> 
>  	amdgpu_init_rlc_reg_funcs(adev);
> 
> -	return gfx_v11_0_init_microcode(adev);
> +	return 0;
>  }
> 
>  static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)