[PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[Alex Deucher]

This is needed to allocate occlusion counters across
both gfx pipes.

Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d72ecf5dab09e..6ff7a8a700939 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
 	gfx_v10_0_get_tcc_info(adev);
 	adev->gfx.config.pa_sc_tile_steering_override =
 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
+	/* program DB_RING_CONTROL for multiple GFX pipes */
+	WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
+		       (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
 
 	/* XXX SH_MEM regs */
 	/* where to put LDS, scratch, GPUVM in FSA64 space */
-- 
2.54.0

[PATCH 2/4] drm/gfx11: Program DB_RING_CONTROL

[Alex Deucher]

This is needed to allocate occlusion counters across
both gfx pipes. No functional change since we only
use one gfx pipe at the moment (default value is 1).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index d171d41654980..5e7d0cd85c365 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -2178,6 +2178,9 @@ static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
 	tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
 	adev->gfx.config.ta_cntl2_truncate_coord_mode =
 		REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
+	/* program DB_RING_CONTROL for multiple GFX pipes */
+	WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
+			      (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
 
 	/* XXX SH_MEM regs */
 	/* where to put LDS, scratch, GPUVM in FSA64 space */
-- 
2.54.0

[PATCH 3/4] drm/gfx12: Program DB_RING_CONTROL

[Alex Deucher]

This is needed to allocate occlusion counters across
both gfx pipes. GFX 12 only has one gfx pipe, so no functional
change since the default value is 1.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index a2f0960b23fae..9ae9b1e4d291e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -1826,6 +1826,9 @@ static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
 	gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
 	gfx_v12_0_get_tcc_info(adev);
 	adev->gfx.config.pa_sc_tile_steering_override = 0;
+	/* program DB_RING_CONTROL for multiple GFX pipes */
+	WREG32_FIELD15_PREREG(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
+			      (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
 
 	/* XXX SH_MEM regs */
 	/* where to put LDS, scratch, GPUVM in FSA64 space */
-- 
2.54.0

[PATCH 4/4] drm/amdgpu/gfx11: enable gfx pipe1 hardware support

[Alex Deucher]

Enable gfx pipe1 hardware support.  This is only available
on gfx11 chips using the F32 microcontroller.  Chips using
the RS64 microcontroller are not able to use the second gfx
pipe.  In practice this means the second pipe is only
available on APUs. This explains the stability issues
Pierre-Eric saw previously with this on Navi33.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5e7d0cd85c365..c0e34519b6b06 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -51,7 +51,7 @@
 #include "mes_userqueue.h"
 #include "amdgpu_userq_fence.h"
 
-#define GFX11_NUM_GFX_RINGS		1
+#define GFX11_NUM_GFX_RINGS		2
 #define GFX11_MEC_HPD_SIZE	2048
 
 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
@@ -1612,7 +1612,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
 	case IP_VERSION(11, 5, 4):
 	case IP_VERSION(11, 5, 6):
 		adev->gfx.me.num_me = 1;
-		adev->gfx.me.num_pipe_per_me = 1;
+		if (adev->gfx.rs64_enable)
+			adev->gfx.me.num_pipe_per_me = 1;
+		else
+			adev->gfx.me.num_pipe_per_me = 2;
 		adev->gfx.me.num_queue_per_pipe = 2;
 		adev->gfx.mec.num_mec = 1;
 		adev->gfx.mec.num_pipe_per_mec = 4;
@@ -5355,6 +5358,7 @@ static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
 static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
 
 	switch (amdgpu_user_queue) {
 	case -1:
@@ -5375,6 +5379,11 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 
 	adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
 
+	gfx_v11_0_set_imu_funcs(adev);
+	r = gfx_v11_0_init_microcode(adev);
+	if (r)
+		return r;
+
 	if (adev->gfx.disable_kq) {
 		/* We need one GFX ring temporarily to set up
 		 * the clear state.
@@ -5382,7 +5391,11 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 		adev->gfx.num_gfx_rings = 1;
 		adev->gfx.num_compute_rings = 0;
 	} else {
-		adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
+		/* rs64 only supports one gfx pipe */
+		if (adev->gfx.rs64_enable)
+			adev->gfx.num_gfx_rings = 1;
+		else
+			adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
 		adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
 						  AMDGPU_MAX_COMPUTE_RINGS);
 	}
@@ -5393,13 +5406,12 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
 	gfx_v11_0_set_gds_init(adev);
 	gfx_v11_0_set_rlc_funcs(adev);
 	gfx_v11_0_set_mqd_funcs(adev);
-	gfx_v11_0_set_imu_funcs(adev);
 
 	gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
 
 	amdgpu_init_rlc_reg_funcs(adev);
 
-	return gfx_v11_0_init_microcode(adev);
+	return 0;
 }
 
 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
-- 
2.54.0

Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[Alex Deucher]

Ping on this series?

On Fri, Jun 26, 2026 at 4:49 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> This is needed to allocate occlusion counters across
> both gfx pipes.
>
> Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index d72ecf5dab09e..6ff7a8a700939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
>         gfx_v10_0_get_tcc_info(adev);
>         adev->gfx.config.pa_sc_tile_steering_override =
>                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
> +       /* program DB_RING_CONTROL for multiple GFX pipes */
> +       WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
> +                      (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
>
>         /* XXX SH_MEM regs */
>         /* where to put LDS, scratch, GPUVM in FSA64 space */
> --
> 2.54.0
>

Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[Timur Kristóf]

On 2026. június 26., péntek 22:40:58 közép-európai nyári idő Alex Deucher 
wrote:
> This is needed to allocate occlusion counters across
> both gfx pipes.
> 
> Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d72ecf5dab09e..6ff7a8a700939
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct
> amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev);
>  	adev->gfx.config.pa_sc_tile_steering_override =
>  		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
> +	/* program DB_RING_CONTROL for multiple GFX pipes */
> +	WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
> +		       (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);

Hi Alex,

Why do you set this to zero when the number of pipes is more than 1?
Wouldn't it need to be the other way around and set to the number of pipes (or 
number of rings)?

Thanks,
Timur

> 
>  	/* XXX SH_MEM regs */
>  	/* where to put LDS, scratch, GPUVM in FSA64 space */

Re: [PATCH 4/4] drm/amdgpu/gfx11: enable gfx pipe1 hardware support

[Timur Kristóf]

On 2026. június 26., péntek 22:41:01 közép-európai nyári idő Alex Deucher 
wrote:
> Enable gfx pipe1 hardware support.  This is only available
> on gfx11 chips using the F32 microcontroller.  Chips using
> the RS64 microcontroller are not able to use the second gfx
> pipe.  In practice this means the second pipe is only
> available on APUs. This explains the stability issues
> Pierre-Eric saw previously with this on Navi33.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5e7d0cd85c365..c0e34519b6b06
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -51,7 +51,7 @@
>  #include "mes_userqueue.h"
>  #include "amdgpu_userq_fence.h"
> 
> -#define GFX11_NUM_GFX_RINGS		1
> +#define GFX11_NUM_GFX_RINGS		2
>  #define GFX11_MEC_HPD_SIZE	2048
> 
>  #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
> @@ -1612,7 +1612,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block
> *ip_block) case IP_VERSION(11, 5, 4):
>  	case IP_VERSION(11, 5, 6):
>  		adev->gfx.me.num_me = 1;
> -		adev->gfx.me.num_pipe_per_me = 1;
> +		if (adev->gfx.rs64_enable)
> +			adev->gfx.me.num_pipe_per_me = 1;
> +		else
> +			adev->gfx.me.num_pipe_per_me = 2;
>  		adev->gfx.me.num_queue_per_pipe = 2;
>  		adev->gfx.mec.num_mec = 1;
>  		adev->gfx.mec.num_pipe_per_mec = 4;
> @@ -5355,6 +5358,7 @@ static void gfx_v11_0_ring_emit_gds_switch(struct
> amdgpu_ring *ring, static int gfx_v11_0_early_init(struct amdgpu_ip_block
> *ip_block) {
>  	struct amdgpu_device *adev = ip_block->adev;
> +	int r;
> 
>  	switch (amdgpu_user_queue) {
>  	case -1:
> @@ -5375,6 +5379,11 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block)
> 
>  	adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
> 
> +	gfx_v11_0_set_imu_funcs(adev);
> +	r = gfx_v11_0_init_microcode(adev);
> +	if (r)
> +		return r;
> +
>  	if (adev->gfx.disable_kq) {
>  		/* We need one GFX ring temporarily to set up
>  		 * the clear state.
> @@ -5382,7 +5391,11 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block) adev->gfx.num_gfx_rings = 1;
>  		adev->gfx.num_compute_rings = 0;
>  	} else {
> -		adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
> +		/* rs64 only supports one gfx pipe */
> +		if (adev->gfx.rs64_enable)
> +			adev->gfx.num_gfx_rings = 1;
> +		else
> +			adev->gfx.num_gfx_rings = 
GFX11_NUM_GFX_RINGS;

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Could you maybe move this code to a small helper function, eg. we could call 
it gfx_v11_0_calc_num_pipes_per_me() and call that from both places.

Thanks & best regards,
Timur


>  		adev->gfx.num_compute_rings = 
min(amdgpu_gfx_get_num_kcq(adev),
>  						  
AMDGPU_MAX_COMPUTE_RINGS);
>  	}
> @@ -5393,13 +5406,12 @@ static int gfx_v11_0_early_init(struct
> amdgpu_ip_block *ip_block) gfx_v11_0_set_gds_init(adev);
>  	gfx_v11_0_set_rlc_funcs(adev);
>  	gfx_v11_0_set_mqd_funcs(adev);
> -	gfx_v11_0_set_imu_funcs(adev);
> 
>  	gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
> 
>  	amdgpu_init_rlc_reg_funcs(adev);
> 
> -	return gfx_v11_0_init_microcode(adev);
> +	return 0;
>  }
> 
>  static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)

Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[Alex Deucher]

On Tue, Jul 7, 2026 at 4:06 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On 2026. június 26., péntek 22:40:58 közép-európai nyári idő Alex Deucher
> wrote:
> > This is needed to allocate occlusion counters across
> > both gfx pipes.
> >
> > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d72ecf5dab09e..6ff7a8a700939
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct
> > amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev);
> >       adev->gfx.config.pa_sc_tile_steering_override =
> >               gfx_v10_0_init_pa_sc_tile_steering_override(adev);
> > +     /* program DB_RING_CONTROL for multiple GFX pipes */
> > +     WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
> > +                    (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
>
> Hi Alex,
>
> Why do you set this to zero when the number of pipes is more than 1?
> Wouldn't it need to be the other way around and set to the number of pipes (or
> number of rings)?

The hardware default is 1.  The other settings are as follows for this field:
0 - split occlusion counters between gfx pipes
1 - all occlusion counters to pipe 0
2 - all occlusion counters to pipe 1

Alex

>
> Thanks,
> Timur
>
> >
> >       /* XXX SH_MEM regs */
> >       /* where to put LDS, scratch, GPUVM in FSA64 space */
>
>
>
>

Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL

[Timur Kristóf]

On Tuesday, July 7, 2026 3:44:28 PM Central European Summer Time Alex Deucher 
wrote:
> On Tue, Jul 7, 2026 at 4:06 AM Timur Kristóf <timur.kristof@gmail.com> 
wrote:
> > On 2026. június 26., péntek 22:40:58 közép-európai nyári idő Alex Deucher
> > 
> > wrote:
> > > This is needed to allocate occlusion counters across
> > > both gfx pipes.
> > > 
> > > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support")
> > > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > > ---
> > > 
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index
> > > d72ecf5dab09e..6ff7a8a700939
> > > 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct
> > > amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev);
> > > 
> > >       adev->gfx.config.pa_sc_tile_steering_override =
> > >       
> > >               gfx_v10_0_init_pa_sc_tile_steering_override(adev);
> > > 
> > > +     /* program DB_RING_CONTROL for multiple GFX pipes */
> > > +     WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL,
> > > +                    (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1);
> > 
> > Hi Alex,
> > 
> > Why do you set this to zero when the number of pipes is more than 1?
> > Wouldn't it need to be the other way around and set to the number of pipes
> > (or number of rings)?
> 
> The hardware default is 1.  The other settings are as follows for this
> field: 0 - split occlusion counters between gfx pipes
> 1 - all occlusion counters to pipe 0
> 2 - all occlusion counters to pipe 1
> 

I see, thanks!

Could you please mention that in a comment or maybe add an enum for the 
possible values of that field?

With that, the series is:
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>


> > 
> > >       /* XXX SH_MEM regs */
> > >       /* where to put LDS, scratch, GPUVM in FSA64 space */