* [PATCH 01/32] drm/amd/display: Only register backlight device if embedded panel connected
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 02/32] drm/amd/display: Don't register backlight on connector_destroy Harry Wentland
` (30 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 58 +++++++++++++----------
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 47ef8f5b6c9a..0a5a5ae5ab50 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1403,6 +1403,28 @@ static int initialize_plane(struct amdgpu_display_manager *dm,
return ret;
}
+
+static void register_backlight_device(struct amdgpu_display_manager *dm,
+ struct dc_link *link)
+{
+#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
+ defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
+
+ if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
+ link->type != dc_connection_none) {
+ /* Event if registration failed, we should continue with
+ * DM initialization because not having a backlight control
+ * is better then a black screen.
+ */
+ amdgpu_dm_register_backlight_device(dm);
+
+ if (dm->backlight_dev)
+ dm->backlight_link = link;
+ }
+#endif
+}
+
+
/* In this architecture, the association
* connector -> encoder -> crtc
* id not really requried. The crtc and connector will hold the
@@ -1456,6 +1478,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
+ struct dc_link *link = NULL;
if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
DRM_ERROR(
@@ -1482,9 +1505,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
goto fail;
}
- if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
- DETECT_REASON_BOOT))
+ link = dc_get_link_at_index(dm->dc, i);
+
+ if (dc_link_detect(link, DETECT_REASON_BOOT)) {
amdgpu_dm_update_connector_after_detect(aconnector);
+ register_backlight_device(dm, link);
+ }
+
+
}
/* Software is initialized. Now we can register interrupt handlers. */
@@ -2715,7 +2743,8 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
- if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
+ if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
+ link->type != dc_connection_none) {
amdgpu_dm_register_backlight_device(dm);
if (dm->backlight_dev) {
@@ -3596,6 +3625,7 @@ create_i2c(struct ddc_service *ddc_service,
return i2c;
}
+
/* Note: this function assumes that dc_link_detect() was called for the
* dc_link which will be represented by this aconnector.
*/
@@ -3665,28 +3695,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
|| connector_type == DRM_MODE_CONNECTOR_eDP)
amdgpu_dm_initialize_dp_connector(dm, aconnector);
-#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
- defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
-
- /* NOTE: this currently will create backlight device even if a panel
- * is not connected to the eDP/LVDS connector.
- *
- * This is less than ideal but we don't have sink information at this
- * stage since detection happens after. We can't do detection earlier
- * since MST detection needs connectors to be created first.
- */
- if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
- /* Event if registration failed, we should continue with
- * DM initialization because not having a backlight control
- * is better then a black screen.
- */
- amdgpu_dm_register_backlight_device(dm);
-
- if (dm->backlight_dev)
- dm->backlight_link = link;
- }
-#endif
-
out_free:
if (res) {
kfree(i2c);
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 02/32] drm/amd/display: Don't register backlight on connector_destroy
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-04-04 1:27 ` [PATCH 01/32] drm/amd/display: Only register backlight device if embedded panel connected Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 03/32] drm/amd/display: Program v_total_min/max after v_total_cntl Harry Wentland
` (29 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0a5a5ae5ab50..3b2437d5fdd4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2744,14 +2744,10 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
- link->type != dc_connection_none) {
- amdgpu_dm_register_backlight_device(dm);
-
- if (dm->backlight_dev) {
- backlight_device_unregister(dm->backlight_dev);
- dm->backlight_dev = NULL;
- }
-
+ link->type != dc_connection_none &&
+ dm->backlight_dev) {
+ backlight_device_unregister(dm->backlight_dev);
+ dm->backlight_dev = NULL;
}
#endif
drm_connector_unregister(connector);
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 03/32] drm/amd/display: Program v_total_min/max after v_total_cntl
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-04-04 1:27 ` [PATCH 01/32] drm/amd/display: Only register backlight device if embedded panel connected Harry Wentland
2018-04-04 1:27 ` [PATCH 02/32] drm/amd/display: Don't register backlight on connector_destroy Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 04/32] drm/amd/display: Set ignore_msa_timing_param Harry Wentland
` (28 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
.../drm/amd/display/dc/dce110/dce110_timing_generator.c | 16 ++++++++--------
.../drm/amd/display/dc/dce120/dce120_timing_generator.c | 12 ++++++------
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 12 ++++++------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index be7153924a70..1b2fe0df347f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_SET_V_TOTAL_MIN_MASK);
- set_reg_field_value(v_total_min,
- 0,
- CRTC_V_TOTAL_MIN,
- CRTC_V_TOTAL_MIN);
- set_reg_field_value(v_total_max,
- 0,
- CRTC_V_TOTAL_MAX,
- CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,
@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_V_TOTAL_MAX_SEL);
+ set_reg_field_value(v_total_min,
+ 0,
+ CRTC_V_TOTAL_MIN,
+ CRTC_V_TOTAL_MIN);
+ set_reg_field_value(v_total_max,
+ 0,
+ CRTC_V_TOTAL_MAX,
+ CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 7bee78172d85..2ea490f8482e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr(
0x180);
} else {
- CRTC_REG_UPDATE(
- CRTC0_CRTC_V_TOTAL_MIN,
- CRTC_V_TOTAL_MIN, 0);
- CRTC_REG_UPDATE(
- CRTC0_CRTC_V_TOTAL_MAX,
- CRTC_V_TOTAL_MAX, 0);
CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
+ CRTC_REG_UPDATE(
+ CRTC0_CRTC_V_TOTAL_MIN,
+ CRTC_V_TOTAL_MIN, 0);
+ CRTC_REG_UPDATE(
+ CRTC0_CRTC_V_TOTAL_MAX,
+ CRTC_V_TOTAL_MAX, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_STATIC_SCREEN_CONTROL,
CRTC_STATIC_SCREEN_EVENT_MASK,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index f56eac0e4dd2..dc921307874a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -855,17 +855,17 @@ void optc1_set_drr(
OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
OTG_SET_V_TOTAL_MIN_MASK, 0);
} else {
- REG_SET(OTG_V_TOTAL_MIN, 0,
- OTG_V_TOTAL_MIN, 0);
-
- REG_SET(OTG_V_TOTAL_MAX, 0,
- OTG_V_TOTAL_MAX, 0);
-
REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
OTG_SET_V_TOTAL_MIN_MASK, 0,
OTG_V_TOTAL_MIN_SEL, 0,
OTG_V_TOTAL_MAX_SEL, 0,
OTG_FORCE_LOCK_ON_EVENT, 0);
+
+ REG_SET(OTG_V_TOTAL_MIN, 0,
+ OTG_V_TOTAL_MIN, 0);
+
+ REG_SET(OTG_V_TOTAL_MAX, 0,
+ OTG_V_TOTAL_MAX, 0);
}
}
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 04/32] drm/amd/display: Set ignore_msa_timing_param
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 03/32] drm/amd/display: Program v_total_min/max after v_total_cntl Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 05/32] drm/amd/display: Non-HDMI DP active dongle should not support YUV pixel format Harry Wentland
` (27 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3b2437d5fdd4..a2399b53c9e0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2492,6 +2492,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
update_stream_signal(stream);
+ if (dm_state && dm_state->freesync_capable)
+ stream->ignore_msa_timing_param = true;
+
return stream;
}
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 05/32] drm/amd/display: Non-HDMI DP active dongle should not support YUV pixel format
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 04/32] drm/amd/display: Set ignore_msa_timing_param Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 06/32] drm/amd/display: Fix potential access beyond end of array in CM Harry Wentland
` (26 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Hersen Wu
From: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c18f24afa698..e612841f7f91 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1848,9 +1848,22 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
static bool dp_active_dongle_validate_timing(
const struct dc_crtc_timing *timing,
- const struct dc_dongle_caps *dongle_caps)
+ const struct dpcd_caps *dpcd_caps)
{
unsigned int required_pix_clk = timing->pix_clk_khz;
+ const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
+
+ switch (dpcd_caps->dongle_type) {
+ case DISPLAY_DONGLE_DP_VGA_CONVERTER:
+ case DISPLAY_DONGLE_DP_DVI_CONVERTER:
+ case DISPLAY_DONGLE_DP_DVI_DONGLE:
+ if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
+ return true;
+ else
+ return false;
+ default:
+ break;
+ }
if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
dongle_caps->extendedCapValid == false)
@@ -1916,7 +1929,7 @@ enum dc_status dc_link_validate_mode_timing(
const struct dc_crtc_timing *timing)
{
uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
- struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
+ struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
/* A hack to avoid failing any modes for EDID override feature on
* topology change such as lower quality cable for DP or different dongle
@@ -1929,7 +1942,7 @@ enum dc_status dc_link_validate_mode_timing(
return DC_EXCEED_DONGLE_CAP;
/* Active Dongle*/
- if (!dp_active_dongle_validate_timing(timing, dongle_caps))
+ if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
return DC_EXCEED_DONGLE_CAP;
switch (stream->signal) {
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 06/32] drm/amd/display: Fix potential access beyond end of array in CM
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 05/32] drm/amd/display: Non-HDMI DP active dongle should not support YUV pixel format Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 07/32] drm/amd/display: Add Dynamic debug prints Harry Wentland
` (25 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland, Dan Carpenter
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
CC: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 881a1bff94d2..96d5878e9ccd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -367,15 +367,15 @@ bool cm_helper_translate_curve_to_hw_format(
lut_params->hw_points_num = hw_points;
- i = 1;
- for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
+ k = 0;
+ for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
- i++;
+ k++;
}
if (seg_distr[k] != -1)
@@ -529,15 +529,15 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
lut_params->hw_points_num = hw_points;
- i = 1;
- for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
+ k = 0;
+ for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
- i++;
+ k++;
}
if (seg_distr[k] != -1)
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 07/32] drm/amd/display: Add Dynamic debug prints
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 06/32] drm/amd/display: Fix potential access beyond end of array in CM Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 08/32] drm/amd/display: Add vmax/min_sel prints to dcn10_log_hw_state Harry Wentland
` (24 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Bhawanpreet Lakha
From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Created Macros for DC_LOG_XXX to pr_debug() & DRM_DEBUG_KMS.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 --
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 20 +++----
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 ++++---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 7 ++-
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 9 +--
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 11 ++--
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 7 ++-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 ++---
drivers/gpu/drm/amd/display/include/logger_types.h | 64 +++++++++++-----------
9 files changed, 77 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a2399b53c9e0..7bc31f280a56 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -433,11 +433,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
- if (amdgpu_dc_log)
- init_data.log_mask = DC_DEFAULT_LOG_MASK;
- else
- init_data.log_mask = DC_MIN_LOG_MASK;
-
/*
* TODO debug why this doesn't work on Raven
*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 71cc60fcff5e..a3c87611220d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -36,8 +36,9 @@
#include "hw_sequencer.h"
#include "resource.h"
-#define DC_LOGGER \
- logger
+
+#define DC_LOGGER_INIT(logger)
+
#define SURFACE_TRACE(...) do {\
if (dc->debug.surface_trace) \
@@ -60,8 +61,7 @@ void pre_surface_trace(
int surface_count)
{
int i;
- struct dc *core_dc = dc;
- struct dal_logger *logger = core_dc->ctx->logger;
+ DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < surface_count; i++) {
const struct dc_plane_state *plane_state = plane_states[i];
@@ -183,8 +183,7 @@ void update_surface_trace(
int surface_count)
{
int i;
- struct dc *core_dc = dc;
- struct dal_logger *logger = core_dc->ctx->logger;
+ DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < surface_count; i++) {
const struct dc_surface_update *update = &updates[i];
@@ -304,8 +303,7 @@ void update_surface_trace(
void post_surface_trace(struct dc *dc)
{
- struct dc *core_dc = dc;
- struct dal_logger *logger = core_dc->ctx->logger;
+ DC_LOGGER_INIT(dc->ctx->logger);
SURFACE_TRACE("post surface process.\n");
@@ -317,10 +315,10 @@ void context_timing_trace(
{
int i;
struct dc *core_dc = dc;
- struct dal_logger *logger = core_dc->ctx->logger;
int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
struct crtc_position position;
unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
+ DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
@@ -355,9 +353,7 @@ void context_clock_trace(
struct dc_state *context)
{
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
- struct dc *core_dc = dc;
- struct dal_logger *logger = core_dc->ctx->logger;
-
+ DC_LOGGER_INIT(dc->ctx->logger);
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index e612841f7f91..d9efdd926145 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -45,8 +45,9 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_enum.h"
#include "dce/dce_11_0_sh_mask.h"
-#define DC_LOGGER \
- dc_ctx->logger
+
+#define DC_LOGGER_INIT(logger)
+
#define LINK_INFO(...) \
DC_LOG_HW_HOTPLUG( \
@@ -561,7 +562,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL;
enum dc_connection_type new_connection_type = dc_connection_none;
-
+ DC_LOGGER_INIT(link->ctx->logger);
if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
return false;
@@ -927,6 +928,7 @@ static bool construct(
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
+ DC_LOGGER_INIT(dc_ctx->logger);
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@@ -1135,7 +1137,8 @@ static void dpcd_configure_panel_mode(
{
union dpcd_edp_config edp_config_set;
bool panel_mode_edp = false;
- struct dc_context *dc_ctx = link->ctx;
+ DC_LOGGER_INIT(link->ctx->logger);
+
memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
if (DP_PANEL_MODE_DEFAULT != panel_mode) {
@@ -1968,10 +1971,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
struct dc *core_dc = link->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
- struct dc_context *dc_ctx = link->ctx;
unsigned int controller_id = 0;
bool use_smooth_brightness = true;
int i;
+ DC_LOGGER_INIT(link->ctx->logger);
if ((dmcu == NULL) ||
(abm == NULL) ||
@@ -2154,8 +2157,8 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
- struct dc_context *dc_ctx = link->ctx;
uint8_t i;
+ DC_LOGGER_INIT(link->ctx->logger);
/* enable_link_dp_mst already check link->enabled_stream_count
* and stream is in link->stream[]. This is called during set mode,
@@ -2234,7 +2237,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
uint8_t i;
bool mst_mode = (link->type == dc_connection_mst_branch);
- struct dc_context *dc_ctx = link->ctx;
+ DC_LOGGER_INIT(link->ctx->logger);
/* deallocate_mst_payload is called before disable link. When mode or
* disable/enable monitor, new stream is created which is not in link
@@ -2307,8 +2310,8 @@ void core_link_enable_stream(
struct pipe_ctx *pipe_ctx)
{
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
- struct dc_context *dc_ctx = pipe_ctx->stream->ctx;
enum dc_status status;
+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
/* eDP lit up by bios already, no need to enable again. */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 379b05536321..50b84f69bd25 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -45,8 +45,9 @@
#include "dcn10/dcn10_resource.h"
#endif
#include "dce120/dce120_resource.h"
-#define DC_LOGGER \
- ctx->logger
+
+#define DC_LOGGER_INIT(logger)
+
enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
{
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
@@ -835,7 +836,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
struct view recout_skip = { 0 };
bool res = false;
- struct dc_context *ctx = pipe_ctx->stream->ctx;
+ DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
/* Important: scaling ratio calculation requires pixel format,
* lb depth calculation requires recout and taps require scaling ratios.
* Inits require viewport, taps, ratios and recout of split pipe
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 6d5cdcdc8ec9..7f6d724686f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -33,8 +33,9 @@
#define CTX \
aud->base.ctx
-#define DC_LOGGER \
- aud->base.ctx->logger
+
+#define DC_LOGGER_INIT()
+
#define REG(reg)\
(aud->regs->reg)
@@ -348,8 +349,8 @@ static void set_audio_latency(
void dce_aud_az_enable(struct audio *audio)
{
- struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+ DC_LOGGER_INIT();
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
@@ -371,7 +372,7 @@ void dce_aud_az_enable(struct audio *audio)
void dce_aud_az_disable(struct audio *audio)
{
uint32_t value;
- struct dce_audio *aud = DCE_AUD(audio);
+ DC_LOGGER_INIT();
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 0aa2cda60890..67dad7f1e643 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -41,8 +41,9 @@
#define CTX \
clk_src->base.ctx
-#define DC_LOGGER \
- calc_pll_cs->ctx->logger
+
+#define DC_LOGGER_INIT()
+
#undef FN
#define FN(reg_name, field_name) \
clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
@@ -467,7 +468,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
{
uint32_t field = 0;
uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
- struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
+ DC_LOGGER_INIT();
/* Check if reference clock is external (not pcie/xtalin)
* HW Dce80 spec:
* 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
@@ -557,8 +558,8 @@ static uint32_t dce110_get_pix_clk_dividers(
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
- struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
+ DC_LOGGER_INIT();
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk == 0) {
@@ -1054,7 +1055,7 @@ static void get_ss_info_from_atombios(
struct spread_spectrum_info *ss_info_cur;
struct spread_spectrum_data *ss_data_cur;
uint32_t i;
- struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
+ DC_LOGGER_INIT();
if (ss_entries_num == NULL) {
DC_LOG_SYNC(
"Invalid entry !!!\n");
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c6212301712b..e8df50f30e5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -70,8 +70,9 @@
#define CTX \
hws->ctx
-#define DC_LOGGER \
- ctx->logger
+
+#define DC_LOGGER_INIT()
+
#define REG(reg)\
hws->regs->reg
@@ -2701,7 +2702,7 @@ static void dce110_program_front_end_for_pipe(
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
unsigned int i;
- struct dc_context *ctx = dc->ctx;
+ DC_LOGGER_INIT();
memset(&tbl_entry, 0, sizeof(tbl_entry));
if (dc->current_state)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e21458169d15..de5293dc4db3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -45,8 +45,8 @@
#include "dcn10_hubbub.h"
#include "dcn10_cm_common.h"
-#define DC_LOGGER \
- ctx->logger
+#define DC_LOGGER_INIT(logger)
+
#define CTX \
hws->ctx
#define REG(reg)\
@@ -363,7 +363,7 @@ static void power_on_plane(
struct dce_hwseq *hws,
int plane_id)
{
- struct dc_context *ctx = hws->ctx;
+ DC_LOGGER_INIT(hws->ctx->logger);
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 1);
@@ -562,7 +562,7 @@ static void reset_back_end_for_pipe(
struct dc_state *context)
{
int i;
- struct dc_context *ctx = dc->ctx;
+ DC_LOGGER_INIT(dc->ctx->logger);
if (pipe_ctx->stream_res.stream_enc == NULL) {
pipe_ctx->stream = NULL;
return;
@@ -658,7 +658,7 @@ static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct dce_hwseq *hws = dc->hwseq;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
- struct dc_context *ctx = dc->ctx;
+ DC_LOGGER_INIT(dc->ctx->logger);
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
@@ -708,7 +708,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
- struct dc_context *ctx = dc->ctx;
+ DC_LOGGER_INIT(dc->ctx->logger);
if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
return;
@@ -2001,9 +2001,9 @@ static void dcn10_apply_ctx_for_surface(
bool removed_pipe[4] = { false };
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
bool program_water_mark = false;
- struct dc_context *ctx = dc->ctx;
struct pipe_ctx *top_pipe_to_program =
find_top_pipe_for_stream(dc, context, stream);
+ DC_LOGGER_INIT(dc->ctx->logger);
if (!top_pipe_to_program)
return;
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 427796bdc14a..4f332e80cecc 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -29,39 +29,39 @@
#include "os_types.h"
#define MAX_NAME_LEN 32
-#define DC_LOG_ERROR(a, ...) dm_logger_write(DC_LOGGER, LOG_ERROR, a, ## __VA_ARGS__)
-#define DC_LOG_WARNING(a, ...) dm_logger_write(DC_LOGGER, LOG_WARNING, a, ## __VA_ARGS__)
-#define DC_LOG_DEBUG(a, ...) dm_logger_write(DC_LOGGER, LOG_DEBUG, a, ## __VA_ARGS__)
-#define DC_LOG_DC(a, ...) dm_logger_write(DC_LOGGER, LOG_DC, a, ## __VA_ARGS__)
-#define DC_LOG_DTN(a, ...) dm_logger_write(DC_LOGGER, LOG_DTN, a, ## __VA_ARGS__)
-#define DC_LOG_SURFACE(a, ...) dm_logger_write(DC_LOGGER, LOG_SURFACE, a, ## __VA_ARGS__)
-#define DC_LOG_HW_HOTPLUG(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HOTPLUG, a, ## __VA_ARGS__)
-#define DC_LOG_HW_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_LINK_TRAINING, a, ## __VA_ARGS__)
-#define DC_LOG_HW_SET_MODE(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_SET_MODE, a, ## __VA_ARGS__)
-#define DC_LOG_HW_RESUME_S3(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_RESUME_S3, a, ## __VA_ARGS__)
-#define DC_LOG_HW_AUDIO(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_AUDIO, a, ## __VA_ARGS__)
-#define DC_LOG_HW_HPD_IRQ(a, ...) dm_logger_write(DC_LOGGER, LOG_HW_HPD_IRQ, a, ## __VA_ARGS__)
-#define DC_LOG_MST(a, ...) dm_logger_write(DC_LOGGER, LOG_MST, a, ## __VA_ARGS__)
-#define DC_LOG_SCALER(a, ...) dm_logger_write(DC_LOGGER, LOG_SCALER, a, ## __VA_ARGS__)
-#define DC_LOG_BIOS(a, ...) dm_logger_write(DC_LOGGER, LOG_BIOS, a, ## __VA_ARGS__)
-#define DC_LOG_BANDWIDTH_CALCS(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_CALCS, a, ## __VA_ARGS__)
-#define DC_LOG_BANDWIDTH_VALIDATION(a, ...) dm_logger_write(DC_LOGGER, LOG_BANDWIDTH_VALIDATION, a, ## __VA_ARGS__)
-#define DC_LOG_I2C_AUX(a, ...) dm_logger_write(DC_LOGGER, LOG_I2C_AUX, a, ## __VA_ARGS__)
-#define DC_LOG_SYNC(a, ...) dm_logger_write(DC_LOGGER, LOG_SYNC, a, ## __VA_ARGS__)
-#define DC_LOG_BACKLIGHT(a, ...) dm_logger_write(DC_LOGGER, LOG_BACKLIGHT, a, ## __VA_ARGS__)
-#define DC_LOG_FEATURE_OVERRIDE(a, ...) dm_logger_write(DC_LOGGER, LOG_FEATURE_OVERRIDE, a, ## __VA_ARGS__)
-#define DC_LOG_DETECTION_EDID_PARSER(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_EDID_PARSER, a, ## __VA_ARGS__)
-#define DC_LOG_DETECTION_DP_CAPS(a, ...) dm_logger_write(DC_LOGGER, LOG_DETECTION_DP_CAPS, a, ## __VA_ARGS__)
-#define DC_LOG_RESOURCE(a, ...) dm_logger_write(DC_LOGGER, LOG_RESOURCE, a, ## __VA_ARGS__)
-#define DC_LOG_DML(a, ...) dm_logger_write(DC_LOGGER, LOG_DML, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_MODE_SET(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_MODE_SET, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_DETECTION(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_DETECTION, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_LINK_TRAINING(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_TRAINING, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_LINK_LOSS(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_LINK_LOSS, a, ## __VA_ARGS__)
-#define DC_LOG_EVENT_UNDERFLOW(a, ...) dm_logger_write(DC_LOGGER, LOG_EVENT_UNDERFLOW, a, ## __VA_ARGS__)
-#define DC_LOG_IF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_IF_TRACE, a, ## __VA_ARGS__)
-#define DC_LOG_PERF_TRACE(a, ...) dm_logger_write(DC_LOGGER, LOG_PERF_TRACE, a, ## __VA_ARGS__)
+#define DC_LOG_ERROR(...) DRM_ERROR(__VA_ARGS__)
+#define DC_LOG_WARNING(...) DRM_WARN(__VA_ARGS__)
+#define DC_LOG_DEBUG(...) DRM_INFO(__VA_ARGS__)
+#define DC_LOG_DC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DTN(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SURFACE(...) pr_debug("[SURFACE]:"__VA_ARGS__)
+#define DC_LOG_HW_HOTPLUG(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_LINK_TRAINING(...) pr_debug("[HW_LINK_TRAINING]:"__VA_ARGS__)
+#define DC_LOG_HW_SET_MODE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_RESUME_S3(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_HW_AUDIO(...) pr_debug("[HW_AUDIO]:"__VA_ARGS__)
+#define DC_LOG_HW_HPD_IRQ(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_MST(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SCALER(...) pr_debug("[SCALER]:"__VA_ARGS__)
+#define DC_LOG_BIOS(...) pr_debug("[BIOS]:"__VA_ARGS__)
+#define DC_LOG_BANDWIDTH_CALCS(...) pr_debug("[BANDWIDTH_CALCS]:"__VA_ARGS__)
+#define DC_LOG_BANDWIDTH_VALIDATION(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_I2C_AUX(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_SYNC(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_BACKLIGHT(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_FEATURE_OVERRIDE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DETECTION_EDID_PARSER(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DETECTION_DP_CAPS(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_RESOURCE(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_DML(...) pr_debug("[DML]:"__VA_ARGS__)
+#define DC_LOG_EVENT_MODE_SET(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_DETECTION(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_LINK_TRAINING(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_LINK_LOSS(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_EVENT_UNDERFLOW(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
+#define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__)
struct dal_logger;
--
2.15.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 08/32] drm/amd/display: Add vmax/min_sel prints to dcn10_log_hw_state
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 07/32] drm/amd/display: Add Dynamic debug prints Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 09/32] drm/amd/display: Implement dm_get_timestamp Harry Wentland
` (23 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 ++++--
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 6 ++++++
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 2 ++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index de5293dc4db3..f3341a2399fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -165,7 +165,7 @@ void dcn10_log_hw_state(struct dc *dc)
}
DTN_INFO("\n");
- DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin"
+ DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
" h_bs h_be h_ss h_se hpol htot vtot underflow\n");
for (i = 0; i < pool->timing_generator_count; i++) {
@@ -178,7 +178,7 @@ void dcn10_log_hw_state(struct dc *dc)
if ((s.otg_enabled & 1) == 0)
continue;
- DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %5d %5d %5d"
+ DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
" %5d %5d %5d %5d %9d\n",
tg->inst,
s.v_blank_start,
@@ -188,6 +188,8 @@ void dcn10_log_hw_state(struct dc *dc)
s.v_sync_a_pol,
s.v_total_max,
s.v_total_min,
+ s.v_total_max_sel,
+ s.v_total_min_sel,
s.h_blank_start,
s.h_blank_end,
s.h_sync_a_start,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index dc921307874a..2c5dbece928e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -1229,6 +1229,12 @@ void optc1_read_otg_state(struct optc *optc1,
REG_GET(OTG_V_TOTAL_MIN,
OTG_V_TOTAL_MIN, &s->v_total_min);
+ REG_GET(OTG_V_TOTAL_CONTROL,
+ OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
+
+ REG_GET(OTG_V_TOTAL_CONTROL,
+ OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
+
REG_GET_2(OTG_V_SYNC_A,
OTG_V_SYNC_A_START, &s->v_sync_a_start,
OTG_V_SYNC_A_END, &s->v_sync_a_end);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 5a9a73d69fd6..89e09e5327a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -406,6 +406,8 @@ struct dcn_otg_state {
uint32_t v_total;
uint32_t v_total_max;
uint32_t v_total_min;
+ uint32_t v_total_min_sel;
+ uint32_t v_total_max_sel;
uint32_t v_sync_a_start;
uint32_t v_sync_a_end;
uint32_t h_blank_start;
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 09/32] drm/amd/display: Implement dm_get_timestamp
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 08/32] drm/amd/display: Add vmax/min_sel prints to dcn10_log_hw_state Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 10/32] drm/amd/display: add delay between panel pwr off to on Harry Wentland
` (22 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland
We use this to ensure we wait at least 500ms in between eDP
disable/enable.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 89342b48be6b..fe29125215b5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -37,8 +37,10 @@
unsigned long long dm_get_timestamp(struct dc_context *ctx)
{
- /* TODO: return actual timestamp */
- return 0;
+ struct timespec64 time;
+
+ getrawmonotonic64(&time);
+ return timespec64_to_ns(&time);
}
void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 10/32] drm/amd/display: add delay between panel pwr off to on.
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 09/32] drm/amd/display: Implement dm_get_timestamp Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 11/32] drm/amd/display: Set all update flags when we have full update Harry Wentland
` (21 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Charlene Liu
From: Charlene Liu <charlene.liu@amd.com>
As per eDP 1.4 spec, there must be at least 500ms delay
between eDP power off and on.
This change added time stamp when edp power off, which can
be used to calculate duration time when edp power on.
If duration less than 500ms, add a wait.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 7 ++++++
drivers/gpu/drm/amd/display/dc/dc_link.h | 9 +++++++
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +++++++++++++++++++++-
drivers/gpu/drm/amd/display/dc/dm_services.h | 4 +++
4 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index fe29125215b5..0229c7edb8ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -43,6 +43,13 @@ unsigned long long dm_get_timestamp(struct dc_context *ctx)
return timespec64_to_ns(&time);
}
+unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
+ unsigned long long current_time_stamp,
+ unsigned long long last_time_stamp)
+{
+ return current_time_stamp - last_time_stamp;
+}
+
void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
{
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index fb4d9eafdc6e..eeff98741293 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -51,6 +51,14 @@ struct link_mst_stream_allocation_table {
struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
};
+struct time_stamp {
+ uint64_t edp_poweroff;
+ uint64_t edp_poweron;
+};
+
+struct link_trace {
+ struct time_stamp time_stamp;
+};
/*
* A link contains one or more sinks and their connected status.
* The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
@@ -114,6 +122,7 @@ struct dc_link {
struct dc_link_status link_status;
+ struct link_trace link_trace;
};
const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e8df50f30e5b..db2d15dfb831 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -849,6 +849,28 @@ void hwss_edp_power_control(
if (power_up != is_panel_powered_on(hwseq)) {
/* Send VBIOS command to prompt eDP panel power */
+ if (power_up) {
+ unsigned long long current_ts = dm_get_timestamp(ctx);
+ unsigned long long duration_in_ms =
+ dm_get_elapse_time_in_ns(
+ ctx,
+ current_ts,
+ link->link_trace.time_stamp.edp_poweroff) / 1000000;
+ unsigned long long wait_time_ms = 0;
+
+ /* max 500ms from LCDVDD off to on */
+ if (link->link_trace.time_stamp.edp_poweroff == 0)
+ wait_time_ms = 500;
+ else if (duration_in_ms < 500)
+ wait_time_ms = 500 - duration_in_ms;
+
+ if (wait_time_ms) {
+ msleep(wait_time_ms);
+ dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
+ __func__, wait_time_ms);
+ }
+
+ }
DC_LOG_HW_RESUME_S3(
"%s: Panel Power action: %s\n",
@@ -862,9 +884,14 @@ void hwss_edp_power_control(
cntl.coherent = false;
cntl.lanes_number = LANE_COUNT_FOUR;
cntl.hpd_sel = link->link_enc->hpd_source;
-
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
+ if (!power_up)
+ /*save driver power off time stamp*/
+ link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
+ else
+ link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
+
if (bp_result != BP_RESULT_OK)
DC_LOG_ERROR(
"%s: Panel Power bp_result: %d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 22e7ee7dcd26..8eafe1af8a5e 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -341,6 +341,10 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
unsigned long long dm_get_timestamp(struct dc_context *ctx);
+unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
+ unsigned long long current_time_stamp,
+ unsigned long long last_time_stamp);
+
/*
* performance tracing
*/
--
2.15.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 11/32] drm/amd/display: Set all update flags when we have full update
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (9 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 10/32] drm/amd/display: add delay between panel pwr off to on Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 12/32] drm/amd/display: Refactor FreeSync module Harry Wentland
` (20 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Eric Yang
From: Eric Yang <Eric.Yang2@amd.com>
To prevent future optimization related bugs, just set all update
flags when we have a full update, since we know we want to reprogram
everything in that case.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 6f4ad67ffca6..b331d9e78cdb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1208,7 +1208,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
if (type == UPDATE_TYPE_FULL)
for (i = 0; i < surface_count; i++)
- updates[i].surface->update_flags.bits.full_update = 1;
+ updates[i].surface->update_flags.raw = 0xFFFFFFFF;
return type;
}
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 12/32] drm/amd/display: Refactor FreeSync module
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (10 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 11/32] drm/amd/display: Set all update flags when we have full update Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 13/32] drm/amd/display: Refactor stream encoder for HW review Harry Wentland
` (19 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Harry Wentland, Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Remove dependency on internal sink map and instead
use existing stream and plane state
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 322 ++--
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 18 +-
.../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 60 +-
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 3 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 110 +-
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 6 -
drivers/gpu/drm/amd/display/dc/dc_stream.h | 29 +-
drivers/gpu/drm/amd/display/dc/dc_types.h | 22 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 34 +-
.../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 27 +-
.../gpu/drm/amd/display/include/set_mode_types.h | 12 -
.../drm/amd/display/modules/freesync/freesync.c | 1836 +++++++-------------
.../gpu/drm/amd/display/modules/inc/mod_freesync.h | 144 +-
14 files changed, 937 insertions(+), 1695 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7bc31f280a56..55a8aaf68a1f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -54,8 +54,6 @@
#include <drm/drm_fb_helper.h>
#include <drm/drm_edid.h>
-#include "modules/inc/mod_freesync.h"
-
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "ivsrcid/irqsrcs_dcn_1_0.h"
@@ -850,8 +848,7 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
if (sink) {
if (aconnector->dc_sink) {
- amdgpu_dm_remove_sink_from_freesync_module(
- connector);
+ amdgpu_dm_update_freesync_caps(connector, NULL);
/* retain and release bellow are used for
* bump up refcount for sink because the link don't point
* to it anymore after disconnect so on next crtc to connector
@@ -861,10 +858,10 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
dc_sink_release(aconnector->dc_sink);
}
aconnector->dc_sink = sink;
- amdgpu_dm_add_sink_to_freesync_module(
- connector, aconnector->edid);
+ amdgpu_dm_update_freesync_caps(connector,
+ aconnector->edid);
} else {
- amdgpu_dm_remove_sink_from_freesync_module(connector);
+ amdgpu_dm_update_freesync_caps(connector, NULL);
if (!aconnector->dc_sink)
aconnector->dc_sink = aconnector->dc_em_sink;
else if (aconnector->dc_sink != aconnector->dc_em_sink)
@@ -901,8 +898,7 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
/* TODO: check if we still need the S3 mode update workaround.
* If yes, put it here. */
if (aconnector->dc_sink)
- amdgpu_dm_remove_sink_from_freesync_module(
- connector);
+ amdgpu_dm_update_freesync_caps(connector, NULL);
aconnector->dc_sink = sink;
if (sink->dc_edid.length == 0) {
@@ -915,10 +911,10 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
drm_mode_connector_update_edid_property(connector,
aconnector->edid);
}
- amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
+ amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
} else {
- amdgpu_dm_remove_sink_from_freesync_module(connector);
+ amdgpu_dm_update_freesync_caps(connector, NULL);
drm_mode_connector_update_edid_property(connector, NULL);
aconnector->num_modes = 0;
aconnector->dc_sink = NULL;
@@ -1594,31 +1590,72 @@ static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
struct drm_file *filp)
{
- struct mod_freesync_params freesync_params;
- uint8_t num_streams;
- uint8_t i;
-
- struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_freesync *args = data;
- int r = 0;
+ struct drm_atomic_state *state;
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_crtc *crtc;
+ struct drm_connector *connector;
+ struct drm_connector_state *old_con_state, *new_con_state;
+ int ret = 0;
+ uint8_t i;
+ bool enable = false;
- freesync_params.state = FREESYNC_STATE_FULLSCREEN;
if (args->op == AMDGPU_FREESYNC_FULLSCREEN_ENTER)
- freesync_params.enable = true;
- else
- freesync_params.enable = false;
+ enable = true;
- num_streams = dc_get_current_stream_count(adev->dm.dc);
+ drm_modeset_acquire_init(&ctx, 0);
- for (i = 0; i < num_streams; i++) {
- struct dc_stream_state *stream;
- stream = dc_get_stream_at_index(adev->dm.dc, i);
+ state = drm_atomic_state_alloc(dev);
+ if (!state) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ state->acquire_ctx = &ctx;
- mod_freesync_update_state(adev->dm.freesync_module,
- &stream, 1, &freesync_params);
+retry:
+ drm_for_each_crtc(crtc, dev) {
+ ret = drm_atomic_add_affected_connectors(state, crtc);
+ if (ret)
+ goto fail;
+
+ /* TODO rework amdgpu_dm_commit_planes so we don't need this */
+ ret = drm_atomic_add_affected_planes(state, crtc);
+ if (ret)
+ goto fail;
}
- return r;
+ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
+ struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
+ struct drm_crtc_state *new_crtc_state;
+ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+ struct dm_crtc_state *dm_new_crtc_state;
+
+ if (!acrtc) {
+ ASSERT(0);
+ continue;
+ }
+
+ new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
+ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+ dm_new_crtc_state->freesync_enabled = enable;
+ }
+
+ ret = drm_atomic_commit(state);
+
+fail:
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ drm_atomic_state_put(state);
+
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
}
static const struct amdgpu_display_funcs dm_display_funcs = {
@@ -2552,6 +2589,10 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
dc_stream_retain(state->stream);
}
+ state->adjust = cur->adjust;
+ state->vrr_infopacket = cur->vrr_infopacket;
+ state->freesync_enabled = cur->freesync_enabled;
+
/* TODO Duplicate dc_stream after objects are stream object is flattened */
return &state->base;
@@ -2661,21 +2702,7 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
dm_new_state->underscan_enable = val;
ret = 0;
} else if (property == adev->mode_info.freesync_property) {
- struct amdgpu_crtc *acrtc;
- struct dm_crtc_state *acrtc_state;
-
- dm_new_state->user_enable.enable_for_gaming = val;
- dm_new_state->user_enable.enable_for_static = val;
- dm_new_state->user_enable.enable_for_video = val;
-
- if (adev->dm.freesync_module && connector_state->crtc) {
- acrtc = to_amdgpu_crtc(connector_state->crtc);
- acrtc_state = to_dm_crtc_state(connector_state->crtc->state);
- mod_freesync_set_user_enable(adev->dm.freesync_module,
- &acrtc_state->stream, 1,
- &dm_new_state->user_enable);
- }
-
+ dm_new_state->freesync_enable = val;
ret = 0;
} else if (property == adev->mode_info.freesync_capable_property) {
dm_new_state->freesync_capable = val;
@@ -2723,7 +2750,7 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
*val = dm_state->underscan_enable;
ret = 0;
} else if (property == adev->mode_info.freesync_property) {
- *val = dm_state->user_enable.enable_for_gaming;
+ *val = dm_state->freesync_enable;
ret = 0;
} else if (property == adev->mode_info.freesync_capable_property) {
*val = dm_state->freesync_capable;
@@ -2782,13 +2809,15 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
struct dm_connector_state *new_state =
kmemdup(state, sizeof(*state), GFP_KERNEL);
- if (new_state) {
- __drm_atomic_helper_connector_duplicate_state(connector,
- &new_state->base);
- return &new_state->base;
- }
+ if (!new_state)
+ return NULL;
- return NULL;
+ __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
+
+ new_state->freesync_capable = state->freesync_capable;
+ new_state->freesync_enable = state->freesync_enable;
+
+ return &new_state->base;
}
static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
@@ -3545,10 +3574,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
drm_object_attach_property(&aconnector->base.base,
- adev->mode_info.freesync_property, 0);
+ adev->mode_info.freesync_property, 0);
drm_object_attach_property(&aconnector->base.base,
- adev->mode_info.freesync_capable_property,
- 0);
+ adev->mode_info.freesync_capable_property, 0);
}
}
@@ -3792,8 +3820,6 @@ static void remove_stream(struct amdgpu_device *adev,
struct dc_stream_state *stream)
{
/* this is the update mode case */
- if (adev->dm.freesync_module)
- mod_freesync_remove_stream(adev->dm.freesync_module, stream);
acrtc->otg_inst = -1;
acrtc->enabled = false;
@@ -4065,6 +4091,11 @@ static bool commit_planes_to_stream(
stream_update->dst = dc_stream->dst;
stream_update->out_transfer_func = dc_stream->out_transfer_func;
+ if (dm_new_crtc_state->freesync_enabled != dm_old_crtc_state->freesync_enabled) {
+ stream_update->vrr_infopacket = &dc_stream->vrr_infopacket;
+ stream_update->adjust = &dc_stream->adjust;
+ }
+
for (i = 0; i < new_plane_count; i++) {
updates[i].surface = plane_states[i];
updates[i].gamma =
@@ -4201,6 +4232,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
}
+ dc_stream_attach->adjust = acrtc_state->adjust;
+ dc_stream_attach->vrr_infopacket = acrtc_state->vrr_infopacket;
if (false == commit_planes_to_stream(dm->dc,
plane_states_constructed,
@@ -4347,62 +4380,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
}
} /* for_each_crtc_in_state() */
- /*
- * Add streams after required streams from new and replaced streams
- * are removed from freesync module
- */
- if (adev->dm.freesync_module) {
- for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- struct amdgpu_dm_connector *aconnector = NULL;
- struct dm_connector_state *dm_new_con_state = NULL;
- struct amdgpu_crtc *acrtc = NULL;
- bool modeset_needed;
-
- dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
- dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
- modeset_needed = modeset_required(
- new_crtc_state,
- dm_new_crtc_state->stream,
- dm_old_crtc_state->stream);
- /* We add stream to freesync if:
- * 1. Said stream is not null, and
- * 2. A modeset is requested. This means that the
- * stream was removed previously, and needs to be
- * replaced.
- */
- if (dm_new_crtc_state->stream == NULL ||
- !modeset_needed)
- continue;
-
- acrtc = to_amdgpu_crtc(crtc);
-
- aconnector =
- amdgpu_dm_find_first_crtc_matching_connector(
- state, crtc);
- if (!aconnector) {
- DRM_DEBUG_DRIVER("Atomic commit: Failed to "
- "find connector for acrtc "
- "id:%d skipping freesync "
- "init\n",
- acrtc->crtc_id);
- continue;
- }
-
- mod_freesync_add_stream(adev->dm.freesync_module,
- dm_new_crtc_state->stream,
- &aconnector->caps);
- new_con_state = drm_atomic_get_new_connector_state(
- state, &aconnector->base);
- dm_new_con_state = to_dm_connector_state(new_con_state);
-
- mod_freesync_set_user_enable(adev->dm.freesync_module,
- &dm_new_crtc_state->stream,
- 1,
- &dm_new_con_state->user_enable);
- }
- }
-
if (dm_state->context) {
dm_enable_per_frame_crtc_master_sync(dm_state->context);
WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
@@ -4456,6 +4433,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
WARN_ON(!status);
WARN_ON(!status->plane_count);
+ dm_new_crtc_state->stream->adjust = dm_new_crtc_state->adjust;
+ dm_new_crtc_state->stream->vrr_infopacket = dm_new_crtc_state->vrr_infopacket;
+
/*TODO How it works with MPO ?*/
if (!commit_planes_to_stream(
dm->dc,
@@ -4485,11 +4465,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
if (dm_new_crtc_state->stream == NULL || !modeset_needed)
continue;
- if (adev->dm.freesync_module)
- mod_freesync_notify_mode_change(
- adev->dm.freesync_module,
- &dm_new_crtc_state->stream, 1);
-
manage_dm_interrupts(adev, acrtc, true);
}
@@ -4664,7 +4639,42 @@ static int do_aquire_global_lock(struct drm_device *dev,
return ret < 0 ? ret : 0;
}
-static int dm_update_crtcs_state(struct dc *dc,
+void set_freesync_on_stream(struct amdgpu_display_manager *dm,
+ struct dm_crtc_state *new_crtc_state,
+ struct dm_connector_state *new_con_state,
+ struct dc_stream_state *new_stream)
+{
+ struct mod_freesync_config config = {0};
+ struct mod_vrr_params vrr = {0};
+ struct dc_info_packet vrr_infopacket = {0};
+ struct amdgpu_dm_connector *aconnector =
+ to_amdgpu_dm_connector(new_con_state->base.connector);
+
+ if (new_con_state->freesync_capable &&
+ new_con_state->freesync_enable) {
+ config.state = new_crtc_state->freesync_enabled ?
+ VRR_STATE_ACTIVE_VARIABLE :
+ VRR_STATE_INACTIVE;
+ config.min_refresh_in_uhz =
+ aconnector->min_vfreq * 1000000;
+ config.max_refresh_in_uhz =
+ aconnector->max_vfreq * 1000000;
+ }
+
+ mod_freesync_build_vrr_params(dm->freesync_module,
+ new_stream,
+ &config, &vrr);
+
+ mod_freesync_build_vrr_infopacket(dm->freesync_module,
+ new_stream,
+ &vrr,
+ &vrr_infopacket);
+
+ new_crtc_state->adjust = vrr.adjust;
+ new_crtc_state->vrr_infopacket = vrr_infopacket;
+}
+
+static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
struct drm_atomic_state *state,
bool enable,
bool *lock_and_validation_needed)
@@ -4723,6 +4733,9 @@ static int dm_update_crtcs_state(struct dc *dc,
break;
}
+ set_freesync_on_stream(dm, dm_new_crtc_state,
+ dm_conn_state, new_stream);
+
if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
new_crtc_state->mode_changed = false;
@@ -4731,6 +4744,9 @@ static int dm_update_crtcs_state(struct dc *dc,
}
}
+ if (dm_old_crtc_state->freesync_enabled != dm_new_crtc_state->freesync_enabled)
+ new_crtc_state->mode_changed = true;
+
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
goto next_crtc;
@@ -4757,7 +4773,7 @@ static int dm_update_crtcs_state(struct dc *dc,
/* i.e. reset mode */
if (dc_remove_stream_from_ctx(
- dc,
+ dm->dc,
dm_state->context,
dm_old_crtc_state->stream) != DC_OK) {
ret = -EINVAL;
@@ -4794,7 +4810,7 @@ static int dm_update_crtcs_state(struct dc *dc,
crtc->base.id);
if (dc_add_stream_to_ctx(
- dc,
+ dm->dc,
dm_state->context,
dm_new_crtc_state->stream) != DC_OK) {
ret = -EINVAL;
@@ -4833,6 +4849,8 @@ static int dm_update_crtcs_state(struct dc *dc,
goto fail;
amdgpu_dm_set_ctm(dm_new_crtc_state);
}
+
+
}
return ret;
@@ -5025,12 +5043,16 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+ struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
ret = dm_atomic_check_plane_state_fb(state, crtc);
if (ret)
goto fail;
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
- !new_crtc_state->color_mgmt_changed)
+ !new_crtc_state->color_mgmt_changed &&
+ (dm_old_crtc_state->freesync_enabled == dm_new_crtc_state->freesync_enabled))
continue;
if (!new_crtc_state->enable)
@@ -5056,13 +5078,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
}
/* Disable all crtcs which require disable */
- ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
+ ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
if (ret) {
goto fail;
}
/* Enable all crtcs which require enable */
- ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
+ ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
if (ret) {
goto fail;
}
@@ -5155,8 +5177,8 @@ static bool is_dp_capable_without_timing_msa(struct dc *dc,
return capable;
}
-void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
- struct edid *edid)
+void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
+ struct edid *edid)
{
int i;
bool edid_check_required;
@@ -5175,6 +5197,18 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
return;
}
+ if (!edid) {
+ dm_con_state = to_dm_connector_state(connector->state);
+
+ amdgpu_dm_connector->min_vfreq = 0;
+ amdgpu_dm_connector->max_vfreq = 0;
+ amdgpu_dm_connector->pixel_clock_mhz = 0;
+
+ dm_con_state->freesync_capable = false;
+ dm_con_state->freesync_enable = false;
+ return;
+ }
+
dm_con_state = to_dm_connector_state(connector->state);
edid_check_required = false;
@@ -5225,46 +5259,10 @@ void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
}
if (amdgpu_dm_connector->max_vfreq -
- amdgpu_dm_connector->min_vfreq > 10) {
- amdgpu_dm_connector->caps.supported = true;
- amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
- amdgpu_dm_connector->min_vfreq * 1000000;
- amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
- amdgpu_dm_connector->max_vfreq * 1000000;
+ amdgpu_dm_connector->min_vfreq > 10) {
+
dm_con_state->freesync_capable = true;
}
}
}
-void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
-{
- struct amdgpu_dm_connector *amdgpu_dm_connector =
- to_amdgpu_dm_connector(connector);
- struct dm_connector_state *dm_con_state;
- struct drm_device *dev = connector->dev;
- struct amdgpu_device *adev = dev->dev_private;
-
- if (!amdgpu_dm_connector->dc_sink || !adev->dm.freesync_module) {
- DRM_ERROR("dc_sink NULL or no free_sync module.\n");
- return;
- }
-
- if (!connector->state) {
- DRM_ERROR("%s - Connector has no state", __func__);
- return;
- }
-
- dm_con_state = to_dm_connector_state(connector->state);
-
- amdgpu_dm_connector->min_vfreq = 0;
- amdgpu_dm_connector->max_vfreq = 0;
- amdgpu_dm_connector->pixel_clock_mhz = 0;
-
- memset(&amdgpu_dm_connector->caps, 0, sizeof(amdgpu_dm_connector->caps));
-
- dm_con_state->freesync_capable = false;
-
- dm_con_state->user_enable.enable_for_gaming = false;
- dm_con_state->user_enable.enable_for_static = false;
- dm_con_state->user_enable.enable_for_video = false;
-}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index b5cf468e90ae..68eb959e41d3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -193,9 +193,6 @@ struct amdgpu_dm_connector {
int max_vfreq ;
int pixel_clock_mhz;
- /*freesync caps*/
- struct mod_freesync_caps caps;
-
struct mutex hpd_lock;
bool fake_enable;
@@ -223,9 +220,13 @@ struct dm_crtc_state {
int crc_skip_count;
bool crc_enabled;
+
+ bool freesync_enabled;
+ struct dc_crtc_timing_adjust adjust;
+ struct dc_info_packet vrr_infopacket;
};
-#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
+#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
struct dm_atomic_state {
struct drm_atomic_state base;
@@ -242,7 +243,7 @@ struct dm_connector_state {
uint8_t underscan_vborder;
uint8_t underscan_hborder;
bool underscan_enable;
- struct mod_freesync_user_enable user_enable;
+ bool freesync_enable;
bool freesync_capable;
};
@@ -276,11 +277,8 @@ int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
void dm_restore_drm_connector_state(struct drm_device *dev,
struct drm_connector *connector);
-void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
- struct edid *edid);
-
-void
-amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
+void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
+ struct edid *edid);
/* amdgpu_dm_crc.c */
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 305292a9ff80..782491e73efc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -212,8 +212,9 @@ void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
dc_sink->priv = aconnector;
aconnector->dc_sink = dc_sink;
- amdgpu_dm_add_sink_to_freesync_module(
- connector, aconnector->edid);
+ if (aconnector->dc_sink)
+ amdgpu_dm_update_freesync_caps(
+ connector, aconnector->edid);
}
static int dm_dp_mst_get_modes(struct drm_connector *connector)
@@ -251,7 +252,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
aconnector->dc_sink = dc_sink;
if (aconnector->dc_sink)
- amdgpu_dm_add_sink_to_freesync_module(
+ amdgpu_dm_update_freesync_caps(
connector, edid);
drm_mode_connector_update_edid_property(
@@ -415,7 +416,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
aconnector->port = NULL;
if (aconnector->dc_sink) {
- amdgpu_dm_remove_sink_from_freesync_module(connector);
+ amdgpu_dm_update_freesync_caps(connector, NULL);
dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b331d9e78cdb..74f516903acd 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -170,11 +170,9 @@ static bool create_links(
}
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
- struct dc_stream_state **streams, int num_streams,
- int vmin, int vmax)
+ struct dc_stream_state *stream,
+ struct dc_crtc_timing_adjust *adjust)
{
- /* TODO: Support multiple streams */
- struct dc_stream_state *stream = streams[0];
int i = 0;
bool ret = false;
@@ -182,11 +180,11 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.stream_enc) {
- dc->hwss.set_drr(&pipe, 1, vmin, vmax);
-
- /* build and update the info frame */
- resource_build_info_frame(pipe);
- dc->hwss.update_info_frame(pipe);
+ pipe->stream->adjust = *adjust;
+ dc->hwss.set_drr(&pipe,
+ 1,
+ adjust->v_total_min,
+ adjust->v_total_max);
ret = true;
}
@@ -199,7 +197,7 @@ bool dc_stream_get_crtc_position(struct dc *dc,
unsigned int *v_pos, unsigned int *nom_v_pos)
{
/* TODO: Support multiple streams */
- struct dc_stream_state *stream = streams[0];
+ const struct dc_stream_state *stream = streams[0];
int i = 0;
bool ret = false;
struct crtc_position position;
@@ -1176,8 +1174,25 @@ static enum surface_update_type check_update_surfaces_for_stream(
if (stream_status == NULL || stream_status->plane_count != surface_count)
return UPDATE_TYPE_FULL;
- if (stream_update)
- return UPDATE_TYPE_FULL;
+ /* some stream updates require passive update */
+ if (stream_update) {
+ if ((stream_update->src.height != 0) &&
+ (stream_update->src.width != 0))
+ return UPDATE_TYPE_FULL;
+
+ if ((stream_update->dst.height != 0) &&
+ (stream_update->dst.width != 0))
+ return UPDATE_TYPE_FULL;
+
+ if (stream_update->out_transfer_func)
+ return UPDATE_TYPE_FULL;
+
+ if (stream_update->hdr_static_metadata)
+ return UPDATE_TYPE_FULL;
+
+ if (stream_update->abm_level)
+ return UPDATE_TYPE_FULL;
+ }
for (i = 0 ; i < surface_count; i++) {
enum surface_update_type type =
@@ -1256,7 +1271,6 @@ static void commit_planes_for_stream(struct dc *dc,
return;
}
- /* Full fe update*/
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
@@ -1267,11 +1281,22 @@ static void commit_planes_for_stream(struct dc *dc,
top_pipe_to_program = pipe_ctx;
- if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state)
+ if (!pipe_ctx->plane_state)
+ continue;
+
+ /* Fast update*/
+ // VRR program can be done as part of FAST UPDATE
+ if (stream_update && stream_update->adjust)
+ dc->hwss.set_drr(&pipe_ctx, 1,
+ stream_update->adjust->v_total_min,
+ stream_update->adjust->v_total_max);
+
+ /* Full fe update*/
+ if (update_type == UPDATE_TYPE_FAST)
continue;
stream_status =
- stream_get_status(context, pipe_ctx->stream);
+ stream_get_status(context, pipe_ctx->stream);
dc->hwss.apply_ctx_for_surface(
dc, pipe_ctx->stream, stream_status->plane_count, context);
@@ -1326,7 +1351,7 @@ static void commit_planes_for_stream(struct dc *dc,
dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
}
- if (stream && stream_update && update_type > UPDATE_TYPE_FAST)
+ if (stream && stream_update)
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx =
&context->res_ctx.pipe_ctx[j];
@@ -1334,7 +1359,8 @@ static void commit_planes_for_stream(struct dc *dc,
if (pipe_ctx->stream != stream)
continue;
- if (stream_update->hdr_static_metadata) {
+ if (stream_update->hdr_static_metadata ||
+ (stream_update->vrr_infopacket)) {
resource_build_info_frame(pipe_ctx);
dc->hwss.update_info_frame(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index b86325bb636f..e103ce8e0558 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2327,6 +2327,9 @@ static bool retrieve_link_cap(struct dc_link *link)
dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
+ down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
+ DP_DPCD_REV];
+
link->dpcd_caps.allow_invalid_MSA_timing_param =
down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 50b84f69bd25..1de8f5518782 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2188,119 +2188,13 @@ static void set_spd_info_packet(
{
/* SPD info packet for FreeSync */
- unsigned char checksum = 0;
- unsigned int idx, payload_size = 0;
-
/* Check if Freesync is supported. Return if false. If true,
* set the corresponding bit in the info packet
*/
- if (stream->freesync_ctx.supported == false)
+ if (!stream->vrr_infopacket.valid)
return;
- if (dc_is_hdmi_signal(stream->signal)) {
-
- /* HEADER */
-
- /* HB0 = Packet Type = 0x83 (Source Product
- * Descriptor InfoFrame)
- */
- info_packet->hb0 = HDMI_INFOFRAME_TYPE_SPD;
-
- /* HB1 = Version = 0x01 */
- info_packet->hb1 = 0x01;
-
- /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
- info_packet->hb2 = 0x08;
-
- payload_size = 0x08;
-
- } else if (dc_is_dp_signal(stream->signal)) {
-
- /* HEADER */
-
- /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
- * when used to associate audio related info packets
- */
- info_packet->hb0 = 0x00;
-
- /* HB1 = Packet Type = 0x83 (Source Product
- * Descriptor InfoFrame)
- */
- info_packet->hb1 = HDMI_INFOFRAME_TYPE_SPD;
-
- /* HB2 = [Bits 7:0 = Least significant eight bits -
- * For INFOFRAME, the value must be 1Bh]
- */
- info_packet->hb2 = 0x1B;
-
- /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
- * [Bits 1:0 = Most significant two bits = 0x00]
- */
- info_packet->hb3 = 0x04;
-
- payload_size = 0x1B;
- }
-
- /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
- info_packet->sb[1] = 0x1A;
-
- /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
- info_packet->sb[2] = 0x00;
-
- /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
- info_packet->sb[3] = 0x00;
-
- /* PB4 = Reserved */
- info_packet->sb[4] = 0x00;
-
- /* PB5 = Reserved */
- info_packet->sb[5] = 0x00;
-
- /* PB6 = [Bits 7:3 = Reserved] */
- info_packet->sb[6] = 0x00;
-
- if (stream->freesync_ctx.supported == true)
- /* PB6 = [Bit 0 = FreeSync Supported] */
- info_packet->sb[6] |= 0x01;
-
- if (stream->freesync_ctx.enabled == true)
- /* PB6 = [Bit 1 = FreeSync Enabled] */
- info_packet->sb[6] |= 0x02;
-
- if (stream->freesync_ctx.active == true)
- /* PB6 = [Bit 2 = FreeSync Active] */
- info_packet->sb[6] |= 0x04;
-
- /* PB7 = FreeSync Minimum refresh rate (Hz) */
- info_packet->sb[7] = (unsigned char) (stream->freesync_ctx.
- min_refresh_in_micro_hz / 1000000);
-
- /* PB8 = FreeSync Maximum refresh rate (Hz)
- *
- * Note: We do not use the maximum capable refresh rate
- * of the panel, because we should never go above the field
- * rate of the mode timing set.
- */
- info_packet->sb[8] = (unsigned char) (stream->freesync_ctx.
- nominal_refresh_in_micro_hz / 1000000);
-
- /* PB9 - PB27 = Reserved */
- for (idx = 9; idx <= 27; idx++)
- info_packet->sb[idx] = 0x00;
-
- /* Calculate checksum */
- checksum += info_packet->hb0;
- checksum += info_packet->hb1;
- checksum += info_packet->hb2;
- checksum += info_packet->hb3;
-
- for (idx = 1; idx <= payload_size; idx++)
- checksum += info_packet->sb[idx];
-
- /* PB0 = Checksum (one byte complement) */
- info_packet->sb[0] = (unsigned char) (0x100 - checksum);
-
- info_packet->valid = true;
+ *info_packet = stream->vrr_infopacket;
}
static void set_hdr_static_info_packet(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index b83a7dc2f5a9..5472316822ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -692,12 +692,6 @@ struct crtc_trigger_info {
enum trigger_delay delay;
};
-enum vrr_state {
- VRR_STATE_OFF = 0,
- VRR_STATE_VARIABLE,
- VRR_STATE_FIXED,
-};
-
struct dc_crtc_timing_adjust {
uint32_t v_total_min;
uint32_t v_total_max;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 2971cd07e093..ca437e1412f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -45,19 +45,25 @@ struct dc_stream_status {
struct dc_link *link;
};
+// TODO: References to this needs to be removed..
+struct freesync_context {
+ bool dummy;
+};
+
struct dc_stream_state {
struct dc_sink *sink;
struct dc_crtc_timing timing;
- struct dc_crtc_timing_adjust timing_adjust;
- struct vrr_params vrr_params;
+ struct dc_crtc_timing_adjust adjust;
+ struct dc_info_packet vrr_infopacket;
struct rect src; /* composition area */
struct rect dst; /* stream addressable area */
- struct audio_info audio_info;
-
+ // TODO: References to this needs to be removed..
struct freesync_context freesync_ctx;
+ struct audio_info audio_info;
+
struct dc_hdr_static_metadata hdr_static_metadata;
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
@@ -117,6 +123,8 @@ struct dc_stream_update {
enum color_transfer_func color_output_tf;
unsigned int *abm_level;
unsigned long long *periodic_fn_vsync_delta;
+ struct dc_crtc_timing_adjust *adjust;
+ struct dc_info_packet *vrr_infopacket;
};
bool dc_is_stream_unchanged(
@@ -257,10 +265,8 @@ bool dc_stream_set_cursor_position(
const struct dc_cursor_position *position);
bool dc_stream_adjust_vmin_vmax(struct dc *dc,
- struct dc_stream_state **stream,
- int num_streams,
- int vmin,
- int vmax);
+ struct dc_stream_state *stream,
+ struct dc_crtc_timing_adjust *adjust);
bool dc_stream_get_crtc_position(struct dc *dc,
struct dc_stream_state **stream,
@@ -287,13 +293,6 @@ void dc_stream_set_static_screen_events(struct dc *dc,
void dc_stream_set_dither_option(struct dc_stream_state *stream,
enum dc_dither_option option);
-
-bool dc_stream_adjust_vmin_vmax(struct dc *dc,
- struct dc_stream_state **stream,
- int num_streams,
- int vmin,
- int vmax);
-
bool dc_stream_get_crtc_position(struct dc *dc,
struct dc_stream_state **stream,
int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index cd324bcc45e8..90f40eecc2bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -521,13 +521,11 @@ struct audio_info {
struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
};
-struct vrr_params {
- enum vrr_state state;
- uint32_t window_min;
- uint32_t window_max;
- uint32_t inserted_frame_duration_in_us;
- uint32_t frames_to_insert;
- uint32_t frame_counter;
+enum dc_infoframe_type {
+ DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
+ DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
+ DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
+ DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
};
struct dc_info_packet {
@@ -547,16 +545,6 @@ struct dc_plane_flip_time {
unsigned int prev_update_time_in_us;
};
-// Will combine with vrr_params at some point.
-struct freesync_context {
- bool supported;
- bool enabled;
- bool active;
-
- unsigned int min_refresh_in_micro_hz;
- unsigned int nominal_refresh_in_micro_hz;
-};
-
struct psr_config {
unsigned char psr_version;
unsigned int psr_rfb_setup_time;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index db2d15dfb831..432bed63ea4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1235,6 +1235,8 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
pipe_ctx[pipe_ctx->pipe_idx];
struct tg_color black_color = {0};
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0;
if (!pipe_ctx_old->stream) {
@@ -1264,9 +1266,19 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
&stream->timing,
true);
- pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
- pipe_ctx->stream_res.tg,
- 0x182);
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+ if (pipe_ctx->stream_res.tg->funcs->set_drr)
+ pipe_ctx->stream_res.tg->funcs->set_drr(
+ pipe_ctx->stream_res.tg, ¶ms);
+
+ // DRR should set trigger event to monitor surface update event
+ if (stream->adjust.v_total_min != 0 &&
+ stream->adjust.v_total_max != 0)
+ event_triggers = 0x80;
+ if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
+ pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
+ pipe_ctx->stream_res.tg, event_triggers);
}
if (!pipe_ctx_old->stream) {
@@ -1277,8 +1289,6 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
}
}
-
-
return DC_OK;
}
@@ -1627,16 +1637,24 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
{
int i = 0;
struct drr_params params = {0};
+ // DRR should set trigger event to monitor surface update event
+ unsigned int event_triggers = 0x80;
params.vertical_total_max = vmax;
params.vertical_total_min = vmin;
/* TODO: If multiple pipes are to be supported, you need
- * some GSL stuff
+ * some GSL stuff. Static screen triggers may be programmed differently
+ * as well.
*/
-
for (i = 0; i < num_pipes; i++) {
- pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms);
+ pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+ pipe_ctx[i]->stream_res.tg, ¶ms);
+
+ if (vmax != 0 && vmin != 0)
+ pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+ pipe_ctx[i]->stream_res.tg,
+ event_triggers);
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f3341a2399fa..dfa6ad5078b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -480,6 +480,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space;
struct tg_color black_color = {0};
+ struct drr_params params = {0};
+ unsigned int event_triggers = 0;
/* by upper caller loop, pipe0 is parent pipe and be called first.
* back end is set up by for pipe0. Other children pipe share back end
@@ -547,6 +549,19 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
return DC_ERROR_UNEXPECTED;
}
+ params.vertical_total_min = stream->adjust.v_total_min;
+ params.vertical_total_max = stream->adjust.v_total_max;
+ if (pipe_ctx->stream_res.tg->funcs->set_drr)
+ pipe_ctx->stream_res.tg->funcs->set_drr(
+ pipe_ctx->stream_res.tg, ¶ms);
+
+ // DRR should set trigger event to monitor surface update event
+ if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
+ event_triggers = 0x80;
+ if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
+ pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
+ pipe_ctx->stream_res.tg, event_triggers);
+
/* TODO program crtc source select for non-virtual signal*/
/* TODO program FMT */
/* TODO setup link_enc */
@@ -2313,15 +2328,23 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
{
int i = 0;
struct drr_params params = {0};
+ // DRR should set trigger event to monitor surface update event
+ unsigned int event_triggers = 0x80;
params.vertical_total_max = vmax;
params.vertical_total_min = vmin;
/* TODO: If multiple pipes are to be supported, you need
- * some GSL stuff
+ * some GSL stuff. Static screen triggers may be programmed differently
+ * as well.
*/
for (i = 0; i < num_pipes; i++) {
- pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, ¶ms);
+ pipe_ctx[i]->stream_res.tg->funcs->set_drr(
+ pipe_ctx[i]->stream_res.tg, ¶ms);
+ if (vmax != 0 && vmin != 0)
+ pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
+ pipe_ctx[i]->stream_res.tg,
+ event_triggers);
}
}
diff --git a/drivers/gpu/drm/amd/display/include/set_mode_types.h b/drivers/gpu/drm/amd/display/include/set_mode_types.h
index fee2b6ffcfc1..2b836e582c08 100644
--- a/drivers/gpu/drm/amd/display/include/set_mode_types.h
+++ b/drivers/gpu/drm/amd/display/include/set_mode_types.h
@@ -90,18 +90,6 @@ union hdmi_info_packet {
struct info_packet_raw_data packet_raw_data;
};
-struct info_packet {
- enum info_frame_flag flags;
- union hdmi_info_packet info_packet_hdmi;
-};
-
-struct info_frame {
- struct info_packet avi_info_packet;
- struct info_packet gamut_packet;
- struct info_packet vendor_info_packet;
- struct info_packet spd_info_packet;
-};
-
#pragma pack(pop)
#endif /* __DAL_SET_MODE_TYPES_H__ */
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 27d4003aa2c7..5e12e463c06a 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -30,6 +30,7 @@
#define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
+#define MIN_REFRESH_RANGE_IN_US 10000000
/* Refresh rate ramp at a fixed rate of 65 Hz/second */
#define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
/* Number of elements in the render times cache array */
@@ -40,103 +41,9 @@
#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
-#define FREESYNC_REGISTRY_NAME "freesync_v1"
-
-#define FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY "DalFreeSyncNoStaticForExternalDp"
-
-#define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal"
-
-#define FREESYNC_DEFAULT_REGKEY "LCDFreeSyncDefault"
-
-struct gradual_static_ramp {
- bool ramp_is_active;
- bool ramp_direction_is_up;
- unsigned int ramp_current_frame_duration_in_ns;
-};
-
-struct freesync_time {
- /* video (48Hz feature) related */
- unsigned int update_duration_in_ns;
-
- /* BTR/fixed refresh related */
- unsigned int prev_time_stamp_in_us;
-
- unsigned int min_render_time_in_us;
- unsigned int max_render_time_in_us;
-
- unsigned int render_times_index;
- unsigned int render_times[RENDER_TIMES_MAX_COUNT];
-
- unsigned int min_window;
- unsigned int max_window;
-};
-
-struct below_the_range {
- bool btr_active;
- bool program_btr;
-
- unsigned int mid_point_in_us;
-
- unsigned int inserted_frame_duration_in_us;
- unsigned int frames_to_insert;
- unsigned int frame_counter;
-};
-
-struct fixed_refresh {
- bool fixed_active;
- bool program_fixed;
- unsigned int frame_counter;
-};
-
-struct freesync_range {
- unsigned int min_refresh;
- unsigned int max_frame_duration;
- unsigned int vmax;
-
- unsigned int max_refresh;
- unsigned int min_frame_duration;
- unsigned int vmin;
-};
-
-struct freesync_state {
- bool fullscreen;
- bool static_screen;
- bool video;
-
- unsigned int vmin;
- unsigned int vmax;
-
- struct freesync_time time;
-
- unsigned int nominal_refresh_rate_in_micro_hz;
- bool windowed_fullscreen;
-
- struct gradual_static_ramp static_ramp;
- struct below_the_range btr;
- struct fixed_refresh fixed_refresh;
- struct freesync_range freesync_range;
-};
-
-struct freesync_entity {
- struct dc_stream_state *stream;
- struct mod_freesync_caps *caps;
- struct freesync_state state;
- struct mod_freesync_user_enable user_enable;
-};
-
-struct freesync_registry_options {
- bool drr_external_supported;
- bool drr_internal_supported;
- bool lcd_freesync_default_set;
- int lcd_freesync_default_value;
-};
-
struct core_freesync {
struct mod_freesync public;
struct dc *dc;
- struct freesync_registry_options opts;
- struct freesync_entity *map;
- int num_entities;
};
#define MOD_FREESYNC_TO_CORE(mod_freesync)\
@@ -147,68 +54,16 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
struct core_freesync *core_freesync =
kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
-
- struct persistent_data_flag flag;
-
- int i, data = 0;
-
if (core_freesync == NULL)
goto fail_alloc_context;
- core_freesync->map = kzalloc(sizeof(struct freesync_entity) * MOD_FREESYNC_MAX_CONCURRENT_STREAMS,
- GFP_KERNEL);
-
- if (core_freesync->map == NULL)
- goto fail_alloc_map;
-
- for (i = 0; i < MOD_FREESYNC_MAX_CONCURRENT_STREAMS; i++)
- core_freesync->map[i].stream = NULL;
-
- core_freesync->num_entities = 0;
-
if (dc == NULL)
goto fail_construct;
core_freesync->dc = dc;
-
- /* Create initial module folder in registry for freesync enable data */
- flag.save_per_edid = true;
- flag.save_per_link = false;
- dm_write_persistent_data(dc->ctx, NULL, FREESYNC_REGISTRY_NAME,
- NULL, NULL, 0, &flag);
- flag.save_per_edid = false;
- flag.save_per_link = false;
-
- if (dm_read_persistent_data(dc->ctx, NULL, NULL,
- FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY,
- &data, sizeof(data), &flag)) {
- core_freesync->opts.drr_internal_supported =
- (data & 1) ? false : true;
- }
-
- if (dm_read_persistent_data(dc->ctx, NULL, NULL,
- FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY,
- &data, sizeof(data), &flag)) {
- core_freesync->opts.drr_external_supported =
- (data & 1) ? false : true;
- }
-
- if (dm_read_persistent_data(dc->ctx, NULL, NULL,
- FREESYNC_DEFAULT_REGKEY,
- &data, sizeof(data), &flag)) {
- core_freesync->opts.lcd_freesync_default_set = true;
- core_freesync->opts.lcd_freesync_default_value = data;
- } else {
- core_freesync->opts.lcd_freesync_default_set = false;
- core_freesync->opts.lcd_freesync_default_value = 0;
- }
-
return &core_freesync->public;
fail_construct:
- kfree(core_freesync->map);
-
-fail_alloc_map:
kfree(core_freesync);
fail_alloc_context:
@@ -217,968 +72,396 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
void mod_freesync_destroy(struct mod_freesync *mod_freesync)
{
- if (mod_freesync != NULL) {
- int i;
- struct core_freesync *core_freesync =
- MOD_FREESYNC_TO_CORE(mod_freesync);
-
- for (i = 0; i < core_freesync->num_entities; i++)
- if (core_freesync->map[i].stream)
- dc_stream_release(core_freesync->map[i].stream);
-
- kfree(core_freesync->map);
-
- kfree(core_freesync);
- }
-}
-
-/* Given a specific dc_stream* this function finds its equivalent
- * on the core_freesync->map and returns the corresponding index
- */
-static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
- struct dc_stream_state *stream)
-{
- unsigned int index = 0;
-
- for (index = 0; index < core_freesync->num_entities; index++) {
- if (core_freesync->map[index].stream == stream) {
- return index;
- }
- }
- /* Could not find stream requested */
- ASSERT(false);
- return index;
-}
-
-bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream, struct mod_freesync_caps *caps)
-{
- struct dc *dc = NULL;
struct core_freesync *core_freesync = NULL;
- int persistent_freesync_enable = 0;
- struct persistent_data_flag flag;
- unsigned int nom_refresh_rate_uhz;
- unsigned long long temp;
-
if (mod_freesync == NULL)
- return false;
-
+ return;
core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- dc = core_freesync->dc;
-
- flag.save_per_edid = true;
- flag.save_per_link = false;
-
- if (core_freesync->num_entities < MOD_FREESYNC_MAX_CONCURRENT_STREAMS) {
-
- dc_stream_retain(stream);
-
- temp = stream->timing.pix_clk_khz;
- temp *= 1000ULL * 1000ULL * 1000ULL;
- temp = div_u64(temp, stream->timing.h_total);
- temp = div_u64(temp, stream->timing.v_total);
-
- nom_refresh_rate_uhz = (unsigned int) temp;
-
- core_freesync->map[core_freesync->num_entities].stream = stream;
- core_freesync->map[core_freesync->num_entities].caps = caps;
-
- core_freesync->map[core_freesync->num_entities].state.
- fullscreen = false;
- core_freesync->map[core_freesync->num_entities].state.
- static_screen = false;
- core_freesync->map[core_freesync->num_entities].state.
- video = false;
- core_freesync->map[core_freesync->num_entities].state.time.
- update_duration_in_ns = 0;
- core_freesync->map[core_freesync->num_entities].state.
- static_ramp.ramp_is_active = false;
-
- /* get persistent data from registry */
- if (dm_read_persistent_data(dc->ctx, stream->sink,
- FREESYNC_REGISTRY_NAME,
- "userenable", &persistent_freesync_enable,
- sizeof(int), &flag)) {
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_gaming =
- (persistent_freesync_enable & 1) ? true : false;
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_static =
- (persistent_freesync_enable & 2) ? true : false;
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_video =
- (persistent_freesync_enable & 4) ? true : false;
- /* If FreeSync display and LCDFreeSyncDefault is set, use as default values write back to userenable */
- } else if (caps->supported && (core_freesync->opts.lcd_freesync_default_set)) {
- core_freesync->map[core_freesync->num_entities].user_enable.enable_for_gaming =
- (core_freesync->opts.lcd_freesync_default_value & 1) ? true : false;
- core_freesync->map[core_freesync->num_entities].user_enable.enable_for_static =
- (core_freesync->opts.lcd_freesync_default_value & 2) ? true : false;
- core_freesync->map[core_freesync->num_entities].user_enable.enable_for_video =
- (core_freesync->opts.lcd_freesync_default_value & 4) ? true : false;
- dm_write_persistent_data(dc->ctx, stream->sink,
- FREESYNC_REGISTRY_NAME,
- "userenable", &core_freesync->opts.lcd_freesync_default_value,
- sizeof(int), &flag);
- } else {
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_gaming = false;
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_static = false;
- core_freesync->map[core_freesync->num_entities].user_enable.
- enable_for_video = false;
- }
-
- if (caps->supported &&
- nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz &&
- nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz)
- stream->ignore_msa_timing_param = 1;
-
- core_freesync->num_entities++;
- return true;
- }
- return false;
+ kfree(core_freesync);
}
-bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream)
+#if 0 /* unused currently */
+static unsigned int calc_refresh_in_uhz_from_duration(
+ unsigned int duration_in_ns)
{
- int i = 0;
- struct core_freesync *core_freesync = NULL;
- unsigned int index = 0;
-
- if (mod_freesync == NULL)
- return false;
+ unsigned int refresh_in_uhz =
+ ((unsigned int)(div64_u64((1000000000ULL * 1000000),
+ duration_in_ns)));
+ return refresh_in_uhz;
+}
+#endif
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- dc_stream_release(core_freesync->map[index].stream);
- core_freesync->map[index].stream = NULL;
- /* To remove this entity, shift everything after down */
- for (i = index; i < core_freesync->num_entities - 1; i++)
- core_freesync->map[i] = core_freesync->map[i + 1];
- core_freesync->num_entities--;
- return true;
+static unsigned int calc_duration_in_us_from_refresh_in_uhz(
+ unsigned int refresh_in_uhz)
+{
+ unsigned int duration_in_us =
+ ((unsigned int)(div64_u64((1000000000ULL * 1000),
+ refresh_in_uhz)));
+ return duration_in_us;
}
-static void adjust_vmin_vmax(struct core_freesync *core_freesync,
- struct dc_stream_state **streams,
- int num_streams,
- int map_index,
- unsigned int v_total_min,
- unsigned int v_total_max)
+static unsigned int calc_duration_in_us_from_v_total(
+ const struct dc_stream_state *stream,
+ const struct mod_vrr_params *in_vrr,
+ unsigned int v_total)
{
- if (num_streams == 0 || streams == NULL || num_streams > 1)
- return;
+ unsigned int duration_in_us =
+ (unsigned int)(div64_u64(((unsigned long long)(v_total)
+ * 1000) * stream->timing.h_total,
+ stream->timing.pix_clk_khz));
- core_freesync->map[map_index].state.vmin = v_total_min;
- core_freesync->map[map_index].state.vmax = v_total_max;
+ if (duration_in_us < in_vrr->min_duration_in_us)
+ duration_in_us = in_vrr->min_duration_in_us;
- dc_stream_adjust_vmin_vmax(core_freesync->dc, streams,
- num_streams, v_total_min,
- v_total_max);
-}
+ if (duration_in_us > in_vrr->max_duration_in_us)
+ duration_in_us = in_vrr->max_duration_in_us;
+ return duration_in_us;
+}
-static void update_stream_freesync_context(struct core_freesync *core_freesync,
- struct dc_stream_state *stream)
+static unsigned int calc_v_total_from_refresh(
+ const struct dc_stream_state *stream,
+ unsigned int refresh_in_uhz)
{
- unsigned int index;
- struct freesync_context *ctx;
+ unsigned int v_total = stream->timing.v_total;
+ unsigned int frame_duration_in_ns;
- ctx = &stream->freesync_ctx;
+ frame_duration_in_ns =
+ ((unsigned int)(div64_u64((1000000000ULL * 1000000),
+ refresh_in_uhz)));
- index = map_index_from_stream(core_freesync, stream);
+ v_total = div64_u64(div64_u64(((unsigned long long)(
+ frame_duration_in_ns) * stream->timing.pix_clk_khz),
+ stream->timing.h_total), 1000000);
- ctx->supported = core_freesync->map[index].caps->supported;
- ctx->enabled = (core_freesync->map[index].user_enable.enable_for_gaming ||
- core_freesync->map[index].user_enable.enable_for_video ||
- core_freesync->map[index].user_enable.enable_for_static);
- ctx->active = (core_freesync->map[index].state.fullscreen ||
- core_freesync->map[index].state.video ||
- core_freesync->map[index].state.static_ramp.ramp_is_active);
- ctx->min_refresh_in_micro_hz =
- core_freesync->map[index].caps->min_refresh_in_micro_hz;
- ctx->nominal_refresh_in_micro_hz = core_freesync->
- map[index].state.nominal_refresh_rate_in_micro_hz;
+ /* v_total cannot be less than nominal */
+ if (v_total < stream->timing.v_total) {
+ ASSERT(v_total < stream->timing.v_total);
+ v_total = stream->timing.v_total;
+ }
+ return v_total;
}
-static void update_stream(struct core_freesync *core_freesync,
- struct dc_stream_state *stream)
+static unsigned int calc_v_total_from_duration(
+ const struct dc_stream_state *stream,
+ const struct mod_vrr_params *vrr,
+ unsigned int duration_in_us)
{
- unsigned int index = map_index_from_stream(core_freesync, stream);
- if (core_freesync->map[index].caps->supported) {
- stream->ignore_msa_timing_param = 1;
- update_stream_freesync_context(core_freesync, stream);
- }
-}
+ unsigned int v_total = 0;
-static void calc_freesync_range(struct core_freesync *core_freesync,
- struct dc_stream_state *stream,
- struct freesync_state *state,
- unsigned int min_refresh_in_uhz,
- unsigned int max_refresh_in_uhz)
-{
- unsigned int min_frame_duration_in_ns = 0, max_frame_duration_in_ns = 0;
- unsigned int index = map_index_from_stream(core_freesync, stream);
- uint32_t vtotal = stream->timing.v_total;
-
- if ((min_refresh_in_uhz == 0) || (max_refresh_in_uhz == 0)) {
- state->freesync_range.min_refresh =
- state->nominal_refresh_rate_in_micro_hz;
- state->freesync_range.max_refresh =
- state->nominal_refresh_rate_in_micro_hz;
+ if (duration_in_us < vrr->min_duration_in_us)
+ duration_in_us = vrr->min_duration_in_us;
- state->freesync_range.max_frame_duration = 0;
- state->freesync_range.min_frame_duration = 0;
+ if (duration_in_us > vrr->max_duration_in_us)
+ duration_in_us = vrr->max_duration_in_us;
- state->freesync_range.vmax = vtotal;
- state->freesync_range.vmin = vtotal;
-
- return;
- }
+ v_total = div64_u64(div64_u64(((unsigned long long)(
+ duration_in_us) * stream->timing.pix_clk_khz),
+ stream->timing.h_total), 1000);
- min_frame_duration_in_ns = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- max_refresh_in_uhz)));
- max_frame_duration_in_ns = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- min_refresh_in_uhz)));
-
- state->freesync_range.min_refresh = min_refresh_in_uhz;
- state->freesync_range.max_refresh = max_refresh_in_uhz;
-
- state->freesync_range.max_frame_duration = max_frame_duration_in_ns;
- state->freesync_range.min_frame_duration = min_frame_duration_in_ns;
-
- state->freesync_range.vmax = div64_u64(div64_u64(((unsigned long long)(
- max_frame_duration_in_ns) * stream->timing.pix_clk_khz),
- stream->timing.h_total), 1000000);
- state->freesync_range.vmin = div64_u64(div64_u64(((unsigned long long)(
- min_frame_duration_in_ns) * stream->timing.pix_clk_khz),
- stream->timing.h_total), 1000000);
-
- /* vmin/vmax cannot be less than vtotal */
- if (state->freesync_range.vmin < vtotal) {
- /* Error of 1 is permissible */
- ASSERT((state->freesync_range.vmin + 1) >= vtotal);
- state->freesync_range.vmin = vtotal;
+ /* v_total cannot be less than nominal */
+ if (v_total < stream->timing.v_total) {
+ ASSERT(v_total < stream->timing.v_total);
+ v_total = stream->timing.v_total;
}
- if (state->freesync_range.vmax < vtotal) {
- /* Error of 1 is permissible */
- ASSERT((state->freesync_range.vmax + 1) >= vtotal);
- state->freesync_range.vmax = vtotal;
- }
-
- /* Determine whether BTR can be supported */
- if (max_frame_duration_in_ns >=
- 2 * min_frame_duration_in_ns)
- core_freesync->map[index].caps->btr_supported = true;
- else
- core_freesync->map[index].caps->btr_supported = false;
-
- /* Cache the time variables */
- state->time.max_render_time_in_us =
- max_frame_duration_in_ns / 1000;
- state->time.min_render_time_in_us =
- min_frame_duration_in_ns / 1000;
- state->btr.mid_point_in_us =
- (max_frame_duration_in_ns +
- min_frame_duration_in_ns) / 2000;
+ return v_total;
}
-static void calc_v_total_from_duration(struct dc_stream_state *stream,
- unsigned int duration_in_ns, int *v_total_nominal)
+static void update_v_total_for_static_ramp(
+ struct core_freesync *core_freesync,
+ const struct dc_stream_state *stream,
+ struct mod_vrr_params *in_out_vrr)
{
- *v_total_nominal = div64_u64(div64_u64(((unsigned long long)(
- duration_in_ns) * stream->timing.pix_clk_khz),
- stream->timing.h_total), 1000000);
-}
-
-static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync,
- struct dc_stream_state *stream,
- unsigned int index, int *v_total)
-{
- unsigned int frame_duration = 0;
-
- struct gradual_static_ramp *static_ramp_variables =
- &core_freesync->map[index].state.static_ramp;
+ unsigned int v_total = 0;
+ unsigned int current_duration_in_us =
+ calc_duration_in_us_from_v_total(
+ stream, in_out_vrr,
+ in_out_vrr->adjust.v_total_max);
+ unsigned int target_duration_in_us =
+ calc_duration_in_us_from_refresh_in_uhz(
+ in_out_vrr->fixed.target_refresh_in_uhz);
+ bool ramp_direction_is_up = (current_duration_in_us >
+ target_duration_in_us) ? true : false;
/* Calc ratio between new and current frame duration with 3 digit */
unsigned int frame_duration_ratio = div64_u64(1000000,
(1000 + div64_u64(((unsigned long long)(
STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
- static_ramp_variables->ramp_current_frame_duration_in_ns),
- 1000000000)));
+ current_duration_in_us),
+ 1000000)));
- /* Calculate delta between new and current frame duration in ns */
+ /* Calculate delta between new and current frame duration in us */
unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
- static_ramp_variables->ramp_current_frame_duration_in_ns) *
+ current_duration_in_us) *
(1000 - frame_duration_ratio)), 1000);
/* Adjust frame duration delta based on ratio between current and
* standard frame duration (frame duration at 60 Hz refresh rate).
*/
unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
- frame_duration_delta) * static_ramp_variables->
- ramp_current_frame_duration_in_ns), 16666666);
+ frame_duration_delta) * current_duration_in_us), 16666);
/* Going to a higher refresh rate (lower frame duration) */
- if (static_ramp_variables->ramp_direction_is_up) {
+ if (ramp_direction_is_up) {
/* reduce frame duration */
- static_ramp_variables->ramp_current_frame_duration_in_ns -=
- ramp_rate_interpolated;
-
- /* min frame duration */
- frame_duration = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- core_freesync->map[index].state.
- nominal_refresh_rate_in_micro_hz)));
+ current_duration_in_us -= ramp_rate_interpolated;
/* adjust for frame duration below min */
- if (static_ramp_variables->ramp_current_frame_duration_in_ns <=
- frame_duration) {
-
- static_ramp_variables->ramp_is_active = false;
- static_ramp_variables->
- ramp_current_frame_duration_in_ns =
- frame_duration;
+ if (current_duration_in_us <= target_duration_in_us) {
+ in_out_vrr->fixed.ramping_active = false;
+ in_out_vrr->fixed.ramping_done = true;
+ current_duration_in_us =
+ calc_duration_in_us_from_refresh_in_uhz(
+ in_out_vrr->fixed.target_refresh_in_uhz);
}
/* Going to a lower refresh rate (larger frame duration) */
} else {
/* increase frame duration */
- static_ramp_variables->ramp_current_frame_duration_in_ns +=
- ramp_rate_interpolated;
-
- /* max frame duration */
- frame_duration = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- core_freesync->map[index].caps->min_refresh_in_micro_hz)));
+ current_duration_in_us += ramp_rate_interpolated;
/* adjust for frame duration above max */
- if (static_ramp_variables->ramp_current_frame_duration_in_ns >=
- frame_duration) {
-
- static_ramp_variables->ramp_is_active = false;
- static_ramp_variables->
- ramp_current_frame_duration_in_ns =
- frame_duration;
+ if (current_duration_in_us >= target_duration_in_us) {
+ in_out_vrr->fixed.ramping_active = false;
+ in_out_vrr->fixed.ramping_done = true;
+ current_duration_in_us =
+ calc_duration_in_us_from_refresh_in_uhz(
+ in_out_vrr->fixed.target_refresh_in_uhz);
}
}
- calc_v_total_from_duration(stream, static_ramp_variables->
- ramp_current_frame_duration_in_ns, v_total);
-}
-
-static void reset_freesync_state_variables(struct freesync_state* state)
-{
- state->static_ramp.ramp_is_active = false;
- if (state->nominal_refresh_rate_in_micro_hz)
- state->static_ramp.ramp_current_frame_duration_in_ns =
- ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- state->nominal_refresh_rate_in_micro_hz)));
-
- state->btr.btr_active = false;
- state->btr.frame_counter = 0;
- state->btr.frames_to_insert = 0;
- state->btr.inserted_frame_duration_in_us = 0;
- state->btr.program_btr = false;
-
- state->fixed_refresh.fixed_active = false;
- state->fixed_refresh.program_fixed = false;
-}
-/*
- * Sets freesync mode on a stream depending on current freesync state.
- */
-static bool set_freesync_on_streams(struct core_freesync *core_freesync,
- struct dc_stream_state **streams, int num_streams)
-{
- int v_total_nominal = 0, v_total_min = 0, v_total_max = 0;
- unsigned int stream_idx, map_index = 0;
- struct freesync_state *state;
+ v_total = calc_v_total_from_duration(stream,
+ in_out_vrr,
+ current_duration_in_us);
- if (num_streams == 0 || streams == NULL || num_streams > 1)
- return false;
- for (stream_idx = 0; stream_idx < num_streams; stream_idx++) {
-
- map_index = map_index_from_stream(core_freesync,
- streams[stream_idx]);
-
- state = &core_freesync->map[map_index].state;
-
- if (core_freesync->map[map_index].caps->supported) {
-
- /* Fullscreen has the topmost priority. If the
- * fullscreen bit is set, we are in a fullscreen
- * application where it should not matter if it is
- * static screen. We should not check the static_screen
- * or video bit.
- *
- * Special cases of fullscreen include btr and fixed
- * refresh. We program btr on every flip and involves
- * programming full range right before the last inserted frame.
- * However, we do not want to program the full freesync range
- * when fixed refresh is active, because we only program
- * that logic once and this will override it.
- */
- if (core_freesync->map[map_index].user_enable.
- enable_for_gaming == true &&
- state->fullscreen == true &&
- state->fixed_refresh.fixed_active == false) {
- /* Enable freesync */
-
- v_total_min = state->freesync_range.vmin;
- v_total_max = state->freesync_range.vmax;
-
- /* Update the freesync context for the stream */
- update_stream_freesync_context(core_freesync,
- streams[stream_idx]);
-
- adjust_vmin_vmax(core_freesync, streams,
- num_streams, map_index,
- v_total_min,
- v_total_max);
-
- return true;
-
- } else if (core_freesync->map[map_index].user_enable.
- enable_for_video && state->video == true) {
- /* Enable 48Hz feature */
-
- calc_v_total_from_duration(streams[stream_idx],
- state->time.update_duration_in_ns,
- &v_total_nominal);
-
- /* Program only if v_total_nominal is in range*/
- if (v_total_nominal >=
- streams[stream_idx]->timing.v_total) {
-
- /* Update the freesync context for
- * the stream
- */
- update_stream_freesync_context(
- core_freesync,
- streams[stream_idx]);
-
- adjust_vmin_vmax(
- core_freesync, streams,
- num_streams, map_index,
- v_total_nominal,
- v_total_nominal);
- }
- return true;
-
- } else {
- /* Disable freesync */
- v_total_nominal = streams[stream_idx]->
- timing.v_total;
-
- /* Update the freesync context for
- * the stream
- */
- update_stream_freesync_context(
- core_freesync,
- streams[stream_idx]);
-
- adjust_vmin_vmax(core_freesync, streams,
- num_streams, map_index,
- v_total_nominal,
- v_total_nominal);
-
- /* Reset the cached variables */
- reset_freesync_state_variables(state);
-
- return true;
- }
- } else {
- /* Disable freesync */
- v_total_nominal = streams[stream_idx]->
- timing.v_total;
- /*
- * we have to reset drr always even sink does
- * not support freesync because a former stream has
- * be programmed
- */
- adjust_vmin_vmax(core_freesync, streams,
- num_streams, map_index,
- v_total_nominal,
- v_total_nominal);
- /* Reset the cached variables */
- reset_freesync_state_variables(state);
- }
-
- }
-
- return false;
+ in_out_vrr->adjust.v_total_min = v_total;
+ in_out_vrr->adjust.v_total_max = v_total;
}
-static void set_static_ramp_variables(struct core_freesync *core_freesync,
- unsigned int index, bool enable_static_screen)
-{
- unsigned int frame_duration = 0;
- unsigned int nominal_refresh_rate = core_freesync->map[index].state.
- nominal_refresh_rate_in_micro_hz;
- unsigned int min_refresh_rate= core_freesync->map[index].caps->
- min_refresh_in_micro_hz;
- struct gradual_static_ramp *static_ramp_variables =
- &core_freesync->map[index].state.static_ramp;
-
- /* If we are ENABLING static screen, refresh rate should go DOWN.
- * If we are DISABLING static screen, refresh rate should go UP.
- */
- if (enable_static_screen)
- static_ramp_variables->ramp_direction_is_up = false;
- else
- static_ramp_variables->ramp_direction_is_up = true;
-
- /* If ramp is not active, set initial frame duration depending on
- * whether we are enabling/disabling static screen mode. If the ramp is
- * already active, ramp should continue in the opposite direction
- * starting with the current frame duration
- */
- if (!static_ramp_variables->ramp_is_active) {
- if (enable_static_screen == true) {
- /* Going to lower refresh rate, so start from max
- * refresh rate (min frame duration)
- */
- frame_duration = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- nominal_refresh_rate)));
- } else {
- /* Going to higher refresh rate, so start from min
- * refresh rate (max frame duration)
- */
- frame_duration = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- min_refresh_rate)));
- }
- static_ramp_variables->
- ramp_current_frame_duration_in_ns = frame_duration;
-
- static_ramp_variables->ramp_is_active = true;
- }
-}
-
-void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams)
+static void apply_below_the_range(struct core_freesync *core_freesync,
+ const struct dc_stream_state *stream,
+ unsigned int last_render_time_in_us,
+ struct mod_vrr_params *in_out_vrr)
{
- unsigned int index, v_total, inserted_frame_v_total = 0;
- unsigned int min_frame_duration_in_ns, vmax, vmin = 0;
- struct freesync_state *state;
- struct core_freesync *core_freesync = NULL;
- struct dc_static_screen_events triggers = {0};
-
- if (mod_freesync == NULL)
- return;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-
- if (core_freesync->num_entities == 0)
- return;
-
- index = map_index_from_stream(core_freesync,
- streams[0]);
-
- if (core_freesync->map[index].caps->supported == false)
- return;
-
- state = &core_freesync->map[index].state;
-
- /* Below the Range Logic */
-
- /* Only execute if in fullscreen mode */
- if (state->fullscreen == true &&
- core_freesync->map[index].user_enable.enable_for_gaming &&
- core_freesync->map[index].caps->btr_supported &&
- state->btr.btr_active) {
+ unsigned int inserted_frame_duration_in_us = 0;
+ unsigned int mid_point_frames_ceil = 0;
+ unsigned int mid_point_frames_floor = 0;
+ unsigned int frame_time_in_us = 0;
+ unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
+ unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
+ unsigned int frames_to_insert = 0;
+ unsigned int min_frame_duration_in_ns = 0;
+ unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
- /* TODO: pass in flag for Pre-DCE12 ASIC
- * in order for frame variable duration to take affect,
- * it needs to be done one VSYNC early, which is at
- * frameCounter == 1.
- * For DCE12 and newer updates to V_TOTAL_MIN/MAX
- * will take affect on current frame
- */
- if (state->btr.frames_to_insert == state->btr.frame_counter) {
+ min_frame_duration_in_ns = ((unsigned int) (div64_u64(
+ (1000000000ULL * 1000000),
+ in_out_vrr->max_refresh_in_uhz)));
- min_frame_duration_in_ns = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- state->nominal_refresh_rate_in_micro_hz)));
+ /* Program BTR */
+ if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+ /* Exit Below the Range */
+ if (in_out_vrr->btr.btr_active) {
+ in_out_vrr->btr.frame_counter = 0;
+ in_out_vrr->btr.btr_active = false;
- vmin = state->freesync_range.vmin;
+ /* Exit Fixed Refresh mode */
+ } else if (in_out_vrr->fixed.fixed_active) {
- inserted_frame_v_total = vmin;
+ in_out_vrr->fixed.frame_counter++;
- if (min_frame_duration_in_ns / 1000)
- inserted_frame_v_total =
- state->btr.inserted_frame_duration_in_us *
- vmin / (min_frame_duration_in_ns / 1000);
+ if (in_out_vrr->fixed.frame_counter >
+ FIXED_REFRESH_EXIT_FRAME_COUNT) {
+ in_out_vrr->fixed.frame_counter = 0;
+ in_out_vrr->fixed.fixed_active = false;
+ }
+ }
+ } else if (last_render_time_in_us > max_render_time_in_us) {
+ /* Enter Below the Range */
+ if (!in_out_vrr->btr.btr_active &&
+ in_out_vrr->btr.btr_enabled) {
+ in_out_vrr->btr.btr_active = true;
- /* Set length of inserted frames as v_total_max*/
- vmax = inserted_frame_v_total;
- vmin = inserted_frame_v_total;
+ /* Enter Fixed Refresh mode */
+ } else if (!in_out_vrr->fixed.fixed_active &&
+ !in_out_vrr->btr.btr_enabled) {
+ in_out_vrr->fixed.frame_counter++;
- /* Program V_TOTAL */
- adjust_vmin_vmax(core_freesync, streams,
- num_streams, index,
- vmin, vmax);
+ if (in_out_vrr->fixed.frame_counter >
+ FIXED_REFRESH_ENTER_FRAME_COUNT) {
+ in_out_vrr->fixed.frame_counter = 0;
+ in_out_vrr->fixed.fixed_active = true;
+ }
}
+ }
- if (state->btr.frame_counter > 0)
- state->btr.frame_counter--;
+ /* BTR set to "not active" so disengage */
+ if (!in_out_vrr->btr.btr_active) {
+ in_out_vrr->btr.btr_active = false;
+ in_out_vrr->btr.inserted_duration_in_us = 0;
+ in_out_vrr->btr.frames_to_insert = 0;
+ in_out_vrr->btr.frame_counter = 0;
/* Restore FreeSync */
- if (state->btr.frame_counter == 0)
- set_freesync_on_streams(core_freesync, streams, num_streams);
- }
-
- /* If in fullscreen freesync mode or in video, do not program
- * static screen ramp values
- */
- if (state->fullscreen == true || state->video == true) {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->max_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->min_refresh_in_uhz);
+ /* BTR set to "active" so engage */
+ } else {
- state->static_ramp.ramp_is_active = false;
+ /* Calculate number of midPoint frames that could fit within
+ * the render time interval- take ceil of this value
+ */
+ mid_point_frames_ceil = (last_render_time_in_us +
+ in_out_vrr->btr.mid_point_in_us - 1) /
+ in_out_vrr->btr.mid_point_in_us;
- return;
- }
+ if (mid_point_frames_ceil > 0) {
+ frame_time_in_us = last_render_time_in_us /
+ mid_point_frames_ceil;
+ delta_from_mid_point_in_us_1 =
+ (in_out_vrr->btr.mid_point_in_us >
+ frame_time_in_us) ?
+ (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
+ (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
+ }
- /* Gradual Static Screen Ramping Logic */
+ /* Calculate number of midPoint frames that could fit within
+ * the render time interval- take floor of this value
+ */
+ mid_point_frames_floor = last_render_time_in_us /
+ in_out_vrr->btr.mid_point_in_us;
- /* Execute if ramp is active and user enabled freesync static screen*/
- if (state->static_ramp.ramp_is_active &&
- core_freesync->map[index].user_enable.enable_for_static) {
+ if (mid_point_frames_floor > 0) {
- calc_v_total_for_static_ramp(core_freesync, streams[0],
- index, &v_total);
+ frame_time_in_us = last_render_time_in_us /
+ mid_point_frames_floor;
+ delta_from_mid_point_in_us_2 =
+ (in_out_vrr->btr.mid_point_in_us >
+ frame_time_in_us) ?
+ (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
+ (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
+ }
- /* Update the freesync context for the stream */
- update_stream_freesync_context(core_freesync, streams[0]);
+ /* Choose number of frames to insert based on how close it
+ * can get to the mid point of the variable range.
+ */
+ if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2)
+ frames_to_insert = mid_point_frames_ceil;
+ else
+ frames_to_insert = mid_point_frames_floor;
- /* Program static screen ramp values */
- adjust_vmin_vmax(core_freesync, streams,
- num_streams, index,
- v_total,
- v_total);
+ /* Either we've calculated the number of frames to insert,
+ * or we need to insert min duration frames
+ */
+ if (frames_to_insert > 0)
+ inserted_frame_duration_in_us = last_render_time_in_us /
+ frames_to_insert;
- triggers.overlay_update = true;
- triggers.surface_update = true;
+ if (inserted_frame_duration_in_us <
+ (1000000 / in_out_vrr->max_refresh_in_uhz))
+ inserted_frame_duration_in_us =
+ (1000000 / in_out_vrr->max_refresh_in_uhz);
- dc_stream_set_static_screen_events(core_freesync->dc, streams,
- num_streams, &triggers);
+ /* Cache the calculated variables */
+ in_out_vrr->btr.inserted_duration_in_us =
+ inserted_frame_duration_in_us;
+ in_out_vrr->btr.frames_to_insert = frames_to_insert;
+ in_out_vrr->btr.frame_counter = frames_to_insert;
+
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_duration(stream, in_out_vrr,
+ in_out_vrr->btr.inserted_duration_in_us);
+ in_out_vrr->adjust.v_total_max =
+ in_out_vrr->adjust.v_total_min;
}
}
-void mod_freesync_update_state(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- struct mod_freesync_params *freesync_params)
+static void apply_fixed_refresh(struct core_freesync *core_freesync,
+ const struct dc_stream_state *stream,
+ unsigned int last_render_time_in_us,
+ struct mod_vrr_params *in_out_vrr)
{
- bool freesync_program_required = false;
- unsigned int stream_index;
- struct freesync_state *state;
- struct core_freesync *core_freesync = NULL;
- struct dc_static_screen_events triggers = {0};
+ bool update = false;
+ unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
- if (mod_freesync == NULL)
- return;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-
- if (core_freesync->num_entities == 0)
- return;
+ if (last_render_time_in_us + BTR_EXIT_MARGIN < max_render_time_in_us) {
+ /* Exit Fixed Refresh mode */
+ if (in_out_vrr->fixed.fixed_active) {
+ in_out_vrr->fixed.frame_counter++;
- for(stream_index = 0; stream_index < num_streams; stream_index++) {
-
- unsigned int map_index = map_index_from_stream(core_freesync,
- streams[stream_index]);
-
- bool is_embedded = dc_is_embedded_signal(
- streams[stream_index]->sink->sink_signal);
-
- struct freesync_registry_options *opts = &core_freesync->opts;
-
- state = &core_freesync->map[map_index].state;
-
- switch (freesync_params->state){
- case FREESYNC_STATE_FULLSCREEN:
- state->fullscreen = freesync_params->enable;
- freesync_program_required = true;
- state->windowed_fullscreen =
- freesync_params->windowed_fullscreen;
- break;
- case FREESYNC_STATE_STATIC_SCREEN:
- /* Static screen ramp is disabled by default, but can
- * be enabled through regkey.
- */
- if ((is_embedded && opts->drr_internal_supported) ||
- (!is_embedded && opts->drr_external_supported))
-
- if (state->static_screen !=
- freesync_params->enable) {
-
- /* Change the state flag */
- state->static_screen =
- freesync_params->enable;
-
- /* Update static screen ramp */
- set_static_ramp_variables(core_freesync,
- map_index,
- freesync_params->enable);
- }
- /* We program the ramp starting next VUpdate */
- break;
- case FREESYNC_STATE_VIDEO:
- /* Change core variables only if there is a change*/
- if(freesync_params->update_duration_in_ns !=
- state->time.update_duration_in_ns) {
-
- state->video = freesync_params->enable;
- state->time.update_duration_in_ns =
- freesync_params->update_duration_in_ns;
-
- freesync_program_required = true;
+ if (in_out_vrr->fixed.frame_counter >
+ FIXED_REFRESH_EXIT_FRAME_COUNT) {
+ in_out_vrr->fixed.frame_counter = 0;
+ in_out_vrr->fixed.fixed_active = false;
+ in_out_vrr->fixed.target_refresh_in_uhz = 0;
+ update = true;
}
- break;
- case FREESYNC_STATE_NONE:
- /* handle here to avoid warning */
- break;
}
- }
-
- /* Update mask */
- triggers.overlay_update = true;
- triggers.surface_update = true;
-
- dc_stream_set_static_screen_events(core_freesync->dc, streams,
- num_streams, &triggers);
-
- if (freesync_program_required)
- /* Program freesync according to current state*/
- set_freesync_on_streams(core_freesync, streams, num_streams);
-}
-
-
-bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- struct mod_freesync_params *freesync_params)
-{
- unsigned int index = 0;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
+ } else if (last_render_time_in_us > max_render_time_in_us) {
+ /* Enter Fixed Refresh mode */
+ if (!in_out_vrr->fixed.fixed_active) {
+ in_out_vrr->fixed.frame_counter++;
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- if (core_freesync->map[index].state.fullscreen) {
- freesync_params->state = FREESYNC_STATE_FULLSCREEN;
- freesync_params->enable = true;
- } else if (core_freesync->map[index].state.static_screen) {
- freesync_params->state = FREESYNC_STATE_STATIC_SCREEN;
- freesync_params->enable = true;
- } else if (core_freesync->map[index].state.video) {
- freesync_params->state = FREESYNC_STATE_VIDEO;
- freesync_params->enable = true;
- } else {
- freesync_params->state = FREESYNC_STATE_NONE;
- freesync_params->enable = false;
+ if (in_out_vrr->fixed.frame_counter >
+ FIXED_REFRESH_ENTER_FRAME_COUNT) {
+ in_out_vrr->fixed.frame_counter = 0;
+ in_out_vrr->fixed.fixed_active = true;
+ in_out_vrr->fixed.target_refresh_in_uhz =
+ in_out_vrr->max_refresh_in_uhz;
+ update = true;
+ }
+ }
}
- freesync_params->update_duration_in_ns =
- core_freesync->map[index].state.time.update_duration_in_ns;
-
- freesync_params->windowed_fullscreen =
- core_freesync->map[index].state.windowed_fullscreen;
-
- return true;
-}
-
-bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- struct mod_freesync_user_enable *user_enable)
-{
- unsigned int stream_index, map_index;
- int persistent_data = 0;
- struct persistent_data_flag flag;
- struct dc *dc = NULL;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- dc = core_freesync->dc;
-
- flag.save_per_edid = true;
- flag.save_per_link = false;
-
- for(stream_index = 0; stream_index < num_streams;
- stream_index++){
-
- map_index = map_index_from_stream(core_freesync,
- streams[stream_index]);
-
- core_freesync->map[map_index].user_enable = *user_enable;
-
- /* Write persistent data in registry*/
- if (core_freesync->map[map_index].user_enable.
- enable_for_gaming)
- persistent_data = persistent_data | 1;
- if (core_freesync->map[map_index].user_enable.
- enable_for_static)
- persistent_data = persistent_data | 2;
- if (core_freesync->map[map_index].user_enable.
- enable_for_video)
- persistent_data = persistent_data | 4;
-
- dm_write_persistent_data(dc->ctx,
- streams[stream_index]->sink,
- FREESYNC_REGISTRY_NAME,
- "userenable",
- &persistent_data,
- sizeof(int),
- &flag);
+ if (update) {
+ if (in_out_vrr->fixed.fixed_active) {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(
+ stream, in_out_vrr->max_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ in_out_vrr->adjust.v_total_min;
+ } else {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(
+ stream, in_out_vrr->max_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ in_out_vrr->adjust.v_total_min;
+ }
}
-
- set_freesync_on_streams(core_freesync, streams, num_streams);
-
- return true;
}
-bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- struct mod_freesync_user_enable *user_enable)
-{
- unsigned int index = 0;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- *user_enable = core_freesync->map[index].user_enable;
-
- return true;
-}
-
-bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- bool *is_ramp_active)
-{
- unsigned int index = 0;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- *is_ramp_active =
- core_freesync->map[index].state.static_ramp.ramp_is_active;
-
- return true;
-}
-
-bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
- struct dc_stream_state *streams,
- unsigned int min_refresh,
- unsigned int max_refresh,
- struct mod_freesync_caps *caps)
+static bool vrr_settings_require_update(struct core_freesync *core_freesync,
+ struct mod_freesync_config *in_config,
+ unsigned int min_refresh_in_uhz,
+ unsigned int max_refresh_in_uhz,
+ struct mod_vrr_params *in_vrr)
{
- unsigned int index = 0;
- struct core_freesync *core_freesync;
- struct freesync_state *state;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, streams);
- state = &core_freesync->map[index].state;
-
- if (max_refresh == 0)
- max_refresh = state->nominal_refresh_rate_in_micro_hz;
-
- if (min_refresh == 0) {
- /* Restore defaults */
- calc_freesync_range(core_freesync, streams, state,
- core_freesync->map[index].caps->
- min_refresh_in_micro_hz,
- state->nominal_refresh_rate_in_micro_hz);
- } else {
- calc_freesync_range(core_freesync, streams,
- state,
- min_refresh,
- max_refresh);
-
- /* Program vtotal min/max */
- adjust_vmin_vmax(core_freesync, &streams, 1, index,
- state->freesync_range.vmin,
- state->freesync_range.vmax);
- }
-
- if (min_refresh != 0 &&
- dc_is_embedded_signal(streams->sink->sink_signal) &&
- (max_refresh - min_refresh >= 10000000)) {
- caps->supported = true;
- caps->min_refresh_in_micro_hz = min_refresh;
- caps->max_refresh_in_micro_hz = max_refresh;
+ if (in_vrr->state != in_config->state) {
+ return true;
+ } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
+ in_vrr->fixed.target_refresh_in_uhz !=
+ in_config->min_refresh_in_uhz) {
+ return true;
+ } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
+ return true;
+ } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
+ return true;
}
- /* Update the stream */
- update_stream(core_freesync, streams);
-
- return true;
-}
-
-bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- unsigned int *min_refresh,
- unsigned int *max_refresh)
-{
- unsigned int index = 0;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- *min_refresh =
- core_freesync->map[index].state.freesync_range.min_refresh;
- *max_refresh =
- core_freesync->map[index].state.freesync_range.max_refresh;
-
- return true;
+ return false;
}
bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
+ const struct dc_stream_state *stream,
unsigned int *vmin,
unsigned int *vmax)
{
- unsigned int index = 0;
- struct core_freesync *core_freesync = NULL;
-
- if (mod_freesync == NULL)
- return false;
-
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
-
- *vmin =
- core_freesync->map[index].state.freesync_range.vmin;
- *vmax =
- core_freesync->map[index].state.freesync_range.vmax;
+ *vmin = stream->adjust.v_total_min;
+ *vmax = stream->adjust.v_total_max;
return true;
}
@@ -1188,7 +471,6 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
unsigned int *nom_v_pos,
unsigned int *v_pos)
{
- unsigned int index = 0;
struct core_freesync *core_freesync = NULL;
struct crtc_position position;
@@ -1196,7 +478,6 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
return false;
core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- index = map_index_from_stream(core_freesync, stream);
if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
&position.vertical_count,
@@ -1211,310 +492,368 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
return false;
}
-void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams)
+void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ const struct mod_vrr_params *vrr,
+ struct dc_info_packet *infopacket)
{
- unsigned int stream_index, map_index;
- struct freesync_state *state;
- struct core_freesync *core_freesync = NULL;
- struct dc_static_screen_events triggers = {0};
- unsigned long long temp = 0;
+ /* SPD info packet for FreeSync */
+ unsigned char checksum = 0;
+ unsigned int idx, payload_size = 0;
- if (mod_freesync == NULL)
+ /* Check if Freesync is supported. Return if false. If true,
+ * set the corresponding bit in the info packet
+ */
+ if (!vrr->supported)
return;
- core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+ if (dc_is_hdmi_signal(stream->signal)) {
- for (stream_index = 0; stream_index < num_streams; stream_index++) {
- map_index = map_index_from_stream(core_freesync,
- streams[stream_index]);
-
- state = &core_freesync->map[map_index].state;
-
- /* Update the field rate for new timing */
- temp = streams[stream_index]->timing.pix_clk_khz;
- temp *= 1000ULL * 1000ULL * 1000ULL;
- temp = div_u64(temp,
- streams[stream_index]->timing.h_total);
- temp = div_u64(temp,
- streams[stream_index]->timing.v_total);
- state->nominal_refresh_rate_in_micro_hz =
- (unsigned int) temp;
-
- if (core_freesync->map[map_index].caps->supported) {
-
- /* Update the stream */
- update_stream(core_freesync, streams[stream_index]);
-
- /* Calculate vmin/vmax and refresh rate for
- * current mode
- */
- calc_freesync_range(core_freesync, *streams, state,
- core_freesync->map[map_index].caps->
- min_refresh_in_micro_hz,
- state->nominal_refresh_rate_in_micro_hz);
-
- /* Update mask */
- triggers.overlay_update = true;
- triggers.surface_update = true;
-
- dc_stream_set_static_screen_events(core_freesync->dc,
- streams, num_streams,
- &triggers);
- }
- }
+ /* HEADER */
- /* Program freesync according to current state*/
- set_freesync_on_streams(core_freesync, streams, num_streams);
-}
+ /* HB0 = Packet Type = 0x83 (Source Product
+ * Descriptor InfoFrame)
+ */
+ infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
-/* Add the timestamps to the cache and determine whether BTR programming
- * is required, depending on the times calculated
- */
-static void update_timestamps(struct core_freesync *core_freesync,
- const struct dc_stream_state *stream, unsigned int map_index,
- unsigned int last_render_time_in_us)
-{
- struct freesync_state *state = &core_freesync->map[map_index].state;
+ /* HB1 = Version = 0x01 */
+ infopacket->hb1 = 0x01;
- state->time.render_times[state->time.render_times_index] =
- last_render_time_in_us;
- state->time.render_times_index++;
+ /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
+ infopacket->hb2 = 0x08;
- if (state->time.render_times_index >= RENDER_TIMES_MAX_COUNT)
- state->time.render_times_index = 0;
+ payload_size = 0x08;
- if (last_render_time_in_us + BTR_EXIT_MARGIN <
- state->time.max_render_time_in_us) {
+ } else if (dc_is_dp_signal(stream->signal)) {
- /* Exit Below the Range */
- if (state->btr.btr_active) {
+ /* HEADER */
- state->btr.program_btr = true;
- state->btr.btr_active = false;
- state->btr.frame_counter = 0;
+ /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
+ * when used to associate audio related info packets
+ */
+ infopacket->hb0 = 0x00;
- /* Exit Fixed Refresh mode */
- } else if (state->fixed_refresh.fixed_active) {
+ /* HB1 = Packet Type = 0x83 (Source Product
+ * Descriptor InfoFrame)
+ */
+ infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
- state->fixed_refresh.frame_counter++;
+ /* HB2 = [Bits 7:0 = Least significant eight bits -
+ * For INFOFRAME, the value must be 1Bh]
+ */
+ infopacket->hb2 = 0x1B;
- if (state->fixed_refresh.frame_counter >
- FIXED_REFRESH_EXIT_FRAME_COUNT) {
- state->fixed_refresh.frame_counter = 0;
- state->fixed_refresh.program_fixed = true;
- state->fixed_refresh.fixed_active = false;
- }
- }
+ /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
+ * [Bits 1:0 = Most significant two bits = 0x00]
+ */
+ infopacket->hb3 = 0x04;
- } else if (last_render_time_in_us > state->time.max_render_time_in_us) {
+ payload_size = 0x1B;
+ }
- /* Enter Below the Range */
- if (!state->btr.btr_active &&
- core_freesync->map[map_index].caps->btr_supported) {
+ /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
+ infopacket->sb[1] = 0x1A;
- state->btr.program_btr = true;
- state->btr.btr_active = true;
+ /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
+ infopacket->sb[2] = 0x00;
- /* Enter Fixed Refresh mode */
- } else if (!state->fixed_refresh.fixed_active &&
- !core_freesync->map[map_index].caps->btr_supported) {
+ /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
+ infopacket->sb[3] = 0x00;
- state->fixed_refresh.frame_counter++;
+ /* PB4 = Reserved */
- if (state->fixed_refresh.frame_counter >
- FIXED_REFRESH_ENTER_FRAME_COUNT) {
- state->fixed_refresh.frame_counter = 0;
- state->fixed_refresh.program_fixed = true;
- state->fixed_refresh.fixed_active = true;
- }
- }
- }
+ /* PB5 = Reserved */
- /* When Below the Range is active, must react on every frame */
- if (state->btr.btr_active)
- state->btr.program_btr = true;
-}
+ /* PB6 = [Bits 7:3 = Reserved] */
-static void apply_below_the_range(struct core_freesync *core_freesync,
- struct dc_stream_state *stream, unsigned int map_index,
- unsigned int last_render_time_in_us)
-{
- unsigned int inserted_frame_duration_in_us = 0;
- unsigned int mid_point_frames_ceil = 0;
- unsigned int mid_point_frames_floor = 0;
- unsigned int frame_time_in_us = 0;
- unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
- unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
- unsigned int frames_to_insert = 0;
- unsigned int min_frame_duration_in_ns = 0;
- struct freesync_state *state = &core_freesync->map[map_index].state;
+ /* PB6 = [Bit 0 = FreeSync Supported] */
+ if (vrr->state != VRR_STATE_UNSUPPORTED)
+ infopacket->sb[6] |= 0x01;
- if (!state->btr.program_btr)
- return;
+ /* PB6 = [Bit 1 = FreeSync Enabled] */
+ if (vrr->state != VRR_STATE_DISABLED &&
+ vrr->state != VRR_STATE_UNSUPPORTED)
+ infopacket->sb[6] |= 0x02;
- state->btr.program_btr = false;
+ /* PB6 = [Bit 2 = FreeSync Active] */
+ if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+ vrr->state == VRR_STATE_ACTIVE_FIXED)
+ infopacket->sb[6] |= 0x04;
- min_frame_duration_in_ns = ((unsigned int) (div64_u64(
- (1000000000ULL * 1000000),
- state->nominal_refresh_rate_in_micro_hz)));
+ /* PB7 = FreeSync Minimum refresh rate (Hz) */
+ infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
- /* Program BTR */
+ /* PB8 = FreeSync Maximum refresh rate (Hz)
+ * Note: We should never go above the field rate of the mode timing set.
+ */
+ infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
- /* BTR set to "not active" so disengage */
- if (!state->btr.btr_active)
+ /* PB9 - PB27 = Reserved */
- /* Restore FreeSync */
- set_freesync_on_streams(core_freesync, &stream, 1);
+ /* Calculate checksum */
+ checksum += infopacket->hb0;
+ checksum += infopacket->hb1;
+ checksum += infopacket->hb2;
+ checksum += infopacket->hb3;
- /* BTR set to "active" so engage */
- else {
+ for (idx = 1; idx <= payload_size; idx++)
+ checksum += infopacket->sb[idx];
- /* Calculate number of midPoint frames that could fit within
- * the render time interval- take ceil of this value
- */
- mid_point_frames_ceil = (last_render_time_in_us +
- state->btr.mid_point_in_us- 1) /
- state->btr.mid_point_in_us;
+ /* PB0 = Checksum (one byte complement) */
+ infopacket->sb[0] = (unsigned char)(0x100 - checksum);
- if (mid_point_frames_ceil > 0) {
+ infopacket->valid = true;
+}
- frame_time_in_us = last_render_time_in_us /
- mid_point_frames_ceil;
- delta_from_mid_point_in_us_1 =
- (state->btr.mid_point_in_us >
- frame_time_in_us) ?
- (state->btr.mid_point_in_us - frame_time_in_us):
- (frame_time_in_us - state->btr.mid_point_in_us);
- }
+void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ struct mod_freesync_config *in_config,
+ struct mod_vrr_params *in_out_vrr)
+{
+ struct core_freesync *core_freesync = NULL;
+ unsigned long long nominal_field_rate_in_uhz = 0;
+ bool nominal_field_rate_in_range = true;
+ unsigned int refresh_range = 0;
+ unsigned int min_refresh_in_uhz = 0;
+ unsigned int max_refresh_in_uhz = 0;
- /* Calculate number of midPoint frames that could fit within
- * the render time interval- take floor of this value
- */
- mid_point_frames_floor = last_render_time_in_us /
- state->btr.mid_point_in_us;
+ if (mod_freesync == NULL)
+ return;
- if (mid_point_frames_floor > 0) {
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- frame_time_in_us = last_render_time_in_us /
- mid_point_frames_floor;
- delta_from_mid_point_in_us_2 =
- (state->btr.mid_point_in_us >
- frame_time_in_us) ?
- (state->btr.mid_point_in_us - frame_time_in_us):
- (frame_time_in_us - state->btr.mid_point_in_us);
- }
+ /* Calculate nominal field rate for stream */
+ nominal_field_rate_in_uhz = stream->timing.pix_clk_khz;
+ nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
+ nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
+ stream->timing.h_total);
+ nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
+ stream->timing.v_total);
+
+ min_refresh_in_uhz = in_config->min_refresh_in_uhz;
+ max_refresh_in_uhz = in_config->max_refresh_in_uhz;
+
+ // Don't allow min > max
+ if (min_refresh_in_uhz > max_refresh_in_uhz)
+ min_refresh_in_uhz = max_refresh_in_uhz;
+
+ // Full range may be larger than current video timing, so cap at nominal
+ if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
+ max_refresh_in_uhz = nominal_field_rate_in_uhz;
+
+ /* Allow for some rounding error of actual video timing by taking ceil.
+ * For example, 144 Hz mode timing may actually be 143.xxx Hz when
+ * calculated from pixel rate and vertical/horizontal totals, but
+ * this should be allowed instead of blocking FreeSync.
+ */
+ if ((min_refresh_in_uhz / 1000000) >
+ ((nominal_field_rate_in_uhz + 1000000 - 1) / 1000000))
+ nominal_field_rate_in_range = false;
- /* Choose number of frames to insert based on how close it
- * can get to the mid point of the variable range.
- */
- if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2)
- frames_to_insert = mid_point_frames_ceil;
- else
- frames_to_insert = mid_point_frames_floor;
+ // Full range may be larger than current video timing, so cap at nominal
+ if (min_refresh_in_uhz > nominal_field_rate_in_uhz)
+ min_refresh_in_uhz = nominal_field_rate_in_uhz;
- /* Either we've calculated the number of frames to insert,
- * or we need to insert min duration frames
- */
- if (frames_to_insert > 0)
- inserted_frame_duration_in_us = last_render_time_in_us /
- frames_to_insert;
+ if (!vrr_settings_require_update(core_freesync,
+ in_config, min_refresh_in_uhz, max_refresh_in_uhz,
+ in_out_vrr))
+ return;
- if (inserted_frame_duration_in_us <
- state->time.min_render_time_in_us)
+ in_out_vrr->state = in_config->state;
- inserted_frame_duration_in_us =
- state->time.min_render_time_in_us;
+ if ((in_config->state == VRR_STATE_UNSUPPORTED) ||
+ (!nominal_field_rate_in_range)) {
+ in_out_vrr->state = VRR_STATE_UNSUPPORTED;
+ in_out_vrr->supported = false;
+ } else {
+ in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
+ in_out_vrr->max_duration_in_us =
+ calc_duration_in_us_from_refresh_in_uhz(
+ min_refresh_in_uhz);
- /* Cache the calculated variables */
- state->btr.inserted_frame_duration_in_us =
- inserted_frame_duration_in_us;
- state->btr.frames_to_insert = frames_to_insert;
- state->btr.frame_counter = frames_to_insert;
+ in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
+ in_out_vrr->min_duration_in_us =
+ calc_duration_in_us_from_refresh_in_uhz(
+ max_refresh_in_uhz);
+ refresh_range = in_out_vrr->max_refresh_in_uhz -
+ in_out_vrr->min_refresh_in_uhz;
+
+ in_out_vrr->supported = true;
+ }
+
+ in_out_vrr->fixed.ramping_active = in_config->ramping;
+
+ in_out_vrr->btr.btr_enabled = in_config->btr;
+ if (in_out_vrr->max_refresh_in_uhz <
+ 2 * in_out_vrr->min_refresh_in_uhz)
+ in_out_vrr->btr.btr_enabled = false;
+ in_out_vrr->btr.btr_active = false;
+ in_out_vrr->btr.inserted_duration_in_us = 0;
+ in_out_vrr->btr.frames_to_insert = 0;
+ in_out_vrr->btr.frame_counter = 0;
+ in_out_vrr->btr.mid_point_in_us =
+ in_out_vrr->min_duration_in_us +
+ (in_out_vrr->max_duration_in_us -
+ in_out_vrr->min_duration_in_us) / 2;
+
+ if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
+ in_out_vrr->adjust.v_total_min = stream->timing.v_total;
+ in_out_vrr->adjust.v_total_max = stream->timing.v_total;
+ } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
+ in_out_vrr->adjust.v_total_min = stream->timing.v_total;
+ in_out_vrr->adjust.v_total_max = stream->timing.v_total;
+ } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
+ in_out_vrr->adjust.v_total_min = stream->timing.v_total;
+ in_out_vrr->adjust.v_total_max = stream->timing.v_total;
+ } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
+ refresh_range >= MIN_REFRESH_RANGE_IN_US) {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->max_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->min_refresh_in_uhz);
+ } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
+ in_out_vrr->fixed.target_refresh_in_uhz =
+ in_out_vrr->min_refresh_in_uhz;
+ if (in_out_vrr->fixed.ramping_active) {
+ in_out_vrr->fixed.fixed_active = true;
+ } else {
+ in_out_vrr->fixed.fixed_active = true;
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->fixed.target_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ in_out_vrr->adjust.v_total_min;
+ }
+ } else {
+ in_out_vrr->state = VRR_STATE_INACTIVE;
+ in_out_vrr->adjust.v_total_min = stream->timing.v_total;
+ in_out_vrr->adjust.v_total_max = stream->timing.v_total;
}
}
-static void apply_fixed_refresh(struct core_freesync *core_freesync,
- struct dc_stream_state *stream, unsigned int map_index)
+void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
+ const struct dc_plane_state *plane,
+ const struct dc_stream_state *stream,
+ unsigned int curr_time_stamp_in_us,
+ struct mod_vrr_params *in_out_vrr)
{
- unsigned int vmin = 0, vmax = 0;
- struct freesync_state *state = &core_freesync->map[map_index].state;
+ struct core_freesync *core_freesync = NULL;
+ unsigned int last_render_time_in_us = 0;
+ unsigned int average_render_time_in_us = 0;
- if (!state->fixed_refresh.program_fixed)
+ if (mod_freesync == NULL)
return;
- state->fixed_refresh.program_fixed = false;
+ core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- /* Program Fixed Refresh */
+ if (in_out_vrr->supported &&
+ in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
+ unsigned int i = 0;
+ unsigned int oldest_index = plane->time.index + 1;
- /* Fixed Refresh set to "not active" so disengage */
- if (!state->fixed_refresh.fixed_active) {
- set_freesync_on_streams(core_freesync, &stream, 1);
+ if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX)
+ oldest_index = 0;
- /* Fixed Refresh set to "active" so engage (fix to max) */
- } else {
+ last_render_time_in_us = curr_time_stamp_in_us -
+ plane->time.prev_update_time_in_us;
+
+ // Sum off all entries except oldest one
+ for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) {
+ average_render_time_in_us +=
+ plane->time.time_elapsed_in_us[i];
+ }
+ average_render_time_in_us -=
+ plane->time.time_elapsed_in_us[oldest_index];
+
+ // Add render time for current flip
+ average_render_time_in_us += last_render_time_in_us;
+ average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX;
+
+ if (in_out_vrr->btr.btr_enabled) {
+ apply_below_the_range(core_freesync,
+ stream,
+ last_render_time_in_us,
+ in_out_vrr);
+ } else {
+ apply_fixed_refresh(core_freesync,
+ stream,
+ last_render_time_in_us,
+ in_out_vrr);
+ }
- vmin = state->freesync_range.vmin;
- vmax = vmin;
- adjust_vmin_vmax(core_freesync, &stream, map_index,
- 1, vmin, vmax);
}
}
-void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- unsigned int curr_time_stamp_in_us)
+void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ struct mod_vrr_params *in_out_vrr)
{
- unsigned int stream_index, map_index, last_render_time_in_us = 0;
struct core_freesync *core_freesync = NULL;
- if (mod_freesync == NULL)
+ if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
return;
core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- for (stream_index = 0; stream_index < num_streams; stream_index++) {
-
- map_index = map_index_from_stream(core_freesync,
- streams[stream_index]);
-
- if (core_freesync->map[map_index].caps->supported) {
-
- last_render_time_in_us = curr_time_stamp_in_us -
- core_freesync->map[map_index].state.time.
- prev_time_stamp_in_us;
-
- /* Add the timestamps to the cache and determine
- * whether BTR program is required
- */
- update_timestamps(core_freesync, streams[stream_index],
- map_index, last_render_time_in_us);
+ if (in_out_vrr->supported == false)
+ return;
- if (core_freesync->map[map_index].state.fullscreen &&
- core_freesync->map[map_index].user_enable.
- enable_for_gaming) {
+ /* Below the Range Logic */
- if (core_freesync->map[map_index].caps->btr_supported) {
+ /* Only execute if in fullscreen mode */
+ if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
+ in_out_vrr->btr.btr_active) {
+ /* TODO: pass in flag for Pre-DCE12 ASIC
+ * in order for frame variable duration to take affect,
+ * it needs to be done one VSYNC early, which is at
+ * frameCounter == 1.
+ * For DCE12 and newer updates to V_TOTAL_MIN/MAX
+ * will take affect on current frame
+ */
+ if (in_out_vrr->btr.frames_to_insert ==
+ in_out_vrr->btr.frame_counter) {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_duration(stream,
+ in_out_vrr,
+ in_out_vrr->btr.inserted_duration_in_us);
+ in_out_vrr->adjust.v_total_max =
+ in_out_vrr->adjust.v_total_min;
+ }
- apply_below_the_range(core_freesync,
- streams[stream_index], map_index,
- last_render_time_in_us);
- } else {
- apply_fixed_refresh(core_freesync,
- streams[stream_index], map_index);
- }
- }
+ if (in_out_vrr->btr.frame_counter > 0)
+ in_out_vrr->btr.frame_counter--;
- core_freesync->map[map_index].state.time.
- prev_time_stamp_in_us = curr_time_stamp_in_us;
+ /* Restore FreeSync */
+ if (in_out_vrr->btr.frame_counter == 0) {
+ in_out_vrr->adjust.v_total_min =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->max_refresh_in_uhz);
+ in_out_vrr->adjust.v_total_max =
+ calc_v_total_from_refresh(stream,
+ in_out_vrr->min_refresh_in_uhz);
}
+ }
+
+ /* If in fullscreen freesync mode or in video, do not program
+ * static screen ramp values
+ */
+ if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
+ in_out_vrr->fixed.ramping_active = false;
+ /* Gradual Static Screen Ramping Logic */
+ /* Execute if ramp is active and user enabled freesync static screen*/
+ if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
+ in_out_vrr->fixed.ramping_active) {
+ update_v_total_for_static_ramp(
+ core_freesync, stream, in_out_vrr);
}
}
void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
+ const struct mod_vrr_params *vrr,
unsigned int *v_total_min, unsigned int *v_total_max,
unsigned int *event_triggers,
unsigned int *window_min, unsigned int *window_max,
@@ -1522,7 +861,6 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
unsigned int *inserted_frames,
unsigned int *inserted_duration_in_us)
{
- unsigned int stream_index, map_index;
struct core_freesync *core_freesync = NULL;
if (mod_freesync == NULL)
@@ -1530,25 +868,13 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
- for (stream_index = 0; stream_index < num_streams; stream_index++) {
-
- map_index = map_index_from_stream(core_freesync,
- streams[stream_index]);
-
- if (core_freesync->map[map_index].caps->supported) {
- struct freesync_state state =
- core_freesync->map[map_index].state;
- *v_total_min = state.vmin;
- *v_total_max = state.vmax;
- *event_triggers = 0;
- *window_min = state.time.min_window;
- *window_max = state.time.max_window;
- *lfc_mid_point_in_us = state.btr.mid_point_in_us;
- *inserted_frames = state.btr.frames_to_insert;
- *inserted_duration_in_us =
- state.btr.inserted_frame_duration_in_us;
- }
-
+ if (vrr->supported) {
+ *v_total_min = vrr->adjust.v_total_min;
+ *v_total_max = vrr->adjust.v_total_max;
+ *event_triggers = 0;
+ *lfc_mid_point_in_us = vrr->btr.mid_point_in_us;
+ *inserted_frames = vrr->btr.frames_to_insert;
+ *inserted_duration_in_us = vrr->btr.inserted_duration_in_us;
}
}
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index f083e1619dbe..bd75ca5f1cd3 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -56,96 +56,72 @@
#include "dm_services.h"
-struct mod_freesync *mod_freesync_create(struct dc *dc);
-void mod_freesync_destroy(struct mod_freesync *mod_freesync);
-
+// Access structures
struct mod_freesync {
int dummy;
};
-enum mod_freesync_state {
- FREESYNC_STATE_NONE,
- FREESYNC_STATE_FULLSCREEN,
- FREESYNC_STATE_STATIC_SCREEN,
- FREESYNC_STATE_VIDEO
-};
-
-enum mod_freesync_user_enable_mask {
- FREESYNC_USER_ENABLE_STATIC = 0x1,
- FREESYNC_USER_ENABLE_VIDEO = 0x2,
- FREESYNC_USER_ENABLE_GAMING = 0x4
-};
-
-struct mod_freesync_user_enable {
- bool enable_for_static;
- bool enable_for_video;
- bool enable_for_gaming;
-};
-
+// TODO: References to this should be removed
struct mod_freesync_caps {
bool supported;
unsigned int min_refresh_in_micro_hz;
unsigned int max_refresh_in_micro_hz;
-
- bool btr_supported;
};
-struct mod_freesync_params {
- enum mod_freesync_state state;
- bool enable;
- unsigned int update_duration_in_ns;
- bool windowed_fullscreen;
+enum mod_vrr_state {
+ VRR_STATE_UNSUPPORTED = 0,
+ VRR_STATE_DISABLED,
+ VRR_STATE_INACTIVE,
+ VRR_STATE_ACTIVE_VARIABLE,
+ VRR_STATE_ACTIVE_FIXED
};
-/*
- * Add stream to be tracked by module
- */
-bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream, struct mod_freesync_caps *caps);
+struct mod_freesync_config {
+ enum mod_vrr_state state;
+ bool ramping;
+ bool btr;
+ unsigned int min_refresh_in_uhz;
+ unsigned int max_refresh_in_uhz;
+};
-/*
- * Remove stream to be tracked by module
- */
-bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream);
+struct mod_vrr_params_btr {
+ bool btr_enabled;
+ bool btr_active;
+ uint32_t mid_point_in_us;
+ uint32_t inserted_duration_in_us;
+ uint32_t frames_to_insert;
+ uint32_t frame_counter;
+};
-/*
- * Update the freesync state flags for each display and program
- * freesync accordingly
- */
-void mod_freesync_update_state(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- struct mod_freesync_params *freesync_params);
+struct mod_vrr_params_fixed_refresh {
+ bool fixed_active;
+ bool ramping_active;
+ bool ramping_done;
+ uint32_t target_refresh_in_uhz;
+ uint32_t frame_counter;
+};
-bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- struct mod_freesync_params *freesync_params);
+struct mod_vrr_params {
+ bool supported;
+ enum mod_vrr_state state;
-bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- struct mod_freesync_user_enable *user_enable);
+ uint32_t min_refresh_in_uhz;
+ uint32_t max_duration_in_us;
+ uint32_t max_refresh_in_uhz;
+ uint32_t min_duration_in_us;
-bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- struct mod_freesync_user_enable *user_enable);
+ struct dc_crtc_timing_adjust adjust;
-bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- bool *is_ramp_active);
+ struct mod_vrr_params_fixed_refresh fixed;
-bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
- struct dc_stream_state *streams,
- unsigned int min_refresh,
- unsigned int max_refresh,
- struct mod_freesync_caps *caps);
+ struct mod_vrr_params_btr btr;
+};
-bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
- unsigned int *min_refresh,
- unsigned int *max_refresh);
+struct mod_freesync *mod_freesync_create(struct dc *dc);
+void mod_freesync_destroy(struct mod_freesync *mod_freesync);
bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
- struct dc_stream_state *stream,
+ const struct dc_stream_state *stream,
unsigned int *vmin,
unsigned int *vmax);
@@ -154,18 +130,8 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
unsigned int *nom_v_pos,
unsigned int *v_pos);
-void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams);
-
-void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams);
-
-void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
- unsigned int curr_time_stamp);
-
void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
- struct dc_stream_state **streams, int num_streams,
+ const struct mod_vrr_params *vrr,
unsigned int *v_total_min, unsigned int *v_total_max,
unsigned int *event_triggers,
unsigned int *window_min, unsigned int *window_max,
@@ -173,4 +139,24 @@ void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
unsigned int *inserted_frames,
unsigned int *inserted_duration_in_us);
+void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ const struct mod_vrr_params *vrr,
+ struct dc_info_packet *infopacket);
+
+void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ struct mod_freesync_config *in_config,
+ struct mod_vrr_params *in_out_vrr);
+
+void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
+ const struct dc_plane_state *plane,
+ const struct dc_stream_state *stream,
+ unsigned int curr_time_stamp_in_us,
+ struct mod_vrr_params *in_out_vrr);
+
+void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
+ const struct dc_stream_state *stream,
+ struct mod_vrr_params *in_out_vrr);
+
#endif
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 13/32] drm/amd/display: Refactor stream encoder for HW review
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (11 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 12/32] drm/amd/display: Refactor FreeSync module Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 14/32] drm/amd/display: remove unused enum Harry Wentland
` (18 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Eric Bernstein
From: Eric Bernstein <eric.bernstein@amd.com>
Move DCN1 implementation of stream encoder to new file (instead
of common dce_stream_encoder.c).
Cleanup code related to different implementation due to register
definition differences.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +-
.../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +-
.../amd/display/dc/dcn10/dcn10_stream_encoder.c | 1505 ++++++++++++++++++++
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 584 ++++++++
4 files changed, 2101 insertions(+), 26 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 5469bdfe19f3..5c69743a4b4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
dcn10_hubp.o dcn10_mpc.o \
dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
- dcn10_hubbub.o
+ dcn10_hubbub.o dcn10_stream_encoder.o
AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 7ad290cbc730..f305f65675d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -39,7 +39,7 @@
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_opp.h"
#include "dce/dce_link_encoder.h"
-#include "dce/dce_stream_encoder.h"
+#include "dcn10/dcn10_stream_encoder.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
@@ -166,36 +166,22 @@ static const struct dce_abm_mask abm_mask = {
#define stream_enc_regs(id)\
[id] = {\
- SE_DCN_REG_LIST(id),\
- .TMDS_CNTL = 0,\
- .AFMT_AVI_INFO0 = 0,\
- .AFMT_AVI_INFO1 = 0,\
- .AFMT_AVI_INFO2 = 0,\
- .AFMT_AVI_INFO3 = 0,\
+ SE_DCN_REG_LIST(id)\
}
-static const struct dce110_stream_enc_registers stream_enc_regs[] = {
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(0),
stream_enc_regs(1),
stream_enc_regs(2),
stream_enc_regs(3),
};
-static const struct dce_stream_encoder_shift se_shift = {
+static const struct dcn10_stream_encoder_shift se_shift = {
SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
};
-static const struct dce_stream_encoder_mask se_mask = {
- SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
- .AFMT_GENERIC0_UPDATE = 0,
- .AFMT_GENERIC2_UPDATE = 0,
- .DP_DYN_RANGE = 0,
- .DP_YCBCR_RANGE = 0,
- .HDMI_AVI_INFO_SEND = 0,
- .HDMI_AVI_INFO_CONT = 0,
- .HDMI_AVI_INFO_LINE = 0,
- .DP_SEC_AVI_ENABLE = 0,
- .AFMT_AVI_INFO_VERSION = 0
+static const struct dcn10_stream_encoder_mask se_mask = {
+ SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
};
#define audio_regs(id)\
@@ -653,16 +639,16 @@ static struct stream_encoder *dcn10_stream_encoder_create(
enum engine_id eng_id,
struct dc_context *ctx)
{
- struct dce110_stream_encoder *enc110 =
- kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
+ struct dcn10_stream_encoder *enc1 =
+ kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
- if (!enc110)
+ if (!enc1)
return NULL;
- dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
+ dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
&stream_enc_regs[eng_id],
&se_shift, &se_mask);
- return &enc110->base;
+ return &enc1->base;
}
static const struct dce_hwseq_registers hwseq_reg = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
new file mode 100644
index 000000000000..0413c707b921
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -0,0 +1,1505 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dc_bios_types.h"
+#include "dcn10_stream_encoder.h"
+
+#include "reg_helper.h"
+#define DC_LOGGER \
+ enc1->base.ctx->logger
+enum DP_PIXEL_ENCODING {
+DP_PIXEL_ENCODING_RGB444 = 0x00000000,
+DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
+DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
+DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
+DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
+DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
+DP_PIXEL_ENCODING_RESERVED = 0x00000006,
+};
+
+
+enum DP_COMPONENT_DEPTH {
+DP_COMPONENT_DEPTH_6BPC = 0x00000000,
+DP_COMPONENT_DEPTH_8BPC = 0x00000001,
+DP_COMPONENT_DEPTH_10BPC = 0x00000002,
+DP_COMPONENT_DEPTH_12BPC = 0x00000003,
+DP_COMPONENT_DEPTH_16BPC = 0x00000004,
+DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
+};
+
+
+#define REG(reg)\
+ (enc1->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ enc1->se_shift->field_name, enc1->se_mask->field_name
+
+#define VBI_LINE_0 0
+#define DP_BLANK_MAX_RETRY 20
+#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
+
+
+enum {
+ DP_MST_UPDATE_MAX_RETRY = 50
+};
+
+#define CTX \
+ enc1->base.ctx
+
+static void enc1_update_generic_info_packet(
+ struct dcn10_stream_encoder *enc1,
+ uint32_t packet_index,
+ const struct dc_info_packet *info_packet)
+{
+ uint32_t regval;
+ /* TODOFPGA Figure out a proper number for max_retries polling for lock
+ * use 50 for now.
+ */
+ uint32_t max_retries = 50;
+
+ /*we need turn on clock before programming AFMT block*/
+ REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
+
+ if (packet_index >= 8)
+ ASSERT(0);
+
+ /* poll dig_update_lock is not locked -> asic internal signal
+ * assume otg master lock will unlock it
+ */
+/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
+ 0, 10, max_retries);*/
+
+ /* check if HW reading GSP memory */
+ REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
+ 0, 10, max_retries);
+
+ /* HW does is not reading GSP memory not reading too long ->
+ * something wrong. clear GPS memory access and notify?
+ * hw SW is writing to GSP memory
+ */
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
+
+ /* choose which generic packet to use */
+ regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
+ AFMT_GENERIC_INDEX, packet_index);
+
+ /* write generic packet header
+ * (4th byte is for GENERIC0 only)
+ */
+ REG_SET_4(AFMT_GENERIC_HDR, 0,
+ AFMT_GENERIC_HB0, info_packet->hb0,
+ AFMT_GENERIC_HB1, info_packet->hb1,
+ AFMT_GENERIC_HB2, info_packet->hb2,
+ AFMT_GENERIC_HB3, info_packet->hb3);
+
+ /* write generic packet contents
+ * (we never use last 4 bytes)
+ * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
+ */
+ {
+ const uint32_t *content =
+ (const uint32_t *) &info_packet->sb[0];
+
+ REG_WRITE(AFMT_GENERIC_0, *content++);
+ REG_WRITE(AFMT_GENERIC_1, *content++);
+ REG_WRITE(AFMT_GENERIC_2, *content++);
+ REG_WRITE(AFMT_GENERIC_3, *content++);
+ REG_WRITE(AFMT_GENERIC_4, *content++);
+ REG_WRITE(AFMT_GENERIC_5, *content++);
+ REG_WRITE(AFMT_GENERIC_6, *content++);
+ REG_WRITE(AFMT_GENERIC_7, *content);
+ }
+
+ switch (packet_index) {
+ case 0:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC0_FRAME_UPDATE, 1);
+ break;
+ case 1:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC1_FRAME_UPDATE, 1);
+ break;
+ case 2:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC2_FRAME_UPDATE, 1);
+ break;
+ case 3:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC3_FRAME_UPDATE, 1);
+ break;
+ case 4:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC4_FRAME_UPDATE, 1);
+ break;
+ case 5:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC5_FRAME_UPDATE, 1);
+ break;
+ case 6:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC6_FRAME_UPDATE, 1);
+ break;
+ case 7:
+ REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
+ AFMT_GENERIC7_FRAME_UPDATE, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void enc1_update_hdmi_info_packet(
+ struct dcn10_stream_encoder *enc1,
+ uint32_t packet_index,
+ const struct dc_info_packet *info_packet)
+{
+ uint32_t cont, send, line;
+
+ if (info_packet->valid) {
+ enc1_update_generic_info_packet(
+ enc1,
+ packet_index,
+ info_packet);
+
+ /* enable transmission of packet(s) -
+ * packet transmission begins on the next frame
+ */
+ cont = 1;
+ /* send packet(s) every frame */
+ send = 1;
+ /* select line number to send packets on */
+ line = 2;
+ } else {
+ cont = 0;
+ send = 0;
+ line = 0;
+ }
+
+ /* choose which generic packet control to use */
+ switch (packet_index) {
+ case 0:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 1:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+ case 2:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 3:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+ case 4:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 5:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+ case 6:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
+ HDMI_GENERIC0_CONT, cont,
+ HDMI_GENERIC0_SEND, send,
+ HDMI_GENERIC0_LINE, line);
+ break;
+ case 7:
+ REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
+ HDMI_GENERIC1_CONT, cont,
+ HDMI_GENERIC1_SEND, send,
+ HDMI_GENERIC1_LINE, line);
+ break;
+ default:
+ /* invalid HW packet index */
+ DC_LOG_WARNING(
+ "Invalid HW packet index: %s()\n",
+ __func__);
+ return;
+ }
+}
+
+/* setup stream encoder in dp mode */
+static void enc1_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space)
+{
+ uint32_t h_active_start;
+ uint32_t v_active_start;
+ uint32_t misc0 = 0;
+ uint32_t misc1 = 0;
+ uint32_t h_blank;
+ uint32_t h_back_porch;
+ uint8_t synchronous_clock = 0; /* asynchronous mode */
+ uint8_t colorimetry_bpc;
+ uint8_t dynamic_range_rgb = 0; /*full range*/
+ uint8_t dynamic_range_ycbcr = 1; /*bt709*/
+
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
+
+ /* set pixel encoding */
+ switch (crtc_timing->pixel_encoding) {
+ case PIXEL_ENCODING_YCBCR422:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_YCBCR422);
+ break;
+ case PIXEL_ENCODING_YCBCR444:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_YCBCR444);
+
+ if (crtc_timing->flags.Y_ONLY)
+ if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
+ /* HW testing only, no use case yet.
+ * Color depth of Y-only could be
+ * 8, 10, 12, 16 bits
+ */
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_Y_ONLY);
+ /* Note: DP_MSA_MISC1 bit 7 is the indicator
+ * of Y-only mode.
+ * This bit is set in HW if register
+ * DP_PIXEL_ENCODING is programmed to 0x4
+ */
+ break;
+ case PIXEL_ENCODING_YCBCR420:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_YCBCR420);
+ REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
+ break;
+ default:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+ DP_PIXEL_ENCODING_RGB444);
+ break;
+ }
+
+ misc1 = REG_READ(DP_MSA_MISC);
+
+ /* set color depth */
+
+ switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ 0);
+ break;
+ case COLOR_DEPTH_888:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ DP_COMPONENT_DEPTH_8BPC);
+ break;
+ case COLOR_DEPTH_101010:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ DP_COMPONENT_DEPTH_10BPC);
+
+ break;
+ case COLOR_DEPTH_121212:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ DP_COMPONENT_DEPTH_12BPC);
+ break;
+ default:
+ REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
+ DP_COMPONENT_DEPTH_6BPC);
+ break;
+ }
+
+ /* set dynamic range and YCbCr range */
+
+ switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_666:
+ colorimetry_bpc = 0;
+ break;
+ case COLOR_DEPTH_888:
+ colorimetry_bpc = 1;
+ break;
+ case COLOR_DEPTH_101010:
+ colorimetry_bpc = 2;
+ break;
+ case COLOR_DEPTH_121212:
+ colorimetry_bpc = 3;
+ break;
+ default:
+ colorimetry_bpc = 0;
+ break;
+ }
+
+ misc0 = misc0 | synchronous_clock;
+ misc0 = colorimetry_bpc << 5;
+
+ switch (output_color_space) {
+ case COLOR_SPACE_SRGB:
+ misc0 = misc0 | 0x0;
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_rgb = 0; /*full range*/
+ break;
+ case COLOR_SPACE_SRGB_LIMITED:
+ misc0 = misc0 | 0x8; /* bit3=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_rgb = 1; /*limited range*/
+ break;
+ case COLOR_SPACE_YCBCR601:
+ case COLOR_SPACE_YCBCR601_LIMITED:
+ misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_ycbcr = 0; /*bt601*/
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_YCBCR709:
+ case COLOR_SPACE_YCBCR709_LIMITED:
+ misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
+ misc1 = misc1 & ~0x80; /* bit7 = 0*/
+ dynamic_range_ycbcr = 1; /*bt709*/
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
+ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+ misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
+ break;
+ case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
+ dynamic_range_rgb = 1; /*limited range*/
+ break;
+ case COLOR_SPACE_2020_RGB_FULLRANGE:
+ case COLOR_SPACE_2020_YCBCR:
+ case COLOR_SPACE_XR_RGB:
+ case COLOR_SPACE_MSREF_SCRGB:
+ case COLOR_SPACE_ADOBERGB:
+ case COLOR_SPACE_DCIP3:
+ case COLOR_SPACE_XV_YCC_709:
+ case COLOR_SPACE_XV_YCC_601:
+ case COLOR_SPACE_DISPLAYNATIVE:
+ case COLOR_SPACE_DOLBYVISION:
+ case COLOR_SPACE_APPCTRL:
+ case COLOR_SPACE_CUSTOMPOINTS:
+ case COLOR_SPACE_UNKNOWN:
+ /* do nothing */
+ break;
+ }
+
+ REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
+ REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
+
+ /* dcn new register
+ * dc_crtc_timing is vesa dmt struct. data from edid
+ */
+ REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
+ DP_MSA_HTOTAL, crtc_timing->h_total,
+ DP_MSA_VTOTAL, crtc_timing->v_total);
+
+ /* calculate from vesa timing parameters
+ * h_active_start related to leading edge of sync
+ */
+
+ h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
+ crtc_timing->h_addressable - crtc_timing->h_border_right;
+
+ h_back_porch = h_blank - crtc_timing->h_front_porch -
+ crtc_timing->h_sync_width;
+
+ /* start at beginning of left border */
+ h_active_start = crtc_timing->h_sync_width + h_back_porch;
+
+
+ v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
+ crtc_timing->v_addressable - crtc_timing->v_border_bottom -
+ crtc_timing->v_front_porch;
+
+
+ /* start at beginning of left border */
+ REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
+ DP_MSA_HSTART, h_active_start,
+ DP_MSA_VSTART, v_active_start);
+
+ REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
+ DP_MSA_HSYNCWIDTH,
+ crtc_timing->h_sync_width,
+ DP_MSA_HSYNCPOLARITY,
+ !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
+ DP_MSA_VSYNCWIDTH,
+ crtc_timing->v_sync_width,
+ DP_MSA_VSYNCPOLARITY,
+ !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
+
+ /* HWDITH include border or overscan */
+ REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
+ DP_MSA_HWIDTH, crtc_timing->h_border_left +
+ crtc_timing->h_addressable + crtc_timing->h_border_right,
+ DP_MSA_VHEIGHT, crtc_timing->v_border_top +
+ crtc_timing->v_addressable + crtc_timing->v_border_bottom);
+}
+
+static void enc1_stream_encoder_set_stream_attribute_helper(
+ struct dcn10_stream_encoder *enc1,
+ struct dc_crtc_timing *crtc_timing)
+{
+ switch (crtc_timing->pixel_encoding) {
+ case PIXEL_ENCODING_YCBCR422:
+ REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
+ break;
+ default:
+ REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
+ break;
+ }
+ REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
+}
+
+/* setup stream encoder in hdmi mode */
+static void enc1_stream_encoder_hdmi_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ int actual_pix_clk_khz,
+ bool enable_audio)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ struct bp_encoder_control cntl = {0};
+
+ cntl.action = ENCODER_CONTROL_SETUP;
+ cntl.engine_id = enc1->base.id;
+ cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
+ cntl.enable_dp_audio = enable_audio;
+ cntl.pixel_clock = actual_pix_clk_khz;
+ cntl.lanes_number = LANE_COUNT_FOUR;
+
+ if (enc1->base.bp->funcs->encoder_control(
+ enc1->base.bp, &cntl) != BP_RESULT_OK)
+ return;
+
+ enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+
+ /* setup HDMI engine */
+ REG_UPDATE_5(HDMI_CONTROL,
+ HDMI_PACKET_GEN_VERSION, 1,
+ HDMI_KEEPOUT_MODE, 1,
+ HDMI_DEEP_COLOR_ENABLE, 0,
+ HDMI_DATA_SCRAMBLE_EN, 0,
+ HDMI_CLOCK_CHANNEL_RATE, 0);
+
+
+ switch (crtc_timing->display_color_depth) {
+ case COLOR_DEPTH_888:
+ REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
+ break;
+ case COLOR_DEPTH_101010:
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DEEP_COLOR_DEPTH, 1,
+ HDMI_DEEP_COLOR_ENABLE, 0);
+ } else {
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DEEP_COLOR_DEPTH, 1,
+ HDMI_DEEP_COLOR_ENABLE, 1);
+ }
+ break;
+ case COLOR_DEPTH_121212:
+ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DEEP_COLOR_DEPTH, 2,
+ HDMI_DEEP_COLOR_ENABLE, 0);
+ } else {
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DEEP_COLOR_DEPTH, 2,
+ HDMI_DEEP_COLOR_ENABLE, 1);
+ }
+ break;
+ case COLOR_DEPTH_161616:
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DEEP_COLOR_DEPTH, 3,
+ HDMI_DEEP_COLOR_ENABLE, 1);
+ break;
+ default:
+ break;
+ }
+
+ if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
+ /* enable HDMI data scrambler
+ * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
+ * Clock channel frequency is 1/4 of character rate.
+ */
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DATA_SCRAMBLE_EN, 1,
+ HDMI_CLOCK_CHANNEL_RATE, 1);
+ } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
+
+ /* TODO: New feature for DCE11, still need to implement */
+
+ /* enable HDMI data scrambler
+ * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
+ * Clock channel frequency is the same
+ * as character rate
+ */
+ REG_UPDATE_2(HDMI_CONTROL,
+ HDMI_DATA_SCRAMBLE_EN, 1,
+ HDMI_CLOCK_CHANNEL_RATE, 0);
+ }
+
+
+ REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
+ HDMI_GC_CONT, 1,
+ HDMI_GC_SEND, 1,
+ HDMI_NULL_SEND, 1);
+
+ /* following belongs to audio */
+ REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
+
+ REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
+
+ REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
+ VBI_LINE_0 + 2);
+
+ REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
+}
+
+/* setup stream encoder in dvi mode */
+static void enc1_stream_encoder_dvi_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ bool is_dual_link)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ struct bp_encoder_control cntl = {0};
+
+ cntl.action = ENCODER_CONTROL_SETUP;
+ cntl.engine_id = enc1->base.id;
+ cntl.signal = is_dual_link ?
+ SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
+ cntl.enable_dp_audio = false;
+ cntl.pixel_clock = crtc_timing->pix_clk_khz;
+ cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
+
+ if (enc1->base.bp->funcs->encoder_control(
+ enc1->base.bp, &cntl) != BP_RESULT_OK)
+ return;
+
+ ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
+ ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
+ enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
+}
+
+static void enc1_stream_encoder_set_mst_bandwidth(
+ struct stream_encoder *enc,
+ struct fixed31_32 avg_time_slots_per_mtp)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t x = dal_fixed31_32_floor(
+ avg_time_slots_per_mtp);
+ uint32_t y = dal_fixed31_32_ceil(
+ dal_fixed31_32_shl(
+ dal_fixed31_32_sub_int(
+ avg_time_slots_per_mtp,
+ x),
+ 26));
+
+ REG_SET_2(DP_MSE_RATE_CNTL, 0,
+ DP_MSE_RATE_X, x,
+ DP_MSE_RATE_Y, y);
+
+ /* wait for update to be completed on the link */
+ /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
+ /* is reset to 0 (not pending) */
+ REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
+ 0,
+ 10, DP_MST_UPDATE_MAX_RETRY);
+}
+
+static void enc1_stream_encoder_update_hdmi_info_packets(
+ struct stream_encoder *enc,
+ const struct encoder_info_frame *info_frame)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ /* for bring up, disable dp double TODO */
+ REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
+
+ enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
+ enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
+ enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
+ enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
+ enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
+}
+
+static void enc1_stream_encoder_stop_hdmi_info_packets(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ /* stop generic packets 0 & 1 on HDMI */
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0);
+
+ /* stop generic packets 2 & 3 on HDMI */
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
+
+ /* stop generic packets 2 & 3 on HDMI */
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
+
+ REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
+ HDMI_GENERIC0_CONT, 0,
+ HDMI_GENERIC0_LINE, 0,
+ HDMI_GENERIC0_SEND, 0,
+ HDMI_GENERIC1_CONT, 0,
+ HDMI_GENERIC1_LINE, 0,
+ HDMI_GENERIC1_SEND, 0);
+}
+
+static void enc1_stream_encoder_update_dp_info_packets(
+ struct stream_encoder *enc,
+ const struct encoder_info_frame *info_frame)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t value = REG_READ(DP_SEC_CNTL);
+
+ if (info_frame->vsc.valid)
+ enc1_update_generic_info_packet(
+ enc1,
+ 0, /* packetIndex */
+ &info_frame->vsc);
+
+ if (info_frame->spd.valid)
+ enc1_update_generic_info_packet(
+ enc1,
+ 2, /* packetIndex */
+ &info_frame->spd);
+
+ if (info_frame->hdrsmd.valid)
+ enc1_update_generic_info_packet(
+ enc1,
+ 3, /* packetIndex */
+ &info_frame->hdrsmd);
+
+ /* enable/disable transmission of packet(s).
+ * If enabled, packet transmission begins on the next frame
+ */
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
+
+ /* This bit is the master enable bit.
+ * When enabling secondary stream engine,
+ * this master bit must also be set.
+ * This register shared with audio info frame.
+ * Therefore we need to enable master bit
+ * if at least on of the fields is not 0
+ */
+ if (value)
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
+}
+
+static void enc1_stream_encoder_stop_dp_info_packets(
+ struct stream_encoder *enc)
+{
+ /* stop generic packets on DP */
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t value = REG_READ(DP_SEC_CNTL);
+
+ REG_SET_10(DP_SEC_CNTL, 0,
+ DP_SEC_GSP0_ENABLE, 0,
+ DP_SEC_GSP1_ENABLE, 0,
+ DP_SEC_GSP2_ENABLE, 0,
+ DP_SEC_GSP3_ENABLE, 0,
+ DP_SEC_GSP4_ENABLE, 0,
+ DP_SEC_GSP5_ENABLE, 0,
+ DP_SEC_GSP6_ENABLE, 0,
+ DP_SEC_GSP7_ENABLE, 0,
+ DP_SEC_MPG_ENABLE, 0,
+ DP_SEC_STREAM_ENABLE, 0);
+
+ /* this register shared with audio info frame.
+ * therefore we need to keep master enabled
+ * if at least one of the fields is not 0 */
+
+ if (value)
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
+
+}
+
+static void enc1_stream_encoder_dp_blank(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t retries = 0;
+ uint32_t reg1 = 0;
+ uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
+
+ /* Note: For CZ, we are changing driver default to disable
+ * stream deferred to next VBLANK. If results are positive, we
+ * will make the same change to all DCE versions. There are a
+ * handful of panels that cannot handle disable stream at
+ * HBLANK and will result in a white line flash across the
+ * screen on stream disable.
+ */
+ REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
+ if ((reg1 & 0x1) == 0)
+ /*stream not enabled*/
+ return;
+ /* Specify the video stream disable point
+ * (2 = start of the next vertical blank)
+ */
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
+ /* Larger delay to wait until VBLANK - use max retry of
+ * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
+ * a little more because we may not trust delay accuracy.
+ */
+ max_retries = DP_BLANK_MAX_RETRY * 150;
+
+ /* disable DP stream */
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
+
+ /* the encoder stops sending the video stream
+ * at the start of the vertical blanking.
+ * Poll for DP_VID_STREAM_STATUS == 0
+ */
+
+ REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
+ 0,
+ 10, max_retries);
+
+ ASSERT(retries <= max_retries);
+
+ /* Tell the DP encoder to ignore timing from CRTC, must be done after
+ * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
+ * complete, stream status will be stuck in video stream enabled state,
+ * i.e. DP_VID_STREAM_STATUS stuck at 1.
+ */
+
+ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
+}
+
+/* output video stream to link encoder */
+static void enc1_stream_encoder_dp_unblank(
+ struct stream_encoder *enc,
+ const struct encoder_unblank_param *param)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
+ uint32_t n_vid = 0x8000;
+ uint32_t m_vid;
+
+ /* M / N = Fstream / Flink
+ * m_vid / n_vid = pixel rate / link rate
+ */
+
+ uint64_t m_vid_l = n_vid;
+
+ m_vid_l *= param->pixel_clk_khz;
+ m_vid_l = div_u64(m_vid_l,
+ param->link_settings.link_rate
+ * LINK_RATE_REF_FREQ_IN_KHZ);
+
+ m_vid = (uint32_t) m_vid_l;
+
+ /* enable auto measurement */
+
+ REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
+
+ /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
+ * therefore program initial value for Mvid and Nvid
+ */
+
+ REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
+
+ REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
+
+ REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
+ }
+
+ /* set DIG_START to 0x1 to resync FIFO */
+
+ REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
+
+ /* switch DP encoder to CRTC data */
+
+ REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
+
+ /* wait 100us for DIG/DP logic to prime
+ * (i.e. a few video lines)
+ */
+ udelay(100);
+
+ /* the hardware would start sending video at the start of the next DP
+ * frame (i.e. rising edge of the vblank).
+ * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
+ * register has no effect on enable transition! HW always guarantees
+ * VID_STREAM enable at start of next frame, and this is not
+ * programmable
+ */
+
+ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
+}
+
+static void enc1_stream_encoder_set_avmute(
+ struct stream_encoder *enc,
+ bool enable)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ unsigned int value = enable ? 1 : 0;
+
+ REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
+}
+
+
+#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
+#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
+
+#include "include/audio_types.h"
+
+/**
+* speakersToChannels
+*
+* @brief
+* translate speakers to channels
+*
+* FL - Front Left
+* FR - Front Right
+* RL - Rear Left
+* RR - Rear Right
+* RC - Rear Center
+* FC - Front Center
+* FLC - Front Left Center
+* FRC - Front Right Center
+* RLC - Rear Left Center
+* RRC - Rear Right Center
+* LFE - Low Freq Effect
+*
+* FC
+* FLC FRC
+* FL FR
+*
+* LFE
+* ()
+*
+*
+* RL RR
+* RLC RRC
+* RC
+*
+* ch 8 7 6 5 4 3 2 1
+* 0b00000011 - - - - - - FR FL
+* 0b00000111 - - - - - LFE FR FL
+* 0b00001011 - - - - FC - FR FL
+* 0b00001111 - - - - FC LFE FR FL
+* 0b00010011 - - - RC - - FR FL
+* 0b00010111 - - - RC - LFE FR FL
+* 0b00011011 - - - RC FC - FR FL
+* 0b00011111 - - - RC FC LFE FR FL
+* 0b00110011 - - RR RL - - FR FL
+* 0b00110111 - - RR RL - LFE FR FL
+* 0b00111011 - - RR RL FC - FR FL
+* 0b00111111 - - RR RL FC LFE FR FL
+* 0b01110011 - RC RR RL - - FR FL
+* 0b01110111 - RC RR RL - LFE FR FL
+* 0b01111011 - RC RR RL FC - FR FL
+* 0b01111111 - RC RR RL FC LFE FR FL
+* 0b11110011 RRC RLC RR RL - - FR FL
+* 0b11110111 RRC RLC RR RL - LFE FR FL
+* 0b11111011 RRC RLC RR RL FC - FR FL
+* 0b11111111 RRC RLC RR RL FC LFE FR FL
+* 0b11000011 FRC FLC - - - - FR FL
+* 0b11000111 FRC FLC - - - LFE FR FL
+* 0b11001011 FRC FLC - - FC - FR FL
+* 0b11001111 FRC FLC - - FC LFE FR FL
+* 0b11010011 FRC FLC - RC - - FR FL
+* 0b11010111 FRC FLC - RC - LFE FR FL
+* 0b11011011 FRC FLC - RC FC - FR FL
+* 0b11011111 FRC FLC - RC FC LFE FR FL
+* 0b11110011 FRC FLC RR RL - - FR FL
+* 0b11110111 FRC FLC RR RL - LFE FR FL
+* 0b11111011 FRC FLC RR RL FC - FR FL
+* 0b11111111 FRC FLC RR RL FC LFE FR FL
+*
+* @param
+* speakers - speaker information as it comes from CEA audio block
+*/
+/* translate speakers to channels */
+
+union audio_cea_channels {
+ uint8_t all;
+ struct audio_cea_channels_bits {
+ uint32_t FL:1;
+ uint32_t FR:1;
+ uint32_t LFE:1;
+ uint32_t FC:1;
+ uint32_t RL_RC:1;
+ uint32_t RR:1;
+ uint32_t RC_RLC_FLC:1;
+ uint32_t RRC_FRC:1;
+ } channels;
+};
+
+struct audio_clock_info {
+ /* pixel clock frequency*/
+ uint32_t pixel_clock_in_10khz;
+ /* N - 32KHz audio */
+ uint32_t n_32khz;
+ /* CTS - 32KHz audio*/
+ uint32_t cts_32khz;
+ uint32_t n_44khz;
+ uint32_t cts_44khz;
+ uint32_t n_48khz;
+ uint32_t cts_48khz;
+};
+
+/* 25.2MHz/1.001*/
+/* 25.2MHz/1.001*/
+/* 25.2MHz*/
+/* 27MHz */
+/* 27MHz*1.001*/
+/* 27MHz*1.001*/
+/* 54MHz*/
+/* 54MHz*1.001*/
+/* 74.25MHz/1.001*/
+/* 74.25MHz*/
+/* 148.5MHz/1.001*/
+/* 148.5MHz*/
+
+static const struct audio_clock_info audio_clock_info_table[16] = {
+ {2517, 4576, 28125, 7007, 31250, 6864, 28125},
+ {2518, 4576, 28125, 7007, 31250, 6864, 28125},
+ {2520, 4096, 25200, 6272, 28000, 6144, 25200},
+ {2700, 4096, 27000, 6272, 30000, 6144, 27000},
+ {2702, 4096, 27027, 6272, 30030, 6144, 27027},
+ {2703, 4096, 27027, 6272, 30030, 6144, 27027},
+ {5400, 4096, 54000, 6272, 60000, 6144, 54000},
+ {5405, 4096, 54054, 6272, 60060, 6144, 54054},
+ {7417, 11648, 210937, 17836, 234375, 11648, 140625},
+ {7425, 4096, 74250, 6272, 82500, 6144, 74250},
+ {14835, 11648, 421875, 8918, 234375, 5824, 140625},
+ {14850, 4096, 148500, 6272, 165000, 6144, 148500},
+ {29670, 5824, 421875, 4459, 234375, 5824, 281250},
+ {29700, 3072, 222750, 4704, 247500, 5120, 247500},
+ {59340, 5824, 843750, 8918, 937500, 5824, 562500},
+ {59400, 3072, 445500, 9408, 990000, 6144, 594000}
+};
+
+static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
+ {2517, 9152, 84375, 7007, 48875, 9152, 56250},
+ {2518, 9152, 84375, 7007, 48875, 9152, 56250},
+ {2520, 4096, 37800, 6272, 42000, 6144, 37800},
+ {2700, 4096, 40500, 6272, 45000, 6144, 40500},
+ {2702, 8192, 81081, 6272, 45045, 8192, 54054},
+ {2703, 8192, 81081, 6272, 45045, 8192, 54054},
+ {5400, 4096, 81000, 6272, 90000, 6144, 81000},
+ {5405, 4096, 81081, 6272, 90090, 6144, 81081},
+ {7417, 11648, 316406, 17836, 351562, 11648, 210937},
+ {7425, 4096, 111375, 6272, 123750, 6144, 111375},
+ {14835, 11648, 632812, 17836, 703125, 11648, 421875},
+ {14850, 4096, 222750, 6272, 247500, 6144, 222750},
+ {29670, 5824, 632812, 8918, 703125, 5824, 421875},
+ {29700, 4096, 445500, 4704, 371250, 5120, 371250}
+};
+
+static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
+ {2517, 4576, 56250, 7007, 62500, 6864, 56250},
+ {2518, 4576, 56250, 7007, 62500, 6864, 56250},
+ {2520, 4096, 50400, 6272, 56000, 6144, 50400},
+ {2700, 4096, 54000, 6272, 60000, 6144, 54000},
+ {2702, 4096, 54054, 6267, 60060, 8192, 54054},
+ {2703, 4096, 54054, 6272, 60060, 8192, 54054},
+ {5400, 4096, 108000, 6272, 120000, 6144, 108000},
+ {5405, 4096, 108108, 6272, 120120, 6144, 108108},
+ {7417, 11648, 421875, 17836, 468750, 11648, 281250},
+ {7425, 4096, 148500, 6272, 165000, 6144, 148500},
+ {14835, 11648, 843750, 8918, 468750, 11648, 281250},
+ {14850, 4096, 297000, 6272, 330000, 6144, 297000},
+ {29670, 5824, 843750, 4459, 468750, 5824, 562500},
+ {29700, 3072, 445500, 4704, 495000, 5120, 495000}
+
+
+};
+
+static union audio_cea_channels speakers_to_channels(
+ struct audio_speaker_flags speaker_flags)
+{
+ union audio_cea_channels cea_channels = {0};
+
+ /* these are one to one */
+ cea_channels.channels.FL = speaker_flags.FL_FR;
+ cea_channels.channels.FR = speaker_flags.FL_FR;
+ cea_channels.channels.LFE = speaker_flags.LFE;
+ cea_channels.channels.FC = speaker_flags.FC;
+
+ /* if Rear Left and Right exist move RC speaker to channel 7
+ * otherwise to channel 5
+ */
+ if (speaker_flags.RL_RR) {
+ cea_channels.channels.RL_RC = speaker_flags.RL_RR;
+ cea_channels.channels.RR = speaker_flags.RL_RR;
+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
+ } else {
+ cea_channels.channels.RL_RC = speaker_flags.RC;
+ }
+
+ /* FRONT Left Right Center and REAR Left Right Center are exclusive */
+ if (speaker_flags.FLC_FRC) {
+ cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
+ cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
+ } else {
+ cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
+ cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
+ }
+
+ return cea_channels;
+}
+
+static uint32_t calc_max_audio_packets_per_line(
+ const struct audio_crtc_info *crtc_info)
+{
+ uint32_t max_packets_per_line;
+
+ max_packets_per_line =
+ crtc_info->h_total - crtc_info->h_active;
+
+ if (crtc_info->pixel_repetition)
+ max_packets_per_line *= crtc_info->pixel_repetition;
+
+ /* for other hdmi features */
+ max_packets_per_line -= 58;
+ /* for Control Period */
+ max_packets_per_line -= 16;
+ /* Number of Audio Packets per Line */
+ max_packets_per_line /= 32;
+
+ return max_packets_per_line;
+}
+
+static void get_audio_clock_info(
+ enum dc_color_depth color_depth,
+ uint32_t crtc_pixel_clock_in_khz,
+ uint32_t actual_pixel_clock_in_khz,
+ struct audio_clock_info *audio_clock_info)
+{
+ const struct audio_clock_info *clock_info;
+ uint32_t index;
+ uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
+ uint32_t audio_array_size;
+
+ switch (color_depth) {
+ case COLOR_DEPTH_161616:
+ clock_info = audio_clock_info_table_48bpc;
+ audio_array_size = ARRAY_SIZE(
+ audio_clock_info_table_48bpc);
+ break;
+ case COLOR_DEPTH_121212:
+ clock_info = audio_clock_info_table_36bpc;
+ audio_array_size = ARRAY_SIZE(
+ audio_clock_info_table_36bpc);
+ break;
+ default:
+ clock_info = audio_clock_info_table;
+ audio_array_size = ARRAY_SIZE(
+ audio_clock_info_table);
+ break;
+ }
+
+ if (clock_info != NULL) {
+ /* search for exact pixel clock in table */
+ for (index = 0; index < audio_array_size; index++) {
+ if (clock_info[index].pixel_clock_in_10khz >
+ crtc_pixel_clock_in_10khz)
+ break; /* not match */
+ else if (clock_info[index].pixel_clock_in_10khz ==
+ crtc_pixel_clock_in_10khz) {
+ /* match found */
+ *audio_clock_info = clock_info[index];
+ return;
+ }
+ }
+ }
+
+ /* not found */
+ if (actual_pixel_clock_in_khz == 0)
+ actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
+
+ /* See HDMI spec the table entry under
+ * pixel clock of "Other". */
+ audio_clock_info->pixel_clock_in_10khz =
+ actual_pixel_clock_in_khz / 10;
+ audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
+ audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
+ audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
+
+ audio_clock_info->n_32khz = 4096;
+ audio_clock_info->n_44khz = 6272;
+ audio_clock_info->n_48khz = 6144;
+}
+
+static void enc1_se_audio_setup(
+ struct stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *audio_info)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ uint32_t speakers = 0;
+ uint32_t channels = 0;
+
+ ASSERT(audio_info);
+ if (audio_info == NULL)
+ /* This should not happen.it does so we don't get BSOD*/
+ return;
+
+ speakers = audio_info->flags.info.ALLSPEAKERS;
+ channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
+
+ /* setup the audio stream source select (audio -> dig mapping) */
+ REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
+
+ /* Channel allocation */
+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
+}
+
+static void enc1_se_setup_hdmi_audio(
+ struct stream_encoder *enc,
+ const struct audio_crtc_info *crtc_info)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ struct audio_clock_info audio_clock_info = {0};
+ uint32_t max_packets_per_line;
+
+ /* For now still do calculation, although this field is ignored when
+ * above HDMI_PACKET_GEN_VERSION set to 1
+ */
+ max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
+
+ /* HDMI_AUDIO_PACKET_CONTROL */
+ REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
+ HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
+ HDMI_AUDIO_DELAY_EN, 1);
+
+ /* AFMT_AUDIO_PACKET_CONTROL */
+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
+
+ /* AFMT_AUDIO_PACKET_CONTROL2 */
+ REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
+ AFMT_AUDIO_LAYOUT_OVRD, 0,
+ AFMT_60958_OSF_OVRD, 0);
+
+ /* HDMI_ACR_PACKET_CONTROL */
+ REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
+ HDMI_ACR_AUTO_SEND, 1,
+ HDMI_ACR_SOURCE, 0,
+ HDMI_ACR_AUDIO_PRIORITY, 0);
+
+ /* Program audio clock sample/regeneration parameters */
+ get_audio_clock_info(crtc_info->color_depth,
+ crtc_info->requested_pixel_clock,
+ crtc_info->calculated_pixel_clock,
+ &audio_clock_info);
+ DC_LOG_HW_AUDIO(
+ "\n%s:Input::requested_pixel_clock = %d" \
+ "calculated_pixel_clock = %d \n", __func__, \
+ crtc_info->requested_pixel_clock, \
+ crtc_info->calculated_pixel_clock);
+
+ /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
+ REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
+
+ /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
+ REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
+
+ /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
+ REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
+
+ /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
+ REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
+
+ /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
+ REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
+
+ /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
+ REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
+
+ /* Video driver cannot know in advance which sample rate will
+ * be used by HD Audio driver
+ * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
+ * programmed below in interruppt callback
+ */
+
+ /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
+ * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
+ */
+ REG_UPDATE_2(AFMT_60958_0,
+ AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
+ AFMT_60958_CS_CLOCK_ACCURACY, 0);
+
+ /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
+ REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
+
+ /* AFMT_60958_2 now keep this settings until
+ * Programming guide comes out
+ */
+ REG_UPDATE_6(AFMT_60958_2,
+ AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
+ AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
+ AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
+ AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
+ AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
+ AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
+}
+
+static void enc1_se_setup_dp_audio(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ /* --- DP Audio packet configurations --- */
+
+ /* ATP Configuration */
+ REG_SET(DP_SEC_AUD_N, 0,
+ DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
+
+ /* Async/auto-calc timestamp mode */
+ REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
+ DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
+
+ /* --- The following are the registers
+ * copied from the SetupHDMI ---
+ */
+
+ /* AFMT_AUDIO_PACKET_CONTROL */
+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
+
+ /* AFMT_AUDIO_PACKET_CONTROL2 */
+ /* Program the ATP and AIP next */
+ REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
+ AFMT_AUDIO_LAYOUT_OVRD, 0,
+ AFMT_60958_OSF_OVRD, 0);
+
+ /* AFMT_INFOFRAME_CONTROL0 */
+ REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
+
+ /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
+ REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
+}
+
+static void enc1_se_enable_audio_clock(
+ struct stream_encoder *enc,
+ bool enable)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ if (REG(AFMT_CNTL) == 0)
+ return; /* DCE8/10 does not have this register */
+
+ REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
+
+ /* wait for AFMT clock to turn on,
+ * expectation: this should complete in 1-2 reads
+ *
+ * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
+ *
+ * TODO: wait for clock_on does not work well. May need HW
+ * program sequence. But audio seems work normally even without wait
+ * for clock_on status change
+ */
+}
+
+static void enc1_se_enable_dp_audio(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ /* Enable Audio packets */
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
+
+ /* Program the ATP and AIP next */
+ REG_UPDATE_2(DP_SEC_CNTL,
+ DP_SEC_ATP_ENABLE, 1,
+ DP_SEC_AIP_ENABLE, 1);
+
+ /* Program STREAM_ENABLE after all the other enables. */
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
+}
+
+static void enc1_se_disable_dp_audio(
+ struct stream_encoder *enc)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t value = REG_READ(DP_SEC_CNTL);
+
+ /* Disable Audio packets */
+ REG_UPDATE_5(DP_SEC_CNTL,
+ DP_SEC_ASP_ENABLE, 0,
+ DP_SEC_ATP_ENABLE, 0,
+ DP_SEC_AIP_ENABLE, 0,
+ DP_SEC_ACM_ENABLE, 0,
+ DP_SEC_STREAM_ENABLE, 0);
+
+ /* This register shared with encoder info frame. Therefore we need to
+ * keep master enabled if at least on of the fields is not 0
+ */
+ if (value != 0)
+ REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
+
+}
+
+void enc1_se_audio_mute_control(
+ struct stream_encoder *enc,
+ bool mute)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+ REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
+}
+
+void enc1_se_dp_audio_setup(
+ struct stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *info)
+{
+ enc1_se_audio_setup(enc, az_inst, info);
+}
+
+void enc1_se_dp_audio_enable(
+ struct stream_encoder *enc)
+{
+ enc1_se_enable_audio_clock(enc, true);
+ enc1_se_setup_dp_audio(enc);
+ enc1_se_enable_dp_audio(enc);
+}
+
+void enc1_se_dp_audio_disable(
+ struct stream_encoder *enc)
+{
+ enc1_se_disable_dp_audio(enc);
+ enc1_se_enable_audio_clock(enc, false);
+}
+
+void enc1_se_hdmi_audio_setup(
+ struct stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *info,
+ struct audio_crtc_info *audio_crtc_info)
+{
+ enc1_se_enable_audio_clock(enc, true);
+ enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
+ enc1_se_audio_setup(enc, az_inst, info);
+}
+
+void enc1_se_hdmi_audio_disable(
+ struct stream_encoder *enc)
+{
+ enc1_se_enable_audio_clock(enc, false);
+}
+
+
+static void enc1_setup_stereo_sync(
+ struct stream_encoder *enc,
+ int tg_inst, bool enable)
+{
+ struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
+ REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
+}
+
+
+static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
+ .dp_set_stream_attribute =
+ enc1_stream_encoder_dp_set_stream_attribute,
+ .hdmi_set_stream_attribute =
+ enc1_stream_encoder_hdmi_set_stream_attribute,
+ .dvi_set_stream_attribute =
+ enc1_stream_encoder_dvi_set_stream_attribute,
+ .set_mst_bandwidth =
+ enc1_stream_encoder_set_mst_bandwidth,
+ .update_hdmi_info_packets =
+ enc1_stream_encoder_update_hdmi_info_packets,
+ .stop_hdmi_info_packets =
+ enc1_stream_encoder_stop_hdmi_info_packets,
+ .update_dp_info_packets =
+ enc1_stream_encoder_update_dp_info_packets,
+ .stop_dp_info_packets =
+ enc1_stream_encoder_stop_dp_info_packets,
+ .dp_blank =
+ enc1_stream_encoder_dp_blank,
+ .dp_unblank =
+ enc1_stream_encoder_dp_unblank,
+ .audio_mute_control = enc1_se_audio_mute_control,
+
+ .dp_audio_setup = enc1_se_dp_audio_setup,
+ .dp_audio_enable = enc1_se_dp_audio_enable,
+ .dp_audio_disable = enc1_se_dp_audio_disable,
+
+ .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
+ .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
+ .setup_stereo_sync = enc1_setup_stereo_sync,
+ .set_avmute = enc1_stream_encoder_set_avmute,
+};
+
+void dcn10_stream_encoder_construct(
+ struct dcn10_stream_encoder *enc1,
+ struct dc_context *ctx,
+ struct dc_bios *bp,
+ enum engine_id eng_id,
+ const struct dcn10_stream_enc_registers *regs,
+ const struct dcn10_stream_encoder_shift *se_shift,
+ const struct dcn10_stream_encoder_mask *se_mask)
+{
+ enc1->base.funcs = &dcn10_str_enc_funcs;
+ enc1->base.ctx = ctx;
+ enc1->base.id = eng_id;
+ enc1->base.bp = bp;
+ enc1->regs = regs;
+ enc1->se_shift = se_shift;
+ enc1->se_mask = se_mask;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
new file mode 100644
index 000000000000..86f8ee5ed8b8
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_STREAM_ENCODER_DCN10_H__
+#define __DC_STREAM_ENCODER_DCN10_H__
+
+#include "stream_encoder.h"
+
+#define DCN10STRENC_FROM_STRENC(stream_encoder)\
+ container_of(stream_encoder, struct dcn10_stream_encoder, base)
+
+#define SE_COMMON_REG_LIST_BASE(id) \
+ SRI(AFMT_GENERIC_0, DIG, id), \
+ SRI(AFMT_GENERIC_1, DIG, id), \
+ SRI(AFMT_GENERIC_2, DIG, id), \
+ SRI(AFMT_GENERIC_3, DIG, id), \
+ SRI(AFMT_GENERIC_4, DIG, id), \
+ SRI(AFMT_GENERIC_5, DIG, id), \
+ SRI(AFMT_GENERIC_6, DIG, id), \
+ SRI(AFMT_GENERIC_7, DIG, id), \
+ SRI(AFMT_GENERIC_HDR, DIG, id), \
+ SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
+ SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
+ SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
+ SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
+ SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
+ SRI(AFMT_60958_0, DIG, id), \
+ SRI(AFMT_60958_1, DIG, id), \
+ SRI(AFMT_60958_2, DIG, id), \
+ SRI(DIG_FE_CNTL, DIG, id), \
+ SRI(HDMI_CONTROL, DIG, id), \
+ SRI(HDMI_GC, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
+ SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
+ SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
+ SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
+ SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
+ SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
+ SRI(HDMI_ACR_32_0, DIG, id),\
+ SRI(HDMI_ACR_32_1, DIG, id),\
+ SRI(HDMI_ACR_44_0, DIG, id),\
+ SRI(HDMI_ACR_44_1, DIG, id),\
+ SRI(HDMI_ACR_48_0, DIG, id),\
+ SRI(HDMI_ACR_48_1, DIG, id),\
+ SRI(TMDS_CNTL, DIG, id), \
+ SRI(DP_MSE_RATE_CNTL, DP, id), \
+ SRI(DP_MSE_RATE_UPDATE, DP, id), \
+ SRI(DP_PIXEL_FORMAT, DP, id), \
+ SRI(DP_SEC_CNTL, DP, id), \
+ SRI(DP_STEER_FIFO, DP, id), \
+ SRI(DP_VID_M, DP, id), \
+ SRI(DP_VID_N, DP, id), \
+ SRI(DP_VID_STREAM_CNTL, DP, id), \
+ SRI(DP_VID_TIMING, DP, id), \
+ SRI(DP_SEC_AUD_N, DP, id), \
+ SRI(DP_SEC_TIMESTAMP, DP, id)
+
+#define SE_DCN_REG_LIST(id)\
+ SE_COMMON_REG_LIST_BASE(id),\
+ SRI(AFMT_CNTL, DIG, id),\
+ SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
+ SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
+ SRI(DP_DB_CNTL, DP, id), \
+ SRI(DP_MSA_MISC, DP, id), \
+ SRI(DP_MSA_COLORIMETRY, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM1, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM2, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM3, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM4, DP, id), \
+ SRI(HDMI_DB_CONTROL, DIG, id)
+
+#define SE_SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
+ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
+ SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
+ SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
+ SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
+ SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
+ SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
+ SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
+ SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
+ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
+ SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
+ SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
+ SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
+ SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
+ SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
+ SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
+ SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
+ SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
+ SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
+ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
+ SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
+ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
+ SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
+ SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
+ SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
+ SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
+ SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
+
+#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
+ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
+ SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
+
+struct dcn10_stream_encoder_shift {
+ uint8_t AFMT_GENERIC_INDEX;
+ uint8_t AFMT_GENERIC_HB0;
+ uint8_t AFMT_GENERIC_HB1;
+ uint8_t AFMT_GENERIC_HB2;
+ uint8_t AFMT_GENERIC_HB3;
+ uint8_t AFMT_GENERIC_LOCK_STATUS;
+ uint8_t AFMT_GENERIC_CONFLICT;
+ uint8_t AFMT_GENERIC_CONFLICT_CLR;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint8_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint8_t AFMT_GENERIC7_FRAME_UPDATE;
+ uint8_t HDMI_GENERIC0_CONT;
+ uint8_t HDMI_GENERIC0_SEND;
+ uint8_t HDMI_GENERIC0_LINE;
+ uint8_t HDMI_GENERIC1_CONT;
+ uint8_t HDMI_GENERIC1_SEND;
+ uint8_t HDMI_GENERIC1_LINE;
+ uint8_t HDMI_GENERIC2_CONT;
+ uint8_t HDMI_GENERIC2_SEND;
+ uint8_t HDMI_GENERIC2_LINE;
+ uint8_t HDMI_GENERIC3_CONT;
+ uint8_t HDMI_GENERIC3_SEND;
+ uint8_t HDMI_GENERIC3_LINE;
+ uint8_t HDMI_GENERIC4_CONT;
+ uint8_t HDMI_GENERIC4_SEND;
+ uint8_t HDMI_GENERIC4_LINE;
+ uint8_t HDMI_GENERIC5_CONT;
+ uint8_t HDMI_GENERIC5_SEND;
+ uint8_t HDMI_GENERIC5_LINE;
+ uint8_t HDMI_GENERIC6_CONT;
+ uint8_t HDMI_GENERIC6_SEND;
+ uint8_t HDMI_GENERIC6_LINE;
+ uint8_t HDMI_GENERIC7_CONT;
+ uint8_t HDMI_GENERIC7_SEND;
+ uint8_t HDMI_GENERIC7_LINE;
+ uint8_t DP_PIXEL_ENCODING;
+ uint8_t DP_COMPONENT_DEPTH;
+ uint8_t HDMI_PACKET_GEN_VERSION;
+ uint8_t HDMI_KEEPOUT_MODE;
+ uint8_t HDMI_DEEP_COLOR_ENABLE;
+ uint8_t HDMI_CLOCK_CHANNEL_RATE;
+ uint8_t HDMI_DEEP_COLOR_DEPTH;
+ uint8_t HDMI_GC_CONT;
+ uint8_t HDMI_GC_SEND;
+ uint8_t HDMI_NULL_SEND;
+ uint8_t HDMI_DATA_SCRAMBLE_EN;
+ uint8_t HDMI_AUDIO_INFO_SEND;
+ uint8_t AFMT_AUDIO_INFO_UPDATE;
+ uint8_t HDMI_AUDIO_INFO_LINE;
+ uint8_t HDMI_GC_AVMUTE;
+ uint8_t DP_MSE_RATE_X;
+ uint8_t DP_MSE_RATE_Y;
+ uint8_t DP_MSE_RATE_UPDATE_PENDING;
+ uint8_t DP_SEC_GSP0_ENABLE;
+ uint8_t DP_SEC_STREAM_ENABLE;
+ uint8_t DP_SEC_GSP1_ENABLE;
+ uint8_t DP_SEC_GSP2_ENABLE;
+ uint8_t DP_SEC_GSP3_ENABLE;
+ uint8_t DP_SEC_GSP4_ENABLE;
+ uint8_t DP_SEC_GSP5_ENABLE;
+ uint8_t DP_SEC_GSP6_ENABLE;
+ uint8_t DP_SEC_GSP7_ENABLE;
+ uint8_t DP_SEC_MPG_ENABLE;
+ uint8_t DP_VID_STREAM_DIS_DEFER;
+ uint8_t DP_VID_STREAM_ENABLE;
+ uint8_t DP_VID_STREAM_STATUS;
+ uint8_t DP_STEER_FIFO_RESET;
+ uint8_t DP_VID_M_N_GEN_EN;
+ uint8_t DP_VID_N;
+ uint8_t DP_VID_M;
+ uint8_t DIG_START;
+ uint8_t AFMT_AUDIO_SRC_SELECT;
+ uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
+ uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
+ uint8_t HDMI_AUDIO_DELAY_EN;
+ uint8_t AFMT_60958_CS_UPDATE;
+ uint8_t AFMT_AUDIO_LAYOUT_OVRD;
+ uint8_t AFMT_60958_OSF_OVRD;
+ uint8_t HDMI_ACR_AUTO_SEND;
+ uint8_t HDMI_ACR_SOURCE;
+ uint8_t HDMI_ACR_AUDIO_PRIORITY;
+ uint8_t HDMI_ACR_CTS_32;
+ uint8_t HDMI_ACR_N_32;
+ uint8_t HDMI_ACR_CTS_44;
+ uint8_t HDMI_ACR_N_44;
+ uint8_t HDMI_ACR_CTS_48;
+ uint8_t HDMI_ACR_N_48;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
+ uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
+ uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
+ uint8_t DP_SEC_AUD_N;
+ uint8_t DP_SEC_TIMESTAMP_MODE;
+ uint8_t DP_SEC_ASP_ENABLE;
+ uint8_t DP_SEC_ATP_ENABLE;
+ uint8_t DP_SEC_AIP_ENABLE;
+ uint8_t DP_SEC_ACM_ENABLE;
+ uint8_t AFMT_AUDIO_SAMPLE_SEND;
+ uint8_t AFMT_AUDIO_CLOCK_EN;
+ uint8_t TMDS_PIXEL_ENCODING;
+ uint8_t TMDS_COLOR_FORMAT;
+ uint8_t DIG_STEREOSYNC_SELECT;
+ uint8_t DIG_STEREOSYNC_GATE_EN;
+ uint8_t DP_DB_DISABLE;
+ uint8_t DP_MSA_MISC0;
+ uint8_t DP_MSA_HTOTAL;
+ uint8_t DP_MSA_VTOTAL;
+ uint8_t DP_MSA_HSTART;
+ uint8_t DP_MSA_VSTART;
+ uint8_t DP_MSA_HSYNCWIDTH;
+ uint8_t DP_MSA_HSYNCPOLARITY;
+ uint8_t DP_MSA_VSYNCWIDTH;
+ uint8_t DP_MSA_VSYNCPOLARITY;
+ uint8_t DP_MSA_HWIDTH;
+ uint8_t DP_MSA_VHEIGHT;
+ uint8_t HDMI_DB_DISABLE;
+ uint8_t DP_VID_N_MUL;
+ uint8_t DP_VID_M_DOUBLE_VALUE_EN;
+};
+
+struct dcn10_stream_encoder_mask {
+ uint32_t AFMT_GENERIC_INDEX;
+ uint32_t AFMT_GENERIC_HB0;
+ uint32_t AFMT_GENERIC_HB1;
+ uint32_t AFMT_GENERIC_HB2;
+ uint32_t AFMT_GENERIC_HB3;
+ uint32_t AFMT_GENERIC_LOCK_STATUS;
+ uint32_t AFMT_GENERIC_CONFLICT;
+ uint32_t AFMT_GENERIC_CONFLICT_CLR;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
+ uint32_t AFMT_GENERIC0_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC1_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC2_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC3_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC4_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC5_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC6_FRAME_UPDATE;
+ uint32_t AFMT_GENERIC7_FRAME_UPDATE;
+ uint32_t HDMI_GENERIC0_CONT;
+ uint32_t HDMI_GENERIC0_SEND;
+ uint32_t HDMI_GENERIC0_LINE;
+ uint32_t HDMI_GENERIC1_CONT;
+ uint32_t HDMI_GENERIC1_SEND;
+ uint32_t HDMI_GENERIC1_LINE;
+ uint32_t HDMI_GENERIC2_CONT;
+ uint32_t HDMI_GENERIC2_SEND;
+ uint32_t HDMI_GENERIC2_LINE;
+ uint32_t HDMI_GENERIC3_CONT;
+ uint32_t HDMI_GENERIC3_SEND;
+ uint32_t HDMI_GENERIC3_LINE;
+ uint32_t HDMI_GENERIC4_CONT;
+ uint32_t HDMI_GENERIC4_SEND;
+ uint32_t HDMI_GENERIC4_LINE;
+ uint32_t HDMI_GENERIC5_CONT;
+ uint32_t HDMI_GENERIC5_SEND;
+ uint32_t HDMI_GENERIC5_LINE;
+ uint32_t HDMI_GENERIC6_CONT;
+ uint32_t HDMI_GENERIC6_SEND;
+ uint32_t HDMI_GENERIC6_LINE;
+ uint32_t HDMI_GENERIC7_CONT;
+ uint32_t HDMI_GENERIC7_SEND;
+ uint32_t HDMI_GENERIC7_LINE;
+ uint32_t DP_PIXEL_ENCODING;
+ uint32_t DP_COMPONENT_DEPTH;
+ uint32_t HDMI_PACKET_GEN_VERSION;
+ uint32_t HDMI_KEEPOUT_MODE;
+ uint32_t HDMI_DEEP_COLOR_ENABLE;
+ uint32_t HDMI_CLOCK_CHANNEL_RATE;
+ uint32_t HDMI_DEEP_COLOR_DEPTH;
+ uint32_t HDMI_GC_CONT;
+ uint32_t HDMI_GC_SEND;
+ uint32_t HDMI_NULL_SEND;
+ uint32_t HDMI_DATA_SCRAMBLE_EN;
+ uint32_t HDMI_AUDIO_INFO_SEND;
+ uint32_t AFMT_AUDIO_INFO_UPDATE;
+ uint32_t HDMI_AUDIO_INFO_LINE;
+ uint32_t HDMI_GC_AVMUTE;
+ uint32_t DP_MSE_RATE_X;
+ uint32_t DP_MSE_RATE_Y;
+ uint32_t DP_MSE_RATE_UPDATE_PENDING;
+ uint32_t DP_SEC_GSP0_ENABLE;
+ uint32_t DP_SEC_STREAM_ENABLE;
+ uint32_t DP_SEC_GSP1_ENABLE;
+ uint32_t DP_SEC_GSP2_ENABLE;
+ uint32_t DP_SEC_GSP3_ENABLE;
+ uint32_t DP_SEC_GSP4_ENABLE;
+ uint32_t DP_SEC_GSP5_ENABLE;
+ uint32_t DP_SEC_GSP6_ENABLE;
+ uint32_t DP_SEC_GSP7_ENABLE;
+ uint32_t DP_SEC_MPG_ENABLE;
+ uint32_t DP_VID_STREAM_DIS_DEFER;
+ uint32_t DP_VID_STREAM_ENABLE;
+ uint32_t DP_VID_STREAM_STATUS;
+ uint32_t DP_STEER_FIFO_RESET;
+ uint32_t DP_VID_M_N_GEN_EN;
+ uint32_t DP_VID_N;
+ uint32_t DP_VID_M;
+ uint32_t DIG_START;
+ uint32_t AFMT_AUDIO_SRC_SELECT;
+ uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
+ uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
+ uint32_t HDMI_AUDIO_DELAY_EN;
+ uint32_t AFMT_60958_CS_UPDATE;
+ uint32_t AFMT_AUDIO_LAYOUT_OVRD;
+ uint32_t AFMT_60958_OSF_OVRD;
+ uint32_t HDMI_ACR_AUTO_SEND;
+ uint32_t HDMI_ACR_SOURCE;
+ uint32_t HDMI_ACR_AUDIO_PRIORITY;
+ uint32_t HDMI_ACR_CTS_32;
+ uint32_t HDMI_ACR_N_32;
+ uint32_t HDMI_ACR_CTS_44;
+ uint32_t HDMI_ACR_N_44;
+ uint32_t HDMI_ACR_CTS_48;
+ uint32_t HDMI_ACR_N_48;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
+ uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
+ uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
+ uint32_t DP_SEC_AUD_N;
+ uint32_t DP_SEC_TIMESTAMP_MODE;
+ uint32_t DP_SEC_ASP_ENABLE;
+ uint32_t DP_SEC_ATP_ENABLE;
+ uint32_t DP_SEC_AIP_ENABLE;
+ uint32_t DP_SEC_ACM_ENABLE;
+ uint32_t AFMT_AUDIO_SAMPLE_SEND;
+ uint32_t AFMT_AUDIO_CLOCK_EN;
+ uint32_t TMDS_PIXEL_ENCODING;
+ uint32_t DIG_STEREOSYNC_SELECT;
+ uint32_t DIG_STEREOSYNC_GATE_EN;
+ uint32_t TMDS_COLOR_FORMAT;
+ uint32_t DP_DB_DISABLE;
+ uint32_t DP_MSA_MISC0;
+ uint32_t DP_MSA_HTOTAL;
+ uint32_t DP_MSA_VTOTAL;
+ uint32_t DP_MSA_HSTART;
+ uint32_t DP_MSA_VSTART;
+ uint32_t DP_MSA_HSYNCWIDTH;
+ uint32_t DP_MSA_HSYNCPOLARITY;
+ uint32_t DP_MSA_VSYNCWIDTH;
+ uint32_t DP_MSA_VSYNCPOLARITY;
+ uint32_t DP_MSA_HWIDTH;
+ uint32_t DP_MSA_VHEIGHT;
+ uint32_t HDMI_DB_DISABLE;
+ uint32_t DP_VID_N_MUL;
+ uint32_t DP_VID_M_DOUBLE_VALUE_EN;
+};
+
+struct dcn10_stream_enc_registers {
+ uint32_t AFMT_CNTL;
+ uint32_t AFMT_AVI_INFO0;
+ uint32_t AFMT_AVI_INFO1;
+ uint32_t AFMT_AVI_INFO2;
+ uint32_t AFMT_AVI_INFO3;
+ uint32_t AFMT_GENERIC_0;
+ uint32_t AFMT_GENERIC_1;
+ uint32_t AFMT_GENERIC_2;
+ uint32_t AFMT_GENERIC_3;
+ uint32_t AFMT_GENERIC_4;
+ uint32_t AFMT_GENERIC_5;
+ uint32_t AFMT_GENERIC_6;
+ uint32_t AFMT_GENERIC_7;
+ uint32_t AFMT_GENERIC_HDR;
+ uint32_t AFMT_INFOFRAME_CONTROL0;
+ uint32_t AFMT_VBI_PACKET_CONTROL;
+ uint32_t AFMT_VBI_PACKET_CONTROL1;
+ uint32_t AFMT_AUDIO_PACKET_CONTROL;
+ uint32_t AFMT_AUDIO_PACKET_CONTROL2;
+ uint32_t AFMT_AUDIO_SRC_CONTROL;
+ uint32_t AFMT_60958_0;
+ uint32_t AFMT_60958_1;
+ uint32_t AFMT_60958_2;
+ uint32_t DIG_FE_CNTL;
+ uint32_t DP_MSE_RATE_CNTL;
+ uint32_t DP_MSE_RATE_UPDATE;
+ uint32_t DP_PIXEL_FORMAT;
+ uint32_t DP_SEC_CNTL;
+ uint32_t DP_STEER_FIFO;
+ uint32_t DP_VID_M;
+ uint32_t DP_VID_N;
+ uint32_t DP_VID_STREAM_CNTL;
+ uint32_t DP_VID_TIMING;
+ uint32_t DP_SEC_AUD_N;
+ uint32_t DP_SEC_TIMESTAMP;
+ uint32_t HDMI_CONTROL;
+ uint32_t HDMI_GC;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL0;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL1;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL2;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL3;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL4;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL5;
+ uint32_t HDMI_INFOFRAME_CONTROL0;
+ uint32_t HDMI_INFOFRAME_CONTROL1;
+ uint32_t HDMI_VBI_PACKET_CONTROL;
+ uint32_t HDMI_AUDIO_PACKET_CONTROL;
+ uint32_t HDMI_ACR_PACKET_CONTROL;
+ uint32_t HDMI_ACR_32_0;
+ uint32_t HDMI_ACR_32_1;
+ uint32_t HDMI_ACR_44_0;
+ uint32_t HDMI_ACR_44_1;
+ uint32_t HDMI_ACR_48_0;
+ uint32_t HDMI_ACR_48_1;
+ uint32_t TMDS_CNTL;
+ uint32_t DP_DB_CNTL;
+ uint32_t DP_MSA_MISC;
+ uint32_t DP_MSA_COLORIMETRY;
+ uint32_t DP_MSA_TIMING_PARAM1;
+ uint32_t DP_MSA_TIMING_PARAM2;
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
+};
+
+struct dcn10_stream_encoder {
+ struct stream_encoder base;
+ const struct dcn10_stream_enc_registers *regs;
+ const struct dcn10_stream_encoder_shift *se_shift;
+ const struct dcn10_stream_encoder_mask *se_mask;
+};
+
+void dcn10_stream_encoder_construct(
+ struct dcn10_stream_encoder *enc1,
+ struct dc_context *ctx,
+ struct dc_bios *bp,
+ enum engine_id eng_id,
+ const struct dcn10_stream_enc_registers *regs,
+ const struct dcn10_stream_encoder_shift *se_shift,
+ const struct dcn10_stream_encoder_mask *se_mask);
+
+#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 14/32] drm/amd/display: remove unused enum
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (12 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 13/32] drm/amd/display: Refactor stream encoder for HW review Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 15/32] drm/amd/display: fix link bw calculation for 422 and 420 encoding Harry Wentland
` (17 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jun Lei
From: Jun Lei <Jun.Lei@amd.com>
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 90f40eecc2bc..5e041b768412 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -370,12 +370,6 @@ struct dc_csc_adjustments {
struct fixed31_32 hue;
};
-enum {
- MAX_LANES = 2,
- MAX_COFUNC_PATH = 6,
- LAYER_INDEX_PRIMARY = -1,
-};
-
enum dpcd_downstream_port_max_bpc {
DOWN_STREAM_MAX_8BPC = 0,
DOWN_STREAM_MAX_10BPC,
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 15/32] drm/amd/display: fix link bw calculation for 422 and 420 encoding
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (13 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 14/32] drm/amd/display: remove unused enum Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 16/32] drm/amd/display: Fill calcs date from stream src/dst if available Harry Wentland
` (16 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Eric Yang
From: Eric Yang <Eric.Yang2@amd.com>
Link bw required is reduced when we have chroma subsampling.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 53 ++++++++++++++----------
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index e103ce8e0558..a6dcd4246c20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1378,37 +1378,48 @@ static uint32_t bandwidth_in_kbps_from_timing(
{
uint32_t bits_per_channel = 0;
uint32_t kbps;
- switch (timing->display_color_depth) {
- case COLOR_DEPTH_666:
- bits_per_channel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_channel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_channel = 10;
- break;
- case COLOR_DEPTH_121212:
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
bits_per_channel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_channel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_channel = 16;
- break;
- default:
- break;
+ else{
+
+ switch (timing->display_color_depth) {
+
+ case COLOR_DEPTH_666:
+ bits_per_channel = 6;
+ break;
+ case COLOR_DEPTH_888:
+ bits_per_channel = 8;
+ break;
+ case COLOR_DEPTH_101010:
+ bits_per_channel = 10;
+ break;
+ case COLOR_DEPTH_121212:
+ bits_per_channel = 12;
+ break;
+ case COLOR_DEPTH_141414:
+ bits_per_channel = 14;
+ break;
+ case COLOR_DEPTH_161616:
+ bits_per_channel = 16;
+ break;
+ default:
+ break;
+ }
}
ASSERT(bits_per_channel != 0);
kbps = timing->pix_clk_khz;
kbps *= bits_per_channel;
- if (timing->flags.Y_ONLY != 1)
+ if (timing->flags.Y_ONLY != 1) {
/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
kbps *= 3;
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ kbps /= 2;
+ else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ kbps = kbps * 2 / 3;
+ }
return kbps;
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 16/32] drm/amd/display: Fill calcs date from stream src/dst if available
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (14 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 15/32] drm/amd/display: fix link bw calculation for 422 and 420 encoding Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 17/32] drm/amd/display: Change disable backlight ramp change threshold from 0 to maximum value Harry Wentland
` (15 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jun Lei
From: Jun Lei <Jun.Lei@amd.com>
We would otherwise fallback to the timing, which would always give us
identity.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 4b719328afd6..56f46a065a93 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2933,6 +2933,19 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 4;
break;
}
+ } else if (pipe[i].stream->dst.width != 0 &&
+ pipe[i].stream->dst.height != 0 &&
+ pipe[i].stream->src.width != 0 &&
+ pipe[i].stream->src.height != 0) {
+ data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
+ data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
+ data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
+ data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
+ data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
+ data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
+ data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
+ data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
+ data->bytes_per_pixel[num_displays + 4] = 4;
} else {
data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 17/32] drm/amd/display: Change disable backlight ramp change threshold from 0 to maximum value.
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (15 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 16/32] drm/amd/display: Fill calcs date from stream src/dst if available Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 18/32] drm/amd/display: Update scaler v_active data if interlaced Harry Wentland
` (14 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Instead of user set brightness with range of percentage,
HLK test set brightness level with range of normal, this will result in
HLK test case set brightness from 0 to 255, DC set brightness with ramp is 0,
and disabled ramp change which will fail the HLK test.
Fix:
In case of unblank stream and turn on edp, change brightness level in
stream to 0xFFFFFFFF(actural maximum level is 0xFF), use that value as
a flag to recogonize this the case of resume from S3.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 ++
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d9efdd926145..0cd286f8eaa0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1982,7 +1982,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
return false;
if (stream) {
- if (stream->bl_pwm_level == 0)
+ if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
frame_ramp = 0;
((struct dc_stream_state *)stream)->bl_pwm_level = level;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 432bed63ea4a..99d192200797 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1036,7 +1036,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, true);
- stream->bl_pwm_level = 0;
+ stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
}
}
void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index e764cbad881b..f54d478ffc5c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -32,6 +32,8 @@
#include "inc/hw/link_encoder.h"
#include "core_status.h"
+#define EDP_BACKLIGHT_RAMP_DISABLE_LEVEL 0xFFFFFFFF
+
enum pipe_gating_control {
PIPE_GATING_CONTROL_DISABLE = 0,
PIPE_GATING_CONTROL_ENABLE,
--
2.15.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 18/32] drm/amd/display: Update scaler v_active data if interlaced
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (16 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 17/32] drm/amd/display: Change disable backlight ramp change threshold from 0 to maximum value Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 19/32] drm/amd/display: Make DCN stream encoder shareable Harry Wentland
` (13 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Dmytro Laktyushkin
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 1de8f5518782..b57c5404d9bc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -844,6 +844,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
pipe_ctx->plane_state->format);
+ if (pipe_ctx->stream->timing.flags.INTERLACE)
+ pipe_ctx->stream->dst.height *= 2;
+
calculate_scaling_ratios(pipe_ctx);
calculate_viewport(pipe_ctx);
@@ -864,6 +867,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
+ if (pipe_ctx->stream->timing.flags.INTERLACE)
+ pipe_ctx->plane_res.scl_data.v_active *= 2;
/* Taps calculations */
@@ -909,6 +914,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
plane_state->dst_rect.x,
plane_state->dst_rect.y);
+ if (pipe_ctx->stream->timing.flags.INTERLACE)
+ pipe_ctx->stream->dst.height /= 2;
+
return res;
}
--
2.15.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 19/32] drm/amd/display: Make DCN stream encoder shareable
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (17 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 18/32] drm/amd/display: Update scaler v_active data if interlaced Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 20/32] drm/amd/display: csc updates require FULL update Harry Wentland
` (12 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Eric Bernstein
From: Eric Bernstein <eric.bernstein@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/dc/dce/dce_stream_encoder.c | 39 +-
.../amd/display/dc/dcn10/dcn10_stream_encoder.c | 62 +-
.../amd/display/dc/dcn10/dcn10_stream_encoder.h | 646 ++++++++++-----------
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 17 +
4 files changed, 343 insertions(+), 421 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index b85fda5f38e8..07c32421c226 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -26,27 +26,10 @@
#include "dc_bios_types.h"
#include "dce_stream_encoder.h"
#include "reg_helper.h"
+#include "hw_shared.h"
+
#define DC_LOGGER \
enc110->base.ctx->logger
-enum DP_PIXEL_ENCODING {
-DP_PIXEL_ENCODING_RGB444 = 0x00000000,
-DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
-DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
-DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
-DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
-DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
-DP_PIXEL_ENCODING_RESERVED = 0x00000006,
-};
-
-
-enum DP_COMPONENT_DEPTH {
-DP_COMPONENT_DEPTH_6BPC = 0x00000000,
-DP_COMPONENT_DEPTH_8BPC = 0x00000001,
-DP_COMPONENT_DEPTH_10BPC = 0x00000002,
-DP_COMPONENT_DEPTH_12BPC = 0x00000003,
-DP_COMPONENT_DEPTH_16BPC = 0x00000004,
-DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
-};
#define REG(reg)\
@@ -314,11 +297,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR422);
+ DP_PIXEL_ENCODING_TYPE_YCBCR422);
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR444);
+ DP_PIXEL_ENCODING_TYPE_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -326,7 +309,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
* Color depth of Y-only could be
* 8, 10, 12, 16 bits */
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_Y_ONLY);
+ DP_PIXEL_ENCODING_TYPE_Y_ONLY);
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
@@ -334,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR420);
+ DP_PIXEL_ENCODING_TYPE_YCBCR420);
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
@@ -345,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_RGB444);
+ DP_PIXEL_ENCODING_TYPE_RGB444);
break;
}
@@ -363,20 +346,20 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_8BPC);
+ DP_COMPONENT_PIXEL_DEPTH_8BPC);
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_10BPC);
+ DP_COMPONENT_PIXEL_DEPTH_10BPC);
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_12BPC);
+ DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_6BPC);
+ DP_COMPONENT_PIXEL_DEPTH_6BPC);
break;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index 0413c707b921..9ec46f8fc7cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -26,29 +26,11 @@
#include "dc_bios_types.h"
#include "dcn10_stream_encoder.h"
-
#include "reg_helper.h"
+#include "hw_shared.h"
+
#define DC_LOGGER \
enc1->base.ctx->logger
-enum DP_PIXEL_ENCODING {
-DP_PIXEL_ENCODING_RGB444 = 0x00000000,
-DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
-DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
-DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
-DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
-DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
-DP_PIXEL_ENCODING_RESERVED = 0x00000006,
-};
-
-
-enum DP_COMPONENT_DEPTH {
-DP_COMPONENT_DEPTH_6BPC = 0x00000000,
-DP_COMPONENT_DEPTH_8BPC = 0x00000001,
-DP_COMPONENT_DEPTH_10BPC = 0x00000002,
-DP_COMPONENT_DEPTH_12BPC = 0x00000003,
-DP_COMPONENT_DEPTH_16BPC = 0x00000004,
-DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
-};
#define REG(reg)\
@@ -70,7 +52,7 @@ enum {
#define CTX \
enc1->base.ctx
-static void enc1_update_generic_info_packet(
+void enc1_update_generic_info_packet(
struct dcn10_stream_encoder *enc1,
uint32_t packet_index,
const struct dc_info_packet *info_packet)
@@ -260,7 +242,7 @@ static void enc1_update_hdmi_info_packet(
}
/* setup stream encoder in dp mode */
-static void enc1_stream_encoder_dp_set_stream_attribute(
+void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space)
@@ -284,11 +266,11 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR422);
+ DP_PIXEL_ENCODING_TYPE_YCBCR422);
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR444);
+ DP_PIXEL_ENCODING_TYPE_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -297,7 +279,7 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
* 8, 10, 12, 16 bits
*/
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_Y_ONLY);
+ DP_PIXEL_ENCODING_TYPE_Y_ONLY);
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
@@ -306,12 +288,12 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_YCBCR420);
+ DP_PIXEL_ENCODING_TYPE_YCBCR420);
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
- DP_PIXEL_ENCODING_RGB444);
+ DP_PIXEL_ENCODING_TYPE_RGB444);
break;
}
@@ -326,20 +308,20 @@ static void enc1_stream_encoder_dp_set_stream_attribute(
break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_8BPC);
+ DP_COMPONENT_PIXEL_DEPTH_8BPC);
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_10BPC);
+ DP_COMPONENT_PIXEL_DEPTH_10BPC);
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_12BPC);
+ DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
- DP_COMPONENT_DEPTH_6BPC);
+ DP_COMPONENT_PIXEL_DEPTH_6BPC);
break;
}
@@ -485,7 +467,7 @@ static void enc1_stream_encoder_set_stream_attribute_helper(
}
/* setup stream encoder in hdmi mode */
-static void enc1_stream_encoder_hdmi_set_stream_attribute(
+void enc1_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
int actual_pix_clk_khz,
@@ -591,7 +573,7 @@ static void enc1_stream_encoder_hdmi_set_stream_attribute(
}
/* setup stream encoder in dvi mode */
-static void enc1_stream_encoder_dvi_set_stream_attribute(
+void enc1_stream_encoder_dvi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
bool is_dual_link)
@@ -616,7 +598,7 @@ static void enc1_stream_encoder_dvi_set_stream_attribute(
enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
}
-static void enc1_stream_encoder_set_mst_bandwidth(
+void enc1_stream_encoder_set_mst_bandwidth(
struct stream_encoder *enc,
struct fixed31_32 avg_time_slots_per_mtp)
{
@@ -699,7 +681,7 @@ static void enc1_stream_encoder_stop_hdmi_info_packets(
HDMI_GENERIC1_SEND, 0);
}
-static void enc1_stream_encoder_update_dp_info_packets(
+void enc1_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame)
{
@@ -742,7 +724,7 @@ static void enc1_stream_encoder_update_dp_info_packets(
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
-static void enc1_stream_encoder_stop_dp_info_packets(
+void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc)
{
/* stop generic packets on DP */
@@ -770,7 +752,7 @@ static void enc1_stream_encoder_stop_dp_info_packets(
}
-static void enc1_stream_encoder_dp_blank(
+void enc1_stream_encoder_dp_blank(
struct stream_encoder *enc)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@@ -823,7 +805,7 @@ static void enc1_stream_encoder_dp_blank(
}
/* output video stream to link encoder */
-static void enc1_stream_encoder_dp_unblank(
+void enc1_stream_encoder_dp_unblank(
struct stream_encoder *enc,
const struct encoder_unblank_param *param)
{
@@ -885,7 +867,7 @@ static void enc1_stream_encoder_dp_unblank(
REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
}
-static void enc1_stream_encoder_set_avmute(
+void enc1_stream_encoder_set_avmute(
struct stream_encoder *enc,
bool enable)
{
@@ -1442,7 +1424,7 @@ void enc1_se_hdmi_audio_disable(
}
-static void enc1_setup_stereo_sync(
+void enc1_setup_stereo_sync(
struct stream_encoder *enc,
int tg_inst, bool enable)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 86f8ee5ed8b8..6b3e4ded155b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -31,7 +31,8 @@
#define DCN10STRENC_FROM_STRENC(stream_encoder)\
container_of(stream_encoder, struct dcn10_stream_encoder, base)
-#define SE_COMMON_REG_LIST_BASE(id) \
+#define SE_COMMON_DCN_REG_LIST(id) \
+ SRI(AFMT_CNTL, DIG, id), \
SRI(AFMT_GENERIC_0, DIG, id), \
SRI(AFMT_GENERIC_1, DIG, id), \
SRI(AFMT_GENERIC_2, DIG, id), \
@@ -43,6 +44,7 @@
SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
+ SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
@@ -51,9 +53,12 @@
SRI(AFMT_60958_2, DIG, id), \
SRI(DIG_FE_CNTL, DIG, id), \
SRI(HDMI_CONTROL, DIG, id), \
+ SRI(HDMI_DB_CONTROL, DIG, id), \
SRI(HDMI_GC, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
+ SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
@@ -65,7 +70,13 @@
SRI(HDMI_ACR_44_1, DIG, id),\
SRI(HDMI_ACR_48_0, DIG, id),\
SRI(HDMI_ACR_48_1, DIG, id),\
- SRI(TMDS_CNTL, DIG, id), \
+ SRI(DP_DB_CNTL, DP, id), \
+ SRI(DP_MSA_MISC, DP, id), \
+ SRI(DP_MSA_COLORIMETRY, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM1, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM2, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM3, DP, id), \
+ SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
@@ -79,19 +90,74 @@
SRI(DP_SEC_TIMESTAMP, DP, id)
#define SE_DCN_REG_LIST(id)\
- SE_COMMON_REG_LIST_BASE(id),\
- SRI(AFMT_CNTL, DIG, id),\
- SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\
- SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
- SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
- SRI(DP_DB_CNTL, DP, id), \
- SRI(DP_MSA_MISC, DP, id), \
- SRI(DP_MSA_COLORIMETRY, DP, id), \
- SRI(DP_MSA_TIMING_PARAM1, DP, id), \
- SRI(DP_MSA_TIMING_PARAM2, DP, id), \
- SRI(DP_MSA_TIMING_PARAM3, DP, id), \
- SRI(DP_MSA_TIMING_PARAM4, DP, id), \
- SRI(HDMI_DB_CONTROL, DIG, id)
+ SE_COMMON_DCN_REG_LIST(id)
+
+
+struct dcn10_stream_enc_registers {
+ uint32_t AFMT_CNTL;
+ uint32_t AFMT_AVI_INFO0;
+ uint32_t AFMT_AVI_INFO1;
+ uint32_t AFMT_AVI_INFO2;
+ uint32_t AFMT_AVI_INFO3;
+ uint32_t AFMT_GENERIC_0;
+ uint32_t AFMT_GENERIC_1;
+ uint32_t AFMT_GENERIC_2;
+ uint32_t AFMT_GENERIC_3;
+ uint32_t AFMT_GENERIC_4;
+ uint32_t AFMT_GENERIC_5;
+ uint32_t AFMT_GENERIC_6;
+ uint32_t AFMT_GENERIC_7;
+ uint32_t AFMT_GENERIC_HDR;
+ uint32_t AFMT_INFOFRAME_CONTROL0;
+ uint32_t AFMT_VBI_PACKET_CONTROL;
+ uint32_t AFMT_VBI_PACKET_CONTROL1;
+ uint32_t AFMT_AUDIO_PACKET_CONTROL;
+ uint32_t AFMT_AUDIO_PACKET_CONTROL2;
+ uint32_t AFMT_AUDIO_SRC_CONTROL;
+ uint32_t AFMT_60958_0;
+ uint32_t AFMT_60958_1;
+ uint32_t AFMT_60958_2;
+ uint32_t DIG_FE_CNTL;
+ uint32_t DP_MSE_RATE_CNTL;
+ uint32_t DP_MSE_RATE_UPDATE;
+ uint32_t DP_PIXEL_FORMAT;
+ uint32_t DP_SEC_CNTL;
+ uint32_t DP_STEER_FIFO;
+ uint32_t DP_VID_M;
+ uint32_t DP_VID_N;
+ uint32_t DP_VID_STREAM_CNTL;
+ uint32_t DP_VID_TIMING;
+ uint32_t DP_SEC_AUD_N;
+ uint32_t DP_SEC_TIMESTAMP;
+ uint32_t HDMI_CONTROL;
+ uint32_t HDMI_GC;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL0;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL1;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL2;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL3;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL4;
+ uint32_t HDMI_GENERIC_PACKET_CONTROL5;
+ uint32_t HDMI_INFOFRAME_CONTROL0;
+ uint32_t HDMI_INFOFRAME_CONTROL1;
+ uint32_t HDMI_VBI_PACKET_CONTROL;
+ uint32_t HDMI_AUDIO_PACKET_CONTROL;
+ uint32_t HDMI_ACR_PACKET_CONTROL;
+ uint32_t HDMI_ACR_32_0;
+ uint32_t HDMI_ACR_32_1;
+ uint32_t HDMI_ACR_44_0;
+ uint32_t HDMI_ACR_44_1;
+ uint32_t HDMI_ACR_48_0;
+ uint32_t HDMI_ACR_48_1;
+ uint32_t DP_DB_CNTL;
+ uint32_t DP_MSA_MISC;
+ uint32_t DP_MSA_COLORIMETRY;
+ uint32_t DP_MSA_TIMING_PARAM1;
+ uint32_t DP_MSA_TIMING_PARAM2;
+ uint32_t DP_MSA_TIMING_PARAM3;
+ uint32_t DP_MSA_TIMING_PARAM4;
+ uint32_t HDMI_DB_CONTROL;
+};
+
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -221,348 +287,151 @@
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
+
+#define SE_REG_FIELD_LIST_DCN1_0(type) \
+ type AFMT_GENERIC_INDEX;\
+ type AFMT_GENERIC_HB0;\
+ type AFMT_GENERIC_HB1;\
+ type AFMT_GENERIC_HB2;\
+ type AFMT_GENERIC_HB3;\
+ type AFMT_GENERIC_LOCK_STATUS;\
+ type AFMT_GENERIC_CONFLICT;\
+ type AFMT_GENERIC_CONFLICT_CLR;\
+ type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
+ type AFMT_GENERIC0_FRAME_UPDATE;\
+ type AFMT_GENERIC1_FRAME_UPDATE;\
+ type AFMT_GENERIC2_FRAME_UPDATE;\
+ type AFMT_GENERIC3_FRAME_UPDATE;\
+ type AFMT_GENERIC4_FRAME_UPDATE;\
+ type AFMT_GENERIC5_FRAME_UPDATE;\
+ type AFMT_GENERIC6_FRAME_UPDATE;\
+ type AFMT_GENERIC7_FRAME_UPDATE;\
+ type HDMI_GENERIC0_CONT;\
+ type HDMI_GENERIC0_SEND;\
+ type HDMI_GENERIC0_LINE;\
+ type HDMI_GENERIC1_CONT;\
+ type HDMI_GENERIC1_SEND;\
+ type HDMI_GENERIC1_LINE;\
+ type HDMI_GENERIC2_CONT;\
+ type HDMI_GENERIC2_SEND;\
+ type HDMI_GENERIC2_LINE;\
+ type HDMI_GENERIC3_CONT;\
+ type HDMI_GENERIC3_SEND;\
+ type HDMI_GENERIC3_LINE;\
+ type HDMI_GENERIC4_CONT;\
+ type HDMI_GENERIC4_SEND;\
+ type HDMI_GENERIC4_LINE;\
+ type HDMI_GENERIC5_CONT;\
+ type HDMI_GENERIC5_SEND;\
+ type HDMI_GENERIC5_LINE;\
+ type HDMI_GENERIC6_CONT;\
+ type HDMI_GENERIC6_SEND;\
+ type HDMI_GENERIC6_LINE;\
+ type HDMI_GENERIC7_CONT;\
+ type HDMI_GENERIC7_SEND;\
+ type HDMI_GENERIC7_LINE;\
+ type DP_PIXEL_ENCODING;\
+ type DP_COMPONENT_DEPTH;\
+ type HDMI_PACKET_GEN_VERSION;\
+ type HDMI_KEEPOUT_MODE;\
+ type HDMI_DEEP_COLOR_ENABLE;\
+ type HDMI_CLOCK_CHANNEL_RATE;\
+ type HDMI_DEEP_COLOR_DEPTH;\
+ type HDMI_GC_CONT;\
+ type HDMI_GC_SEND;\
+ type HDMI_NULL_SEND;\
+ type HDMI_DATA_SCRAMBLE_EN;\
+ type HDMI_AUDIO_INFO_SEND;\
+ type AFMT_AUDIO_INFO_UPDATE;\
+ type HDMI_AUDIO_INFO_LINE;\
+ type HDMI_GC_AVMUTE;\
+ type DP_MSE_RATE_X;\
+ type DP_MSE_RATE_Y;\
+ type DP_MSE_RATE_UPDATE_PENDING;\
+ type DP_SEC_GSP0_ENABLE;\
+ type DP_SEC_STREAM_ENABLE;\
+ type DP_SEC_GSP1_ENABLE;\
+ type DP_SEC_GSP2_ENABLE;\
+ type DP_SEC_GSP3_ENABLE;\
+ type DP_SEC_GSP4_ENABLE;\
+ type DP_SEC_GSP5_ENABLE;\
+ type DP_SEC_GSP6_ENABLE;\
+ type DP_SEC_GSP7_ENABLE;\
+ type DP_SEC_MPG_ENABLE;\
+ type DP_VID_STREAM_DIS_DEFER;\
+ type DP_VID_STREAM_ENABLE;\
+ type DP_VID_STREAM_STATUS;\
+ type DP_STEER_FIFO_RESET;\
+ type DP_VID_M_N_GEN_EN;\
+ type DP_VID_N;\
+ type DP_VID_M;\
+ type DIG_START;\
+ type AFMT_AUDIO_SRC_SELECT;\
+ type AFMT_AUDIO_CHANNEL_ENABLE;\
+ type HDMI_AUDIO_PACKETS_PER_LINE;\
+ type HDMI_AUDIO_DELAY_EN;\
+ type AFMT_60958_CS_UPDATE;\
+ type AFMT_AUDIO_LAYOUT_OVRD;\
+ type AFMT_60958_OSF_OVRD;\
+ type HDMI_ACR_AUTO_SEND;\
+ type HDMI_ACR_SOURCE;\
+ type HDMI_ACR_AUDIO_PRIORITY;\
+ type HDMI_ACR_CTS_32;\
+ type HDMI_ACR_N_32;\
+ type HDMI_ACR_CTS_44;\
+ type HDMI_ACR_N_44;\
+ type HDMI_ACR_CTS_48;\
+ type HDMI_ACR_N_48;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_L;\
+ type AFMT_60958_CS_CLOCK_ACCURACY;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_R;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_2;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_3;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_4;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_5;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_6;\
+ type AFMT_60958_CS_CHANNEL_NUMBER_7;\
+ type DP_SEC_AUD_N;\
+ type DP_SEC_TIMESTAMP_MODE;\
+ type DP_SEC_ASP_ENABLE;\
+ type DP_SEC_ATP_ENABLE;\
+ type DP_SEC_AIP_ENABLE;\
+ type DP_SEC_ACM_ENABLE;\
+ type AFMT_AUDIO_SAMPLE_SEND;\
+ type AFMT_AUDIO_CLOCK_EN;\
+ type TMDS_PIXEL_ENCODING;\
+ type TMDS_COLOR_FORMAT;\
+ type DIG_STEREOSYNC_SELECT;\
+ type DIG_STEREOSYNC_GATE_EN;\
+ type DP_DB_DISABLE;\
+ type DP_MSA_MISC0;\
+ type DP_MSA_HTOTAL;\
+ type DP_MSA_VTOTAL;\
+ type DP_MSA_HSTART;\
+ type DP_MSA_VSTART;\
+ type DP_MSA_HSYNCWIDTH;\
+ type DP_MSA_HSYNCPOLARITY;\
+ type DP_MSA_VSYNCWIDTH;\
+ type DP_MSA_VSYNCPOLARITY;\
+ type DP_MSA_HWIDTH;\
+ type DP_MSA_VHEIGHT;\
+ type HDMI_DB_DISABLE;\
+ type DP_VID_N_MUL;\
+ type DP_VID_M_DOUBLE_VALUE_EN
+
struct dcn10_stream_encoder_shift {
- uint8_t AFMT_GENERIC_INDEX;
- uint8_t AFMT_GENERIC_HB0;
- uint8_t AFMT_GENERIC_HB1;
- uint8_t AFMT_GENERIC_HB2;
- uint8_t AFMT_GENERIC_HB3;
- uint8_t AFMT_GENERIC_LOCK_STATUS;
- uint8_t AFMT_GENERIC_CONFLICT;
- uint8_t AFMT_GENERIC_CONFLICT_CLR;
- uint8_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
- uint8_t AFMT_GENERIC0_FRAME_UPDATE;
- uint8_t AFMT_GENERIC1_FRAME_UPDATE;
- uint8_t AFMT_GENERIC2_FRAME_UPDATE;
- uint8_t AFMT_GENERIC3_FRAME_UPDATE;
- uint8_t AFMT_GENERIC4_FRAME_UPDATE;
- uint8_t AFMT_GENERIC5_FRAME_UPDATE;
- uint8_t AFMT_GENERIC6_FRAME_UPDATE;
- uint8_t AFMT_GENERIC7_FRAME_UPDATE;
- uint8_t HDMI_GENERIC0_CONT;
- uint8_t HDMI_GENERIC0_SEND;
- uint8_t HDMI_GENERIC0_LINE;
- uint8_t HDMI_GENERIC1_CONT;
- uint8_t HDMI_GENERIC1_SEND;
- uint8_t HDMI_GENERIC1_LINE;
- uint8_t HDMI_GENERIC2_CONT;
- uint8_t HDMI_GENERIC2_SEND;
- uint8_t HDMI_GENERIC2_LINE;
- uint8_t HDMI_GENERIC3_CONT;
- uint8_t HDMI_GENERIC3_SEND;
- uint8_t HDMI_GENERIC3_LINE;
- uint8_t HDMI_GENERIC4_CONT;
- uint8_t HDMI_GENERIC4_SEND;
- uint8_t HDMI_GENERIC4_LINE;
- uint8_t HDMI_GENERIC5_CONT;
- uint8_t HDMI_GENERIC5_SEND;
- uint8_t HDMI_GENERIC5_LINE;
- uint8_t HDMI_GENERIC6_CONT;
- uint8_t HDMI_GENERIC6_SEND;
- uint8_t HDMI_GENERIC6_LINE;
- uint8_t HDMI_GENERIC7_CONT;
- uint8_t HDMI_GENERIC7_SEND;
- uint8_t HDMI_GENERIC7_LINE;
- uint8_t DP_PIXEL_ENCODING;
- uint8_t DP_COMPONENT_DEPTH;
- uint8_t HDMI_PACKET_GEN_VERSION;
- uint8_t HDMI_KEEPOUT_MODE;
- uint8_t HDMI_DEEP_COLOR_ENABLE;
- uint8_t HDMI_CLOCK_CHANNEL_RATE;
- uint8_t HDMI_DEEP_COLOR_DEPTH;
- uint8_t HDMI_GC_CONT;
- uint8_t HDMI_GC_SEND;
- uint8_t HDMI_NULL_SEND;
- uint8_t HDMI_DATA_SCRAMBLE_EN;
- uint8_t HDMI_AUDIO_INFO_SEND;
- uint8_t AFMT_AUDIO_INFO_UPDATE;
- uint8_t HDMI_AUDIO_INFO_LINE;
- uint8_t HDMI_GC_AVMUTE;
- uint8_t DP_MSE_RATE_X;
- uint8_t DP_MSE_RATE_Y;
- uint8_t DP_MSE_RATE_UPDATE_PENDING;
- uint8_t DP_SEC_GSP0_ENABLE;
- uint8_t DP_SEC_STREAM_ENABLE;
- uint8_t DP_SEC_GSP1_ENABLE;
- uint8_t DP_SEC_GSP2_ENABLE;
- uint8_t DP_SEC_GSP3_ENABLE;
- uint8_t DP_SEC_GSP4_ENABLE;
- uint8_t DP_SEC_GSP5_ENABLE;
- uint8_t DP_SEC_GSP6_ENABLE;
- uint8_t DP_SEC_GSP7_ENABLE;
- uint8_t DP_SEC_MPG_ENABLE;
- uint8_t DP_VID_STREAM_DIS_DEFER;
- uint8_t DP_VID_STREAM_ENABLE;
- uint8_t DP_VID_STREAM_STATUS;
- uint8_t DP_STEER_FIFO_RESET;
- uint8_t DP_VID_M_N_GEN_EN;
- uint8_t DP_VID_N;
- uint8_t DP_VID_M;
- uint8_t DIG_START;
- uint8_t AFMT_AUDIO_SRC_SELECT;
- uint8_t AFMT_AUDIO_CHANNEL_ENABLE;
- uint8_t HDMI_AUDIO_PACKETS_PER_LINE;
- uint8_t HDMI_AUDIO_DELAY_EN;
- uint8_t AFMT_60958_CS_UPDATE;
- uint8_t AFMT_AUDIO_LAYOUT_OVRD;
- uint8_t AFMT_60958_OSF_OVRD;
- uint8_t HDMI_ACR_AUTO_SEND;
- uint8_t HDMI_ACR_SOURCE;
- uint8_t HDMI_ACR_AUDIO_PRIORITY;
- uint8_t HDMI_ACR_CTS_32;
- uint8_t HDMI_ACR_N_32;
- uint8_t HDMI_ACR_CTS_44;
- uint8_t HDMI_ACR_N_44;
- uint8_t HDMI_ACR_CTS_48;
- uint8_t HDMI_ACR_N_48;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_L;
- uint8_t AFMT_60958_CS_CLOCK_ACCURACY;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_R;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_2;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_3;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_4;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_5;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_6;
- uint8_t AFMT_60958_CS_CHANNEL_NUMBER_7;
- uint8_t DP_SEC_AUD_N;
- uint8_t DP_SEC_TIMESTAMP_MODE;
- uint8_t DP_SEC_ASP_ENABLE;
- uint8_t DP_SEC_ATP_ENABLE;
- uint8_t DP_SEC_AIP_ENABLE;
- uint8_t DP_SEC_ACM_ENABLE;
- uint8_t AFMT_AUDIO_SAMPLE_SEND;
- uint8_t AFMT_AUDIO_CLOCK_EN;
- uint8_t TMDS_PIXEL_ENCODING;
- uint8_t TMDS_COLOR_FORMAT;
- uint8_t DIG_STEREOSYNC_SELECT;
- uint8_t DIG_STEREOSYNC_GATE_EN;
- uint8_t DP_DB_DISABLE;
- uint8_t DP_MSA_MISC0;
- uint8_t DP_MSA_HTOTAL;
- uint8_t DP_MSA_VTOTAL;
- uint8_t DP_MSA_HSTART;
- uint8_t DP_MSA_VSTART;
- uint8_t DP_MSA_HSYNCWIDTH;
- uint8_t DP_MSA_HSYNCPOLARITY;
- uint8_t DP_MSA_VSYNCWIDTH;
- uint8_t DP_MSA_VSYNCPOLARITY;
- uint8_t DP_MSA_HWIDTH;
- uint8_t DP_MSA_VHEIGHT;
- uint8_t HDMI_DB_DISABLE;
- uint8_t DP_VID_N_MUL;
- uint8_t DP_VID_M_DOUBLE_VALUE_EN;
+ SE_REG_FIELD_LIST_DCN1_0(uint8_t);
};
struct dcn10_stream_encoder_mask {
- uint32_t AFMT_GENERIC_INDEX;
- uint32_t AFMT_GENERIC_HB0;
- uint32_t AFMT_GENERIC_HB1;
- uint32_t AFMT_GENERIC_HB2;
- uint32_t AFMT_GENERIC_HB3;
- uint32_t AFMT_GENERIC_LOCK_STATUS;
- uint32_t AFMT_GENERIC_CONFLICT;
- uint32_t AFMT_GENERIC_CONFLICT_CLR;
- uint32_t AFMT_GENERIC0_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC1_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC2_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC3_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC4_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC5_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC6_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC7_FRAME_UPDATE_PENDING;
- uint32_t AFMT_GENERIC0_FRAME_UPDATE;
- uint32_t AFMT_GENERIC1_FRAME_UPDATE;
- uint32_t AFMT_GENERIC2_FRAME_UPDATE;
- uint32_t AFMT_GENERIC3_FRAME_UPDATE;
- uint32_t AFMT_GENERIC4_FRAME_UPDATE;
- uint32_t AFMT_GENERIC5_FRAME_UPDATE;
- uint32_t AFMT_GENERIC6_FRAME_UPDATE;
- uint32_t AFMT_GENERIC7_FRAME_UPDATE;
- uint32_t HDMI_GENERIC0_CONT;
- uint32_t HDMI_GENERIC0_SEND;
- uint32_t HDMI_GENERIC0_LINE;
- uint32_t HDMI_GENERIC1_CONT;
- uint32_t HDMI_GENERIC1_SEND;
- uint32_t HDMI_GENERIC1_LINE;
- uint32_t HDMI_GENERIC2_CONT;
- uint32_t HDMI_GENERIC2_SEND;
- uint32_t HDMI_GENERIC2_LINE;
- uint32_t HDMI_GENERIC3_CONT;
- uint32_t HDMI_GENERIC3_SEND;
- uint32_t HDMI_GENERIC3_LINE;
- uint32_t HDMI_GENERIC4_CONT;
- uint32_t HDMI_GENERIC4_SEND;
- uint32_t HDMI_GENERIC4_LINE;
- uint32_t HDMI_GENERIC5_CONT;
- uint32_t HDMI_GENERIC5_SEND;
- uint32_t HDMI_GENERIC5_LINE;
- uint32_t HDMI_GENERIC6_CONT;
- uint32_t HDMI_GENERIC6_SEND;
- uint32_t HDMI_GENERIC6_LINE;
- uint32_t HDMI_GENERIC7_CONT;
- uint32_t HDMI_GENERIC7_SEND;
- uint32_t HDMI_GENERIC7_LINE;
- uint32_t DP_PIXEL_ENCODING;
- uint32_t DP_COMPONENT_DEPTH;
- uint32_t HDMI_PACKET_GEN_VERSION;
- uint32_t HDMI_KEEPOUT_MODE;
- uint32_t HDMI_DEEP_COLOR_ENABLE;
- uint32_t HDMI_CLOCK_CHANNEL_RATE;
- uint32_t HDMI_DEEP_COLOR_DEPTH;
- uint32_t HDMI_GC_CONT;
- uint32_t HDMI_GC_SEND;
- uint32_t HDMI_NULL_SEND;
- uint32_t HDMI_DATA_SCRAMBLE_EN;
- uint32_t HDMI_AUDIO_INFO_SEND;
- uint32_t AFMT_AUDIO_INFO_UPDATE;
- uint32_t HDMI_AUDIO_INFO_LINE;
- uint32_t HDMI_GC_AVMUTE;
- uint32_t DP_MSE_RATE_X;
- uint32_t DP_MSE_RATE_Y;
- uint32_t DP_MSE_RATE_UPDATE_PENDING;
- uint32_t DP_SEC_GSP0_ENABLE;
- uint32_t DP_SEC_STREAM_ENABLE;
- uint32_t DP_SEC_GSP1_ENABLE;
- uint32_t DP_SEC_GSP2_ENABLE;
- uint32_t DP_SEC_GSP3_ENABLE;
- uint32_t DP_SEC_GSP4_ENABLE;
- uint32_t DP_SEC_GSP5_ENABLE;
- uint32_t DP_SEC_GSP6_ENABLE;
- uint32_t DP_SEC_GSP7_ENABLE;
- uint32_t DP_SEC_MPG_ENABLE;
- uint32_t DP_VID_STREAM_DIS_DEFER;
- uint32_t DP_VID_STREAM_ENABLE;
- uint32_t DP_VID_STREAM_STATUS;
- uint32_t DP_STEER_FIFO_RESET;
- uint32_t DP_VID_M_N_GEN_EN;
- uint32_t DP_VID_N;
- uint32_t DP_VID_M;
- uint32_t DIG_START;
- uint32_t AFMT_AUDIO_SRC_SELECT;
- uint32_t AFMT_AUDIO_CHANNEL_ENABLE;
- uint32_t HDMI_AUDIO_PACKETS_PER_LINE;
- uint32_t HDMI_AUDIO_DELAY_EN;
- uint32_t AFMT_60958_CS_UPDATE;
- uint32_t AFMT_AUDIO_LAYOUT_OVRD;
- uint32_t AFMT_60958_OSF_OVRD;
- uint32_t HDMI_ACR_AUTO_SEND;
- uint32_t HDMI_ACR_SOURCE;
- uint32_t HDMI_ACR_AUDIO_PRIORITY;
- uint32_t HDMI_ACR_CTS_32;
- uint32_t HDMI_ACR_N_32;
- uint32_t HDMI_ACR_CTS_44;
- uint32_t HDMI_ACR_N_44;
- uint32_t HDMI_ACR_CTS_48;
- uint32_t HDMI_ACR_N_48;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_L;
- uint32_t AFMT_60958_CS_CLOCK_ACCURACY;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_R;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_2;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_3;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_4;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_5;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_6;
- uint32_t AFMT_60958_CS_CHANNEL_NUMBER_7;
- uint32_t DP_SEC_AUD_N;
- uint32_t DP_SEC_TIMESTAMP_MODE;
- uint32_t DP_SEC_ASP_ENABLE;
- uint32_t DP_SEC_ATP_ENABLE;
- uint32_t DP_SEC_AIP_ENABLE;
- uint32_t DP_SEC_ACM_ENABLE;
- uint32_t AFMT_AUDIO_SAMPLE_SEND;
- uint32_t AFMT_AUDIO_CLOCK_EN;
- uint32_t TMDS_PIXEL_ENCODING;
- uint32_t DIG_STEREOSYNC_SELECT;
- uint32_t DIG_STEREOSYNC_GATE_EN;
- uint32_t TMDS_COLOR_FORMAT;
- uint32_t DP_DB_DISABLE;
- uint32_t DP_MSA_MISC0;
- uint32_t DP_MSA_HTOTAL;
- uint32_t DP_MSA_VTOTAL;
- uint32_t DP_MSA_HSTART;
- uint32_t DP_MSA_VSTART;
- uint32_t DP_MSA_HSYNCWIDTH;
- uint32_t DP_MSA_HSYNCPOLARITY;
- uint32_t DP_MSA_VSYNCWIDTH;
- uint32_t DP_MSA_VSYNCPOLARITY;
- uint32_t DP_MSA_HWIDTH;
- uint32_t DP_MSA_VHEIGHT;
- uint32_t HDMI_DB_DISABLE;
- uint32_t DP_VID_N_MUL;
- uint32_t DP_VID_M_DOUBLE_VALUE_EN;
-};
-
-struct dcn10_stream_enc_registers {
- uint32_t AFMT_CNTL;
- uint32_t AFMT_AVI_INFO0;
- uint32_t AFMT_AVI_INFO1;
- uint32_t AFMT_AVI_INFO2;
- uint32_t AFMT_AVI_INFO3;
- uint32_t AFMT_GENERIC_0;
- uint32_t AFMT_GENERIC_1;
- uint32_t AFMT_GENERIC_2;
- uint32_t AFMT_GENERIC_3;
- uint32_t AFMT_GENERIC_4;
- uint32_t AFMT_GENERIC_5;
- uint32_t AFMT_GENERIC_6;
- uint32_t AFMT_GENERIC_7;
- uint32_t AFMT_GENERIC_HDR;
- uint32_t AFMT_INFOFRAME_CONTROL0;
- uint32_t AFMT_VBI_PACKET_CONTROL;
- uint32_t AFMT_VBI_PACKET_CONTROL1;
- uint32_t AFMT_AUDIO_PACKET_CONTROL;
- uint32_t AFMT_AUDIO_PACKET_CONTROL2;
- uint32_t AFMT_AUDIO_SRC_CONTROL;
- uint32_t AFMT_60958_0;
- uint32_t AFMT_60958_1;
- uint32_t AFMT_60958_2;
- uint32_t DIG_FE_CNTL;
- uint32_t DP_MSE_RATE_CNTL;
- uint32_t DP_MSE_RATE_UPDATE;
- uint32_t DP_PIXEL_FORMAT;
- uint32_t DP_SEC_CNTL;
- uint32_t DP_STEER_FIFO;
- uint32_t DP_VID_M;
- uint32_t DP_VID_N;
- uint32_t DP_VID_STREAM_CNTL;
- uint32_t DP_VID_TIMING;
- uint32_t DP_SEC_AUD_N;
- uint32_t DP_SEC_TIMESTAMP;
- uint32_t HDMI_CONTROL;
- uint32_t HDMI_GC;
- uint32_t HDMI_GENERIC_PACKET_CONTROL0;
- uint32_t HDMI_GENERIC_PACKET_CONTROL1;
- uint32_t HDMI_GENERIC_PACKET_CONTROL2;
- uint32_t HDMI_GENERIC_PACKET_CONTROL3;
- uint32_t HDMI_GENERIC_PACKET_CONTROL4;
- uint32_t HDMI_GENERIC_PACKET_CONTROL5;
- uint32_t HDMI_INFOFRAME_CONTROL0;
- uint32_t HDMI_INFOFRAME_CONTROL1;
- uint32_t HDMI_VBI_PACKET_CONTROL;
- uint32_t HDMI_AUDIO_PACKET_CONTROL;
- uint32_t HDMI_ACR_PACKET_CONTROL;
- uint32_t HDMI_ACR_32_0;
- uint32_t HDMI_ACR_32_1;
- uint32_t HDMI_ACR_44_0;
- uint32_t HDMI_ACR_44_1;
- uint32_t HDMI_ACR_48_0;
- uint32_t HDMI_ACR_48_1;
- uint32_t TMDS_CNTL;
- uint32_t DP_DB_CNTL;
- uint32_t DP_MSA_MISC;
- uint32_t DP_MSA_COLORIMETRY;
- uint32_t DP_MSA_TIMING_PARAM1;
- uint32_t DP_MSA_TIMING_PARAM2;
- uint32_t DP_MSA_TIMING_PARAM3;
- uint32_t DP_MSA_TIMING_PARAM4;
- uint32_t HDMI_DB_CONTROL;
+ SE_REG_FIELD_LIST_DCN1_0(uint32_t);
};
struct dcn10_stream_encoder {
@@ -581,4 +450,75 @@ void dcn10_stream_encoder_construct(
const struct dcn10_stream_encoder_shift *se_shift,
const struct dcn10_stream_encoder_mask *se_mask);
+void enc1_update_generic_info_packet(
+ struct dcn10_stream_encoder *enc1,
+ uint32_t packet_index,
+ const struct dc_info_packet *info_packet);
+
+void enc1_stream_encoder_dp_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ enum dc_color_space output_color_space);
+
+void enc1_stream_encoder_hdmi_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ int actual_pix_clk_khz,
+ bool enable_audio);
+
+void enc1_stream_encoder_dvi_set_stream_attribute(
+ struct stream_encoder *enc,
+ struct dc_crtc_timing *crtc_timing,
+ bool is_dual_link);
+
+void enc1_stream_encoder_set_mst_bandwidth(
+ struct stream_encoder *enc,
+ struct fixed31_32 avg_time_slots_per_mtp);
+
+void enc1_stream_encoder_update_dp_info_packets(
+ struct stream_encoder *enc,
+ const struct encoder_info_frame *info_frame);
+
+void enc1_stream_encoder_stop_dp_info_packets(
+ struct stream_encoder *enc);
+
+void enc1_stream_encoder_dp_blank(
+ struct stream_encoder *enc);
+
+void enc1_stream_encoder_dp_unblank(
+ struct stream_encoder *enc,
+ const struct encoder_unblank_param *param);
+
+void enc1_setup_stereo_sync(
+ struct stream_encoder *enc,
+ int tg_inst, bool enable);
+
+void enc1_stream_encoder_set_avmute(
+ struct stream_encoder *enc,
+ bool enable);
+
+void enc1_se_audio_mute_control(
+ struct stream_encoder *enc,
+ bool mute);
+
+void enc1_se_dp_audio_setup(
+ struct stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *info);
+
+void enc1_se_dp_audio_enable(
+ struct stream_encoder *enc);
+
+void enc1_se_dp_audio_disable(
+ struct stream_encoder *enc);
+
+void enc1_se_hdmi_audio_setup(
+ struct stream_encoder *enc,
+ unsigned int az_inst,
+ struct audio_info *info,
+ struct audio_crtc_info *audio_crtc_info);
+
+void enc1_se_hdmi_audio_disable(
+ struct stream_encoder *enc);
+
#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 015e209e58bc..93da44527d2e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -191,6 +191,23 @@ enum controller_dp_test_pattern {
CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
};
+enum dp_pixel_encoding_type {
+ DP_PIXEL_ENCODING_TYPE_RGB444 = 0x00000000,
+ DP_PIXEL_ENCODING_TYPE_YCBCR422 = 0x00000001,
+ DP_PIXEL_ENCODING_TYPE_YCBCR444 = 0x00000002,
+ DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT = 0x00000003,
+ DP_PIXEL_ENCODING_TYPE_Y_ONLY = 0x00000004,
+ DP_PIXEL_ENCODING_TYPE_YCBCR420 = 0x00000005
+};
+
+enum dp_component_depth {
+ DP_COMPONENT_PIXEL_DEPTH_6BPC = 0x00000000,
+ DP_COMPONENT_PIXEL_DEPTH_8BPC = 0x00000001,
+ DP_COMPONENT_PIXEL_DEPTH_10BPC = 0x00000002,
+ DP_COMPONENT_PIXEL_DEPTH_12BPC = 0x00000003,
+ DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004
+};
+
enum dc_lut_mode {
LUT_BYPASS,
LUT_RAM_A,
--
2.15.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 20/32] drm/amd/display: csc updates require FULL update
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (18 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 19/32] drm/amd/display: Make DCN stream encoder shareable Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 21/32] drm/amd/display: Fix FBC text console corruption Harry Wentland
` (11 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++++--
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 74f516903acd..5c7fa0412da1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1152,12 +1152,20 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
if (u->input_csc_color_matrix)
update_flags->bits.input_csc_change = 1;
- if (update_flags->bits.in_transfer_func_change
- || update_flags->bits.input_csc_change) {
+ if (u->coeff_reduction_factor)
+ update_flags->bits.coeff_reduction_change = 1;
+
+ if (update_flags->bits.in_transfer_func_change) {
type = UPDATE_TYPE_MED;
elevate_update_type(&overall_type, type);
}
+ if (update_flags->bits.input_csc_change
+ || update_flags->bits.coeff_reduction_change) {
+ type = UPDATE_TYPE_FULL;
+ elevate_update_type(&overall_type, type);
+ }
+
return overall_type;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 63817ed56c11..7d1a3c5d1b10 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -429,6 +429,7 @@ union surface_update_flags {
uint32_t position_change:1;
uint32_t in_transfer_func_change:1;
uint32_t input_csc_change:1;
+ uint32_t coeff_reduction_change:1;
uint32_t output_tf_change:1;
uint32_t pixel_format_change:1;
--
2.15.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 21/32] drm/amd/display: Fix FBC text console corruption
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (19 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 20/32] drm/amd/display: csc updates require FULL update Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 22/32] drm/amd/display: dal 3.1.41 Harry Wentland
` (10 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Roman Li
From: Roman Li <roman.li@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
.../drm/amd/display/dc/dce110/dce110_compressor.c | 67 +++++++++++++++++-----
1 file changed, 54 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 775d3bf0bd39..9150d2694450 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -102,6 +102,43 @@ static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
return 256 * ((pixels + 255) / 256);
}
+static void reset_lb_on_vblank(struct dc_context *ctx)
+{
+ uint32_t value, frame_count;
+ uint32_t retry = 0;
+ uint32_t status_pos =
+ dm_read_reg(ctx, mmCRTC_STATUS_POSITION);
+
+
+ /* Only if CRTC is enabled and counter is moving we wait for one frame. */
+ if (status_pos != dm_read_reg(ctx, mmCRTC_STATUS_POSITION)) {
+ /* Resetting LB on VBlank */
+ value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
+ set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
+ set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
+ dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
+
+ frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
+
+
+ for (retry = 100; retry > 0; retry--) {
+ if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT))
+ break;
+ msleep(1);
+ }
+ if (!retry)
+ dm_error("Frame count did not increase for 100ms.\n");
+
+ /* Resetting LB on VBlank */
+ value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
+ set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
+ set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
+ dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
+
+ }
+
+}
+
static void wait_for_fbc_state_changed(
struct dce110_compressor *cp110,
bool enabled)
@@ -232,19 +269,23 @@ void dce110_compressor_disable_fbc(struct compressor *compressor)
{
struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
- if (compressor->options.bits.FBC_SUPPORT &&
- dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
- uint32_t reg_data;
- /* Turn off compression */
- reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
- set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
- dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
-
- /* Reset enum controller_id to undefined */
- compressor->attached_inst = 0;
- compressor->is_enabled = false;
-
- wait_for_fbc_state_changed(cp110, false);
+ if (compressor->options.bits.FBC_SUPPORT) {
+ if (dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
+ uint32_t reg_data;
+ /* Turn off compression */
+ reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
+ set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
+ dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
+
+ /* Reset enum controller_id to undefined */
+ compressor->attached_inst = 0;
+ compressor->is_enabled = false;
+
+ wait_for_fbc_state_changed(cp110, false);
+ }
+
+ /* Sync line buffer - dce100/110 only*/
+ reset_lb_on_vblank(compressor->ctx);
}
}
--
2.15.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 22/32] drm/amd/display: dal 3.1.41
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (20 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 21/32] drm/amd/display: Fix FBC text console corruption Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 23/32] drm/amd/display: Updated HDR Static Metadata to directly take info packet raw Harry Wentland
` (9 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yongqiang Sun
From: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7d1a3c5d1b10..23349148c7a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
#include "inc/compressor.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.1.40"
+#define DC_VER "3.1.41"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
--
2.15.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 23/32] drm/amd/display: Updated HDR Static Metadata to directly take info packet raw
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (21 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 22/32] drm/amd/display: dal 3.1.41 Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 24/32] drm/amd/display: Get rid of unused input_tf Harry Wentland
` (8 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Updated HDR Static Metadata to directly take info packet raw
Updating Infopacket does not require Passive
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 -
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 91 +----------------------
drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 +-
3 files changed, 5 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5c7fa0412da1..292667197a30 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1195,9 +1195,6 @@ static enum surface_update_type check_update_surfaces_for_stream(
if (stream_update->out_transfer_func)
return UPDATE_TYPE_FULL;
- if (stream_update->hdr_static_metadata)
- return UPDATE_TYPE_FULL;
-
if (stream_update->abm_level)
return UPDATE_TYPE_FULL;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index b57c5404d9bc..569c3ac2af07 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2209,97 +2209,12 @@ static void set_hdr_static_info_packet(
struct dc_info_packet *info_packet,
struct dc_stream_state *stream)
{
- uint16_t i = 0;
- enum signal_type signal = stream->signal;
- uint32_t data;
+ /* HDR Static Metadata info packet for HDR10 */
- if (!stream->hdr_static_metadata.hdr_supported)
+ if (!stream->hdr_static_metadata.valid)
return;
- if (dc_is_hdmi_signal(signal)) {
- info_packet->valid = true;
-
- info_packet->hb0 = 0x87;
- info_packet->hb1 = 0x01;
- info_packet->hb2 = 0x1A;
- i = 1;
- } else if (dc_is_dp_signal(signal)) {
- info_packet->valid = true;
-
- info_packet->hb0 = 0x00;
- info_packet->hb1 = 0x87;
- info_packet->hb2 = 0x1D;
- info_packet->hb3 = (0x13 << 2);
- i = 2;
- }
-
- data = stream->hdr_static_metadata.is_hdr;
- info_packet->sb[i++] = data ? 0x02 : 0x00;
- info_packet->sb[i++] = 0x00;
-
- data = stream->hdr_static_metadata.chromaticity_green_x / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_green_y / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_red_x / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_red_y / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.max_luminance;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.min_luminance;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.maximum_content_light_level;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- data = stream->hdr_static_metadata.maximum_frame_average_light_level;
- info_packet->sb[i++] = data & 0xFF;
- info_packet->sb[i++] = (data & 0xFF00) >> 8;
-
- if (dc_is_hdmi_signal(signal)) {
- uint32_t checksum = 0;
-
- checksum += info_packet->hb0;
- checksum += info_packet->hb1;
- checksum += info_packet->hb2;
-
- for (i = 1; i <= info_packet->hb2; i++)
- checksum += info_packet->sb[i];
-
- info_packet->sb[0] = 0x100 - checksum;
- } else if (dc_is_dp_signal(signal)) {
- info_packet->sb[0] = 0x01;
- info_packet->sb[1] = 0x1A;
- }
+ *info_packet = stream->hdr_static_metadata;
}
static void set_vsc_info_packet(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index ca437e1412f6..f90c5785a502 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -64,7 +64,7 @@ struct dc_stream_state {
struct audio_info audio_info;
- struct dc_hdr_static_metadata hdr_static_metadata;
+ struct dc_info_packet hdr_static_metadata;
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
struct csc_transform csc_color_matrix;
@@ -119,8 +119,8 @@ struct dc_stream_update {
struct rect src;
struct rect dst;
struct dc_transfer_func *out_transfer_func;
- struct dc_hdr_static_metadata *hdr_static_metadata;
enum color_transfer_func color_output_tf;
+ struct dc_info_packet *hdr_static_metadata;
unsigned int *abm_level;
unsigned long long *periodic_fn_vsync_delta;
struct dc_crtc_timing_adjust *adjust;
--
2.15.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 24/32] drm/amd/display: Get rid of unused input_tf
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (22 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 23/32] drm/amd/display: Updated HDR Static Metadata to directly take info packet raw Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 25/32] drm/amd/display: Remove unused fields Harry Wentland
` (7 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc.c | 3 ---
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 ----
drivers/gpu/drm/amd/display/dc/dc.h | 5 -----
4 files changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 55a8aaf68a1f..9af4c07c2ce3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4104,7 +4104,6 @@ static bool commit_planes_to_stream(
flip_addr[i].address = plane_states[i]->address;
flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
plane_info[i].color_space = plane_states[i]->color_space;
- plane_info[i].input_tf = plane_states[i]->input_tf;
plane_info[i].format = plane_states[i]->format;
plane_info[i].plane_size = plane_states[i]->plane_size;
plane_info[i].rotation = plane_states[i]->rotation;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 292667197a30..33149ed779eb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1016,9 +1016,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
if (u->plane_info->color_space != u->surface->color_space)
update_flags->bits.color_space_change = 1;
- if (u->plane_info->input_tf != u->surface->input_tf)
- update_flags->bits.input_tf_change = 1;
-
if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
update_flags->bits.horizontal_mirror_change = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index a3c87611220d..267c76766dea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -155,7 +155,6 @@ void pre_surface_trace(
"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
"plane_state->tiling_info.gfx8.array_mode = %d;\n"
"plane_state->color_space = %d;\n"
- "plane_state->input_tf = %d;\n"
"plane_state->dcc.enable = %d;\n"
"plane_state->format = %d;\n"
"plane_state->rotation = %d;\n"
@@ -163,7 +162,6 @@ void pre_surface_trace(
plane_state->tiling_info.gfx8.pipe_config,
plane_state->tiling_info.gfx8.array_mode,
plane_state->color_space,
- plane_state->input_tf,
plane_state->dcc.enable,
plane_state->format,
plane_state->rotation,
@@ -203,7 +201,6 @@ void update_surface_trace(
if (update->plane_info) {
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
- "plane_info->input_tf = %d;\n"
"plane_info->format = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
@@ -213,7 +210,6 @@ void update_surface_trace(
"plane_info->rotation = %d;\n"
"plane_info->stereo_format = %d;\n",
update->plane_info->color_space,
- update->plane_info->input_tf,
update->plane_info->format,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 23349148c7a4..6a47da30b281 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -333,7 +333,6 @@ enum {
TRANSFER_FUNC_POINTS = 1025
};
-// Moved here from color module for linux
enum color_transfer_func {
transfer_func_unknown,
transfer_func_srgb,
@@ -420,7 +419,6 @@ union surface_update_flags {
/* Medium updates */
uint32_t dcc_change:1;
uint32_t color_space_change:1;
- uint32_t input_tf_change:1;
uint32_t horizontal_mirror_change:1;
uint32_t per_pixel_alpha_change:1;
uint32_t rotation_change:1;
@@ -470,7 +468,6 @@ struct dc_plane_state {
struct dc_hdr_static_metadata hdr_static_ctx;
enum dc_color_space color_space;
- enum color_transfer_func input_tf;
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
@@ -500,7 +497,6 @@ struct dc_plane_info {
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
enum dc_color_space color_space;
- enum color_transfer_func input_tf;
unsigned int sdr_white_level;
bool horizontal_mirror;
bool visible;
@@ -527,7 +523,6 @@ struct dc_surface_update {
* null means no updates
*/
struct dc_gamma *gamma;
- enum color_transfer_func color_input_tf;
struct dc_transfer_func *in_transfer_func;
struct csc_transform *input_csc_color_matrix;
--
2.15.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 25/32] drm/amd/display: Remove unused fields
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (23 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 24/32] drm/amd/display: Get rid of unused input_tf Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 26/32] drm/amd/display: Do not use os types Harry Wentland
` (6 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 6a47da30b281..5b81ae5acdf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -361,9 +361,6 @@ struct dc_hdr_static_metadata {
uint32_t max_luminance;
uint32_t maximum_content_light_level;
uint32_t maximum_frame_average_light_level;
-
- bool hdr_supported;
- bool is_hdr;
};
enum dc_transfer_func_type {
--
2.15.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 26/32] drm/amd/display: Do not use os types
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (24 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 25/32] drm/amd/display: Remove unused fields Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 27/32] drm/amd/display: csc_transform to dc_csc_transform Harry Wentland
` (5 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 158 ++++++++++-----------
drivers/gpu/drm/amd/display/include/fixed31_32.h | 40 +++---
2 files changed, 98 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 8a9bba879207..7191c3213743 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -26,13 +26,13 @@
#include "dm_services.h"
#include "include/fixed31_32.h"
-static inline uint64_t abs_i64(
- int64_t arg)
+static inline unsigned long long abs_i64(
+ long long arg)
{
if (arg > 0)
- return (uint64_t)arg;
+ return (unsigned long long)arg;
else
- return (uint64_t)(-arg);
+ return (unsigned long long)(-arg);
}
/*
@@ -40,12 +40,12 @@ static inline uint64_t abs_i64(
* result = dividend / divisor
* *remainder = dividend % divisor
*/
-static inline uint64_t complete_integer_division_u64(
- uint64_t dividend,
- uint64_t divisor,
- uint64_t *remainder)
+static inline unsigned long long complete_integer_division_u64(
+ unsigned long long dividend,
+ unsigned long long divisor,
+ unsigned long long *remainder)
{
- uint64_t result;
+ unsigned long long result;
ASSERT(divisor);
@@ -65,29 +65,29 @@ static inline uint64_t complete_integer_division_u64(
(FRACTIONAL_PART_MASK & (x))
struct fixed31_32 dal_fixed31_32_from_fraction(
- int64_t numerator,
- int64_t denominator)
+ long long numerator,
+ long long denominator)
{
struct fixed31_32 res;
bool arg1_negative = numerator < 0;
bool arg2_negative = denominator < 0;
- uint64_t arg1_value = arg1_negative ? -numerator : numerator;
- uint64_t arg2_value = arg2_negative ? -denominator : denominator;
+ unsigned long long arg1_value = arg1_negative ? -numerator : numerator;
+ unsigned long long arg2_value = arg2_negative ? -denominator : denominator;
- uint64_t remainder;
+ unsigned long long remainder;
/* determine integer part */
- uint64_t res_value = complete_integer_division_u64(
+ unsigned long long res_value = complete_integer_division_u64(
arg1_value, arg2_value, &remainder);
ASSERT(res_value <= LONG_MAX);
/* determine fractional part */
{
- uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
+ unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
do {
remainder <<= 1;
@@ -103,14 +103,14 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
/* round up LSB */
{
- uint64_t summand = (remainder << 1) >= arg2_value;
+ unsigned long long summand = (remainder << 1) >= arg2_value;
ASSERT(res_value <= LLONG_MAX - summand);
res_value += summand;
}
- res.value = (int64_t)res_value;
+ res.value = (long long)res_value;
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
@@ -119,7 +119,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
}
struct fixed31_32 dal_fixed31_32_from_int_nonconst(
- int64_t arg)
+ long long arg)
{
struct fixed31_32 res;
@@ -132,7 +132,7 @@ struct fixed31_32 dal_fixed31_32_from_int_nonconst(
struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
- uint8_t shift)
+ unsigned char shift)
{
struct fixed31_32 res;
@@ -181,16 +181,16 @@ struct fixed31_32 dal_fixed31_32_mul(
bool arg1_negative = arg1.value < 0;
bool arg2_negative = arg2.value < 0;
- uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
- uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
+ unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value;
+ unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value;
- uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
- uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
+ unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
+ unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
- uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
- uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
+ unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
+ unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
- uint64_t tmp;
+ unsigned long long tmp;
res.value = arg1_int * arg2_int;
@@ -200,22 +200,22 @@ struct fixed31_32 dal_fixed31_32_mul(
tmp = arg1_int * arg2_fra;
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg2_int * arg1_fra;
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg1_fra * arg2_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
- (tmp >= (uint64_t)dal_fixed31_32_half.value);
+ (tmp >= (unsigned long long)dal_fixed31_32_half.value);
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
@@ -230,13 +230,13 @@ struct fixed31_32 dal_fixed31_32_sqr(
{
struct fixed31_32 res;
- uint64_t arg_value = abs_i64(arg.value);
+ unsigned long long arg_value = abs_i64(arg.value);
- uint64_t arg_int = GET_INTEGER_PART(arg_value);
+ unsigned long long arg_int = GET_INTEGER_PART(arg_value);
- uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
+ unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value);
- uint64_t tmp;
+ unsigned long long tmp;
res.value = arg_int * arg_int;
@@ -246,20 +246,20 @@ struct fixed31_32 dal_fixed31_32_sqr(
tmp = arg_int * arg_fra;
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg_fra * arg_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
- (tmp >= (uint64_t)dal_fixed31_32_half.value);
+ (tmp >= (unsigned long long)dal_fixed31_32_half.value);
- ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
+ ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
@@ -288,7 +288,7 @@ struct fixed31_32 dal_fixed31_32_sinc(
struct fixed31_32 res = dal_fixed31_32_one;
- int32_t n = 27;
+ int n = 27;
struct fixed31_32 arg_norm = arg;
@@ -299,7 +299,7 @@ struct fixed31_32 dal_fixed31_32_sinc(
arg_norm,
dal_fixed31_32_mul_int(
dal_fixed31_32_two_pi,
- (int32_t)div64_s64(
+ (int)div64_s64(
arg_norm.value,
dal_fixed31_32_two_pi.value)));
}
@@ -343,7 +343,7 @@ struct fixed31_32 dal_fixed31_32_cos(
struct fixed31_32 res = dal_fixed31_32_one;
- int32_t n = 26;
+ int n = 26;
do {
res = dal_fixed31_32_sub(
@@ -370,7 +370,7 @@ struct fixed31_32 dal_fixed31_32_cos(
static struct fixed31_32 fixed31_32_exp_from_taylor_series(
struct fixed31_32 arg)
{
- uint32_t n = 9;
+ unsigned int n = 9;
struct fixed31_32 res = dal_fixed31_32_from_fraction(
n + 2,
@@ -409,7 +409,7 @@ struct fixed31_32 dal_fixed31_32_exp(
if (dal_fixed31_32_le(
dal_fixed31_32_ln2_div_2,
dal_fixed31_32_abs(arg))) {
- int32_t m = dal_fixed31_32_round(
+ int m = dal_fixed31_32_round(
dal_fixed31_32_div(
arg,
dal_fixed31_32_ln2));
@@ -429,7 +429,7 @@ struct fixed31_32 dal_fixed31_32_exp(
if (m > 0)
return dal_fixed31_32_shl(
fixed31_32_exp_from_taylor_series(r),
- (uint8_t)m);
+ (unsigned char)m);
else
return dal_fixed31_32_div_int(
fixed31_32_exp_from_taylor_series(r),
@@ -482,50 +482,50 @@ struct fixed31_32 dal_fixed31_32_pow(
arg2));
}
-int32_t dal_fixed31_32_floor(
+int dal_fixed31_32_floor(
struct fixed31_32 arg)
{
- uint64_t arg_value = abs_i64(arg.value);
+ unsigned long long arg_value = abs_i64(arg.value);
if (arg.value >= 0)
- return (int32_t)GET_INTEGER_PART(arg_value);
+ return (int)GET_INTEGER_PART(arg_value);
else
- return -(int32_t)GET_INTEGER_PART(arg_value);
+ return -(int)GET_INTEGER_PART(arg_value);
}
-int32_t dal_fixed31_32_round(
+int dal_fixed31_32_round(
struct fixed31_32 arg)
{
- uint64_t arg_value = abs_i64(arg.value);
+ unsigned long long arg_value = abs_i64(arg.value);
- const int64_t summand = dal_fixed31_32_half.value;
+ const long long summand = dal_fixed31_32_half.value;
- ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
+ ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
- return (int32_t)GET_INTEGER_PART(arg_value);
+ return (int)GET_INTEGER_PART(arg_value);
else
- return -(int32_t)GET_INTEGER_PART(arg_value);
+ return -(int)GET_INTEGER_PART(arg_value);
}
-int32_t dal_fixed31_32_ceil(
+int dal_fixed31_32_ceil(
struct fixed31_32 arg)
{
- uint64_t arg_value = abs_i64(arg.value);
+ unsigned long long arg_value = abs_i64(arg.value);
- const int64_t summand = dal_fixed31_32_one.value -
+ const long long summand = dal_fixed31_32_one.value -
dal_fixed31_32_epsilon.value;
- ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
+ ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
- return (int32_t)GET_INTEGER_PART(arg_value);
+ return (int)GET_INTEGER_PART(arg_value);
else
- return -(int32_t)GET_INTEGER_PART(arg_value);
+ return -(int)GET_INTEGER_PART(arg_value);
}
/* this function is a generic helper to translate fixed point value to
@@ -535,15 +535,15 @@ int32_t dal_fixed31_32_ceil(
* part in 32 bits. It is used in hw programming (scaler)
*/
-static inline uint32_t ux_dy(
- int64_t value,
- uint32_t integer_bits,
- uint32_t fractional_bits)
+static inline unsigned int ux_dy(
+ long long value,
+ unsigned int integer_bits,
+ unsigned int fractional_bits)
{
/* 1. create mask of integer part */
- uint32_t result = (1 << integer_bits) - 1;
+ unsigned int result = (1 << integer_bits) - 1;
/* 2. mask out fractional part */
- uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
+ unsigned int fractional_part = FRACTIONAL_PART_MASK & value;
/* 3. shrink fixed point integer part to be of integer_bits width*/
result &= GET_INTEGER_PART(value);
/* 4. make space for fractional part to be filled in after integer */
@@ -554,13 +554,13 @@ static inline uint32_t ux_dy(
return result | fractional_part;
}
-static inline uint32_t clamp_ux_dy(
- int64_t value,
- uint32_t integer_bits,
- uint32_t fractional_bits,
- uint32_t min_clamp)
+static inline unsigned int clamp_ux_dy(
+ long long value,
+ unsigned int integer_bits,
+ unsigned int fractional_bits,
+ unsigned int min_clamp)
{
- uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);
+ unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits);
if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))
return (1 << (integer_bits + fractional_bits)) - 1;
@@ -570,35 +570,35 @@ static inline uint32_t clamp_ux_dy(
return min_clamp;
}
-uint32_t dal_fixed31_32_u2d19(
+unsigned int dal_fixed31_32_u2d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 2, 19);
}
-uint32_t dal_fixed31_32_u0d19(
+unsigned int dal_fixed31_32_u0d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 0, 19);
}
-uint32_t dal_fixed31_32_clamp_u0d14(
+unsigned int dal_fixed31_32_clamp_u0d14(
struct fixed31_32 arg)
{
return clamp_ux_dy(arg.value, 0, 14, 1);
}
-uint32_t dal_fixed31_32_clamp_u0d10(
+unsigned int dal_fixed31_32_clamp_u0d10(
struct fixed31_32 arg)
{
return clamp_ux_dy(arg.value, 0, 10, 1);
}
-int32_t dal_fixed31_32_s4d19(
+int dal_fixed31_32_s4d19(
struct fixed31_32 arg)
{
if (arg.value < 0)
- return -(int32_t)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
+ return -(int)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
else
return ux_dy(arg.value, 4, 19);
}
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 0de258622c12..16cbdb43d856 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -26,8 +26,6 @@
#ifndef __DAL_FIXED31_32_H__
#define __DAL_FIXED31_32_H__
-#include "os_types.h"
-
#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
/*
@@ -44,7 +42,7 @@
*/
struct fixed31_32 {
- int64_t value;
+ long long value;
};
/*
@@ -73,15 +71,15 @@ static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
* result = numerator / denominator
*/
struct fixed31_32 dal_fixed31_32_from_fraction(
- int64_t numerator,
- int64_t denominator);
+ long long numerator,
+ long long denominator);
/*
* @brief
* result = arg
*/
-struct fixed31_32 dal_fixed31_32_from_int_nonconst(int64_t arg);
-static inline struct fixed31_32 dal_fixed31_32_from_int(int64_t arg)
+struct fixed31_32 dal_fixed31_32_from_int_nonconst(long long arg);
+static inline struct fixed31_32 dal_fixed31_32_from_int(long long arg)
{
if (__builtin_constant_p(arg)) {
struct fixed31_32 res;
@@ -213,7 +211,7 @@ static inline struct fixed31_32 dal_fixed31_32_clamp(
*/
struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
- uint8_t shift);
+ unsigned char shift);
/*
* @brief
@@ -221,7 +219,7 @@ struct fixed31_32 dal_fixed31_32_shl(
*/
static inline struct fixed31_32 dal_fixed31_32_shr(
struct fixed31_32 arg,
- uint8_t shift)
+ unsigned char shift)
{
struct fixed31_32 res;
res.value = arg.value >> shift;
@@ -246,7 +244,7 @@ struct fixed31_32 dal_fixed31_32_add(
* result = arg1 + arg2
*/
static inline struct fixed31_32 dal_fixed31_32_add_int(struct fixed31_32 arg1,
- int32_t arg2)
+ int arg2)
{
return dal_fixed31_32_add(arg1,
dal_fixed31_32_from_int(arg2));
@@ -265,7 +263,7 @@ struct fixed31_32 dal_fixed31_32_sub(
* result = arg1 - arg2
*/
static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
- int32_t arg2)
+ int arg2)
{
return dal_fixed31_32_sub(arg1,
dal_fixed31_32_from_int(arg2));
@@ -291,7 +289,7 @@ struct fixed31_32 dal_fixed31_32_mul(
* result = arg1 * arg2
*/
static inline struct fixed31_32 dal_fixed31_32_mul_int(struct fixed31_32 arg1,
- int32_t arg2)
+ int arg2)
{
return dal_fixed31_32_mul(arg1,
dal_fixed31_32_from_int(arg2));
@@ -309,7 +307,7 @@ struct fixed31_32 dal_fixed31_32_sqr(
* result = arg1 / arg2
*/
static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
- int64_t arg2)
+ long long arg2)
{
return dal_fixed31_32_from_fraction(arg1.value,
dal_fixed31_32_from_int(arg2).value);
@@ -434,21 +432,21 @@ struct fixed31_32 dal_fixed31_32_pow(
* @brief
* result = floor(arg) := greatest integer lower than or equal to arg
*/
-int32_t dal_fixed31_32_floor(
+int dal_fixed31_32_floor(
struct fixed31_32 arg);
/*
* @brief
* result = round(arg) := integer nearest to arg
*/
-int32_t dal_fixed31_32_round(
+int dal_fixed31_32_round(
struct fixed31_32 arg);
/*
* @brief
* result = ceil(arg) := lowest integer greater than or equal to arg
*/
-int32_t dal_fixed31_32_ceil(
+int dal_fixed31_32_ceil(
struct fixed31_32 arg);
/* the following two function are used in scaler hw programming to convert fixed
@@ -457,20 +455,20 @@ int32_t dal_fixed31_32_ceil(
* fractional
*/
-uint32_t dal_fixed31_32_u2d19(
+unsigned int dal_fixed31_32_u2d19(
struct fixed31_32 arg);
-uint32_t dal_fixed31_32_u0d19(
+unsigned int dal_fixed31_32_u0d19(
struct fixed31_32 arg);
-uint32_t dal_fixed31_32_clamp_u0d14(
+unsigned int dal_fixed31_32_clamp_u0d14(
struct fixed31_32 arg);
-uint32_t dal_fixed31_32_clamp_u0d10(
+unsigned int dal_fixed31_32_clamp_u0d10(
struct fixed31_32 arg);
-int32_t dal_fixed31_32_s4d19(
+int dal_fixed31_32_s4d19(
struct fixed31_32 arg);
#endif
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 27/32] drm/amd/display: csc_transform to dc_csc_transform
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (25 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 26/32] drm/amd/display: Do not use os types Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 28/32] drm/amd/display: Refactor color module Harry Wentland
` (4 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 4 ++--
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 5 +++++
drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 5 -----
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 2 +-
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +-
9 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5b81ae5acdf4..588672cbfbf2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -457,7 +457,7 @@ struct dc_plane_state {
struct dc_gamma *gamma_correction;
struct dc_transfer_func *in_transfer_func;
struct dc_bias_and_scale *bias_and_scale;
- struct csc_transform input_csc_color_matrix;
+ struct dc_csc_transform input_csc_color_matrix;
struct fixed31_32 coeff_reduction_factor;
uint32_t sdr_white_level;
@@ -522,7 +522,7 @@ struct dc_surface_update {
struct dc_gamma *gamma;
struct dc_transfer_func *in_transfer_func;
- struct csc_transform *input_csc_color_matrix;
+ struct dc_csc_transform *input_csc_color_matrix;
struct fixed31_32 *coeff_reduction_factor;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 5472316822ce..4a05df3850ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -423,6 +423,11 @@ enum dc_gamma_type {
GAMMA_CS_TFM_1D = 3,
};
+struct dc_csc_transform {
+ uint16_t matrix[12];
+ bool enable_adjustment;
+};
+
struct dc_gamma {
struct kref refcount;
enum dc_gamma_type type;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index f90c5785a502..aa73ce639e5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -67,7 +67,7 @@ struct dc_stream_state {
struct dc_info_packet hdr_static_metadata;
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
- struct csc_transform csc_color_matrix;
+ struct dc_csc_transform csc_color_matrix;
enum dc_color_space output_color_space;
enum dc_dither_option dither_option;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 5f40a7374c02..c008a71ebc4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -264,7 +264,7 @@ void dpp1_cnv_setup (
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
- struct csc_transform input_csc_color_matrix,
+ struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space)
{
uint32_t pixel_format;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 9b5ff76a8027..3fccf9959305 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1451,7 +1451,7 @@ void dpp1_cnv_setup (
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
- struct csc_transform input_csc_color_matrix,
+ struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void dpp1_full_bypass(struct dpp *dpp_base);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index 99995608b620..bb7af1b1c7b3 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -117,7 +117,7 @@ struct dpp_funcs {
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
- struct csc_transform input_csc_color_matrix,
+ struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void (*dpp_full_bypass)(struct dpp *dpp_base);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 93da44527d2e..9fe73028d588 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -140,11 +140,6 @@ enum opp_regamma {
OPP_REGAMMA_USER
};
-struct csc_transform {
- uint16_t matrix[12];
- bool enable_adjustment;
-};
-
struct dc_bias_and_scale {
uint16_t scale_red;
uint16_t bias_red;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
index 2109eac20a3d..b2fa4c4cd920 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
@@ -87,7 +87,7 @@ struct ipp_funcs {
struct input_pixel_processor *ipp,
enum surface_pixel_format format,
enum expansion_mode mode,
- struct csc_transform input_csc_color_matrix,
+ struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
/* DCE function to setup IPP. TODO: see if we can consolidate to setup */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
index c5b3623bcbd9..fecc80c47c26 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
@@ -252,7 +252,7 @@ struct transform_funcs {
struct transform *xfm_base,
enum surface_pixel_format format,
enum expansion_mode mode,
- struct csc_transform input_csc_color_matrix,
+ struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void (*ipp_full_bypass)(struct transform *xfm_base);
--
2.15.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 28/32] drm/amd/display: Refactor color module
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (26 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 27/32] drm/amd/display: csc_transform to dc_csc_transform Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 29/32] drm/amd/display: move color_transfer_func to color mod Harry Wentland
` (3 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Remove some unnecessary TF definitions from update structures
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index aa73ce639e5c..aefc76b0a171 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -73,7 +73,6 @@ struct dc_stream_state {
enum dc_dither_option dither_option;
enum view_3d_format view_format;
- enum color_transfer_func output_tf;
bool ignore_msa_timing_param;
@@ -119,10 +118,11 @@ struct dc_stream_update {
struct rect src;
struct rect dst;
struct dc_transfer_func *out_transfer_func;
- enum color_transfer_func color_output_tf;
struct dc_info_packet *hdr_static_metadata;
unsigned int *abm_level;
+
unsigned long long *periodic_fn_vsync_delta;
+
struct dc_crtc_timing_adjust *adjust;
struct dc_info_packet *vrr_infopacket;
};
--
2.15.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 29/32] drm/amd/display: move color_transfer_func to color mod
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (27 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 28/32] drm/amd/display: Refactor color module Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 30/32] drm/amd/display: Fix structure initialization of hdmi_info_packet Harry Wentland
` (2 subsequent siblings)
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 588672cbfbf2..0f566a1ba35b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -333,19 +333,6 @@ enum {
TRANSFER_FUNC_POINTS = 1025
};
-enum color_transfer_func {
- transfer_func_unknown,
- transfer_func_srgb,
- transfer_func_bt709,
- transfer_func_pq2084,
- transfer_func_pq2084_interim,
- transfer_func_linear_0_1,
- transfer_func_linear_0_125,
- transfer_func_dolbyvision,
- transfer_func_gamma_22,
- transfer_func_gamma_26
-};
-
struct dc_hdr_static_metadata {
/* display chromaticities and white point in units of 0.00001 */
unsigned int chromaticity_green_x;
@@ -693,6 +680,7 @@ struct dc_cursor {
struct dc_cursor_attributes attributes;
};
+
/*******************************************************************************
* Interrupt interfaces
******************************************************************************/
--
2.15.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 30/32] drm/amd/display: Fix structure initialization of hdmi_info_packet
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (28 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 29/32] drm/amd/display: move color_transfer_func to color mod Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 31/32] drm/amd/display: Have DC manage its own allocation of gamma Harry Wentland
2018-04-04 1:27 ` [PATCH 32/32] drm/amd/display: Fix dim display on DCE11 Harry Wentland
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 569c3ac2af07..667fac8749b9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1853,11 +1853,13 @@ static void set_avi_info_frame(
unsigned int cn0_cn1_value = 0;
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
- union hdmi_info_packet hdmi_info = {0};
+ union hdmi_info_packet hdmi_info;
union display_content_support support = {0};
unsigned int vic = pipe_ctx->stream->timing.vic;
enum dc_timing_3d_format format;
+ memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
+
color_space = pipe_ctx->stream->output_color_space;
if (color_space == COLOR_SPACE_UNKNOWN)
color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 31/32] drm/amd/display: Have DC manage its own allocation of gamma
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (29 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 30/32] drm/amd/display: Fix structure initialization of hdmi_info_packet Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
2018-04-04 1:27 ` [PATCH 32/32] drm/amd/display: Fix dim display on DCE11 Harry Wentland
31 siblings, 0 replies; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Anthony Koo
From: Anthony Koo <Anthony.Koo@amd.com>
Creating plane will also allocate gamma and input TF
Creating stream will also allocate outputTF
Fix issue with gamma not applied
OS may call SetGamma before surface committed, so need to store
in target and apply later.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++----
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 ++++--
drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 8 +++++++-
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 ++---
4 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9af4c07c2ce3..a3ca21be978d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2242,7 +2242,6 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
const struct drm_connector *connector)
{
struct dc_crtc_timing *timing_out = &stream->timing;
- struct dc_transfer_func *tf = dc_create_transfer_func();
memset(timing_out, 0, sizeof(struct dc_crtc_timing));
@@ -2286,9 +2285,8 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
stream->output_color_space = get_output_color_space(timing_out);
- tf->type = TF_TYPE_PREDEFINED;
- tf->tf = TRANSFER_FUNCTION_SRGB;
- stream->out_transfer_func = tf;
+ stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
+ stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
}
static void fill_audio_info(struct audio_info *audio_info,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ce0747ed0f00..3b2ddbd8c054 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -101,14 +101,16 @@ static void construct(struct dc_stream_state *stream,
stream->status.link = stream->sink->link;
update_stream_signal(stream);
+
+ stream->out_transfer_func = dc_create_transfer_func();
+ stream->out_transfer_func->type = TF_TYPE_BYPASS;
}
static void destruct(struct dc_stream_state *stream)
{
dc_sink_release(stream->sink);
if (stream->out_transfer_func != NULL) {
- dc_transfer_func_release(
- stream->out_transfer_func);
+ dc_transfer_func_release(stream->out_transfer_func);
stream->out_transfer_func = NULL;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index ade5b8ee9c3c..959387705965 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -38,6 +38,12 @@
static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
{
plane_state->ctx = ctx;
+
+ plane_state->gamma_correction = dc_create_gamma();
+ plane_state->gamma_correction->is_identity = true;
+
+ plane_state->in_transfer_func = dc_create_transfer_func();
+ plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
}
static void destruct(struct dc_plane_state *plane_state)
@@ -175,7 +181,7 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
kref_put(&tf->refcount, dc_transfer_func_free);
}
-struct dc_transfer_func *dc_create_transfer_func(void)
+struct dc_transfer_func *dc_create_transfer_func()
{
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index dfa6ad5078b2..1f59b27e611a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -971,9 +971,8 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
tf = plane_state->in_transfer_func;
if (plane_state->gamma_correction &&
- plane_state->gamma_correction->is_identity)
- dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
- else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
+ !plane_state->gamma_correction->is_identity
+ && dce_use_lut(plane_state->format))
dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
if (tf == NULL)
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 32/32] drm/amd/display: Fix dim display on DCE11
[not found] ` <20180404012747.5651-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
` (30 preceding siblings ...)
2018-04-04 1:27 ` [PATCH 31/32] drm/amd/display: Have DC manage its own allocation of gamma Harry Wentland
@ 2018-04-04 1:27 ` Harry Wentland
[not found] ` <20180404012747.5651-33-harry.wentland-5C7GfCeVMHo@public.gmane.org>
31 siblings, 1 reply; 36+ messages in thread
From: Harry Wentland @ 2018-04-04 1:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Leo (Sunpeng) Li
From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
Before programming the input gamma, check that we're not using the
identity correction.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 99d192200797..f385b18d5c2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -280,7 +280,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
build_prescale_params(&prescale_params, plane_state);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
- if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
+ if (plane_state->gamma_correction &&
+ !plane_state->gamma_correction->is_identity &&
+ dce_use_lut(plane_state->format))
ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
if (tf == NULL) {
--
2.15.1
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^ permalink raw reply related [flat|nested] 36+ messages in thread