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From: "Zhang, Jerry (Junwei)" <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
To: Alex Deucher
	<alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs
Date: Mon, 21 May 2018 09:29:56 +0800	[thread overview]
Message-ID: <5B022114.8050706@amd.com> (raw)
In-Reply-To: <20180516205156.29064-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>

On 05/17/2018 04:51 AM, Alex Deucher wrote:
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Series is
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>   #define mmDF_CS_AON0_DramBaseAddress0									0x0044
>   #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX								0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0								0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX							0
> +
> +
>   #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>   #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
>   #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L
> +
>   #endif
>
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      parent reply	other threads:[~2018-05-21  1:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-16 20:51 [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs Alex Deucher
     [not found] ` <20180516205156.29064-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-05-16 20:51   ` [PATCH 2/4] drm/amdgpu: add new DF callback for ECC setup Alex Deucher
2018-05-16 20:51   ` [PATCH 3/4] drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmw Alex Deucher
2018-05-16 20:51   ` [PATCH 4/4] drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabled Alex Deucher
2018-05-18 19:48   ` [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs Alex Deucher
     [not found]     ` <CADnq5_P=ZLmnesB63GQ8Fq=GWN7yva-8j5VN99hjfN=Fi=Xkdw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-05-20 15:23       ` Zhang, Hawking
2018-05-21  1:16   ` Zhang, Jerry (Junwei)
2018-05-21  1:29   ` Zhang, Jerry (Junwei) [this message]

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