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From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: christian.koenig@amd.com, amd-gfx@lists.freedesktop.org,
	Darren Salt <devspam@moreofthesa.me.uk>
Subject: Re: [PATCH] amdgpu: resize BAR0 to the maximum available size, even if it doesn't cover VRAM
Date: Fri, 11 Dec 2020 17:46:55 +0100	[thread overview]
Message-ID: <77805324-8fdc-8d72-f033-7d75ae04947e@gmail.com> (raw)
In-Reply-To: <58E26045D8%devspam@moreofthesa.me.uk>

Am 11.12.20 um 02:42 schrieb Darren Salt:
> I demand that Christian König may or may not have written...

[SNIP]

Well I did wrote that :)

> I used dd: # dd if=/sys/kernel/debug/dri/0/amdgpu_vram bs=1048576 
> count=1 skip=6127 | hexdump -C |tail

That won't work. amdgpu_vram uses a MMIO register pair to access VRAM 
which works even when it isn't CPU visible.

Thinking more about it umr would probably use this as well, so that 
won't work either.

You could try to use dd on /dev/mem with the offset of the BAR.

> Anyway I agree that a PCI subsystem quirk might be appropriated.

I'm going to discuss AMD internally why you have such strange values in 
the RBAR registers.
>> Just send that to me as a complete and clean patchset. 
> Done, though only to the list. 

I have a few comments on the patches. They can use some polishing, but 
in general the approach looks solid to me.

Regards,
Christian.
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  reply	other threads:[~2020-12-11 16:47 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10  0:57 [PATCH] amdgpu: resize BAR0 to the maximum available size, even if it doesn't cover VRAM Darren Salt
2020-12-10 10:17 ` Christian König
2020-12-10 13:59   ` Darren Salt
2020-12-10 20:41     ` Christian König
2020-12-11  1:42       ` Darren Salt
2020-12-11 16:46         ` Christian König [this message]
2020-12-11 19:48           ` Darren Salt

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