[PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them

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* [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them
  2026-09-01  8:41 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v2) Timur Kristóf
@ 2026-09-01  8:41 ` Timur Kristóf
  0 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-01  8:41 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

The ring contains commands that were emitted before the reset.
These need to be cleared to make sure the HW doesn't execute
them, because they are garbage at this point.

Note that the ring reset helpers will re-emit the commands
that are necessary after the reset.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index fbac732f3e01..66f278f77f71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 		goto exit;
 	}
 
+	amdgpu_ring_clear_ring(gfx_ring);
+	gfx_ring->wptr = 0;
+	atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0);
+	atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0);
+
+	if (adev->sdma.has_page_queue) {
+		amdgpu_ring_clear_ring(page_ring);
+		page_ring->wptr = 0;
+		atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr, 0);
+		atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr, 0);
+	}
+
 	if (sdma_instance->funcs->start_kernel_queue) {
 		sdma_instance->funcs->start_kernel_queue(gfx_ring);
 		if (adev->sdma.has_page_queue)
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3)
@ 2026-09-04  7:28 Timur Kristóf
  2026-09-04  7:28 ` [PATCH 1/8] drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA Timur Kristóf
                   ` (7 more replies)
  0 siblings, 8 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

Improve SDMA queue reset for SDMA v4.4.2, v5.0, v5.2
and also moves some functionality from backend-specific
code to common code in the amdgpu_sdma.c file.

This prepares for implementing SDMA recovery
on more generations, as the same logic can be shared
with all SDMA HW generations that don't use the MES.
The actual recovery implementation for various
older SDMA versions will come in subsequent patch series
after this one is accepted.

Changes in v2:

* Added a fix for an issue in SDMA v4.4.2
* Further simplified some code

Changes in v3:

* Fixed typo (wrong scheduler for page ring)

Timur Kristóf (8):
  drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA
  drm/amdgpu/sdma: Remove superfluous rlc_resume and rlc_stop functions
  drm/amdgpu/sdma: Fix executing duplicate commands after recovery on
    SDMA v4.4.2
  drm/amdgpu/sdma: Remove unnecessary guilty tracking of SDMA queues
  drm/amdgpu/sdma: Clear SDMA rings after reset before starting them
  drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code
  drm/amdgpu/sdma: Always handle kernel queues in
    amdgpu_sdma_reset_engine()
  drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2

 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c      |   2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h      |   2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 109 ++++++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  11 +-
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c         |  32 ----
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c        |  30 ----
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c        |  38 +----
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c        |  40 +----
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      | 158 ++----------------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c        |  60 +------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c        |  52 +-----
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c        |  27 ---
 drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c        |  27 ---
 drivers/gpu/drm/amd/amdgpu/si_dma.c           |   7 -
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |   2 +-
 15 files changed, 109 insertions(+), 488 deletions(-)

-- 
2.55.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 1/8] drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-04  7:28 ` [PATCH 2/8] drm/amdgpu/sdma: Remove superfluous rlc_resume and rlc_stop functions Timur Kristóf
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

These functions are not called from anywhere
and don't do anything. Let's delete them.

Also remove the srbm_soft_reset field from amdgpu_sdma
which is not set anywhere anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 1 -
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 2 --
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 8 +++-----
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 8 --------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 --------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   | 8 --------
 drivers/gpu/drm/amd/amdgpu/si_dma.c      | 7 -------
 7 files changed, 3 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 4f4e56022c97..8a78d6967716 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -107,7 +107,6 @@ struct amdgpu_sdma {
 	    int			num_inst_per_aid;
 	    int			num_inst_per_xcc;
 	};
-	uint32_t                    srbm_soft_reset;
 	bool			has_page_queue;
 	struct ras_common_if	*ras_if;
 	struct amdgpu_sdma_ras	*ras;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 824ccac9f9f5..7040385a98d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -55,8 +55,6 @@ static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
 static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block);
 
-u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
-
 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6198bc2024e4..0d06e6643ade 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1229,13 +1229,11 @@ static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
-	u32 srbm_soft_reset = 0;
+	u32 srbm_soft_reset;
 	u32 tmp;
 
-	if (!adev->sdma.srbm_soft_reset)
-		return 0;
-
-	srbm_soft_reset = adev->sdma.srbm_soft_reset;
+	srbm_soft_reset = SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK |
+			  SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
 
 	if (srbm_soft_reset) {
 		tmp = RREG32(mmSRBM_SOFT_RESET);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index a0f19f7b39e6..bf71f99f7307 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2046,13 +2046,6 @@ static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v4_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
-	/* todo */
-
-	return 0;
-}
-
 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
 					struct amdgpu_irq_src *source,
 					unsigned type,
@@ -2398,7 +2391,6 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
 	.suspend = sdma_v4_0_suspend,
 	.resume = sdma_v4_0_resume,
 	.wait_for_idle = sdma_v4_0_wait_for_idle,
-	.soft_reset = sdma_v4_0_soft_reset,
 	.set_clockgating_state = sdma_v4_0_set_clockgating_state,
 	.set_powergating_state = sdma_v4_0_set_powergating_state,
 	.get_clockgating_state = sdma_v4_0_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 1a2810b6f27c..72ea9db939b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1646,13 +1646,6 @@ static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)
-{
-	/* todo */
-
-	return 0;
-}
-
 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)
 {
 	uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;
@@ -2104,7 +2097,6 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
 	.suspend = sdma_v4_4_2_suspend,
 	.resume = sdma_v4_4_2_resume,
 	.wait_for_idle = sdma_v4_4_2_wait_for_idle,
-	.soft_reset = sdma_v4_4_2_soft_reset,
 	.set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
 	.set_powergating_state = sdma_v4_4_2_set_powergating_state,
 	.get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 1a022a251011..0da54c335822 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1518,13 +1518,6 @@ static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block)
-{
-	/* todo */
-
-	return 0;
-}
-
 static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
 				 unsigned int vmid,
 				 struct amdgpu_fence *timedout_fence)
@@ -1902,7 +1895,6 @@ static const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
 	.suspend = sdma_v5_0_suspend,
 	.resume = sdma_v5_0_resume,
 	.wait_for_idle = sdma_v5_0_wait_for_idle,
-	.soft_reset = sdma_v5_0_soft_reset,
 	.set_clockgating_state = sdma_v5_0_set_clockgating_state,
 	.set_powergating_state = sdma_v5_0_set_powergating_state,
 	.get_clockgating_state = sdma_v5_0_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index edebd9109fd4..1df30779dcbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -594,12 +594,6 @@ static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int si_dma_soft_reset(struct amdgpu_ip_block *ip_block)
-{
-	drm_info(adev_to_drm(ip_block->adev), "si_dma_soft_reset --- not implemented !!!!!!!\n");
-	return 0;
-}
-
 static int si_dma_set_trap_irq_state(struct amdgpu_device *adev,
 					struct amdgpu_irq_src *src,
 					unsigned type,
@@ -726,7 +720,6 @@ static const struct amd_ip_funcs si_dma_ip_funcs = {
 	.suspend = si_dma_suspend,
 	.resume = si_dma_resume,
 	.wait_for_idle = si_dma_wait_for_idle,
-	.soft_reset = si_dma_soft_reset,
 	.set_clockgating_state = si_dma_set_clockgating_state,
 	.set_powergating_state = si_dma_set_powergating_state,
 };
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 2/8] drm/amdgpu/sdma: Remove superfluous rlc_resume and rlc_stop functions
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
  2026-09-04  7:28 ` [PATCH 1/8] drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-04  7:28 ` [PATCH 3/8] drm/amdgpu/sdma: Fix executing duplicate commands after recovery on SDMA v4.4.2 Timur Kristóf
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

Every SDMA generation has an rlc_resume and rlc_stop function
which are not doing anything.

Starting from CIK, the SDMA engine supports additional queues
which are called "SDMA compute" or "RLC" queues, and these
queues are used by the KFD, and configured using the HWS.
There is nothing for the kernel driver to do for these.

Let's delete the functions that don't do anything.
In case of SDMA v4.0 and v4.4.2 let's move the init_pg()
call to the start() function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c    | 30 --------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c   | 30 --------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c   | 30 --------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c   | 32 +--------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 36 +-----------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   | 27 ------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 27 ------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c   | 27 ------------------
 drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c   | 27 ------------------
 9 files changed, 2 insertions(+), 264 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 7040385a98d2..8c138f2fc026 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -316,18 +316,6 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * cik_sdma_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues (CIK).
- */
-static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * cik_ctx_switch_enable - stop the async dma engines context switch
  *
@@ -400,7 +388,6 @@ static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		cik_sdma_gfx_stop(adev);
-		cik_sdma_rlc_stop(adev);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -501,20 +488,6 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * cik_sdma_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them (CIK).
- * Returns 0 for success, error for failure.
- */
-static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-	return 0;
-}
-
 /**
  * cik_sdma_load_microcode - load the sDMA ME ucode
  *
@@ -577,9 +550,6 @@ static int cik_sdma_start(struct amdgpu_device *adev)
 
 	/* start the gfx rings and rlc compute queues */
 	r = cik_sdma_gfx_resume(adev);
-	if (r)
-		return r;
-	r = cik_sdma_rlc_resume(adev);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 9ef7134149d5..b9e0dbe726f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -349,18 +349,6 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * sdma_v2_4_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues (VI).
- */
-static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v2_4_enable - stop the async dma engines
  *
@@ -376,7 +364,6 @@ static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		sdma_v2_4_gfx_stop(adev);
-		sdma_v2_4_rlc_stop(adev);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -477,20 +464,6 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * sdma_v2_4_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them (VI).
- * Returns 0 for success, error for failure.
- */
-static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-	return 0;
-}
-
 
 /**
  * sdma_v2_4_start - setup and start the async dma engines
@@ -509,9 +482,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
 
 	/* start the gfx rings and rlc compute queues */
 	r = sdma_v2_4_gfx_resume(adev);
-	if (r)
-		return r;
-	r = sdma_v2_4_rlc_resume(adev);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 0d06e6643ade..8e83a309062b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -526,18 +526,6 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * sdma_v3_0_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues (VI).
- */
-static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
  *
@@ -614,7 +602,6 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		sdma_v3_0_gfx_stop(adev);
-		sdma_v3_0_rlc_stop(adev);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -752,20 +739,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * sdma_v3_0_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them (VI).
- * Returns 0 for success, error for failure.
- */
-static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-	return 0;
-}
-
 /**
  * sdma_v3_0_start - setup and start the async dma engines
  *
@@ -784,9 +757,6 @@ static int sdma_v3_0_start(struct amdgpu_device *adev)
 
 	/* start the gfx rings and rlc compute queues */
 	r = sdma_v3_0_gfx_resume(adev);
-	if (r)
-		return r;
-	r = sdma_v3_0_rlc_resume(adev);
 	if (r)
 		return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index bf71f99f7307..961f67a5983e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -933,18 +933,6 @@ static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)
 	}
 }
 
-/**
- * sdma_v4_0_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues (VEGA10).
- */
-static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v4_0_page_stop - stop the page async dma engines
  *
@@ -1047,7 +1035,6 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		sdma_v4_0_gfx_enable(adev, enable);
-		sdma_v4_0_rlc_stop(adev);
 		if (adev->sdma.has_page_queue)
 			sdma_v4_0_page_stop(adev);
 	}
@@ -1312,21 +1299,6 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * sdma_v4_0_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them (VEGA10).
- * Returns 0 for success, error for failure.
- */
-static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
-{
-	sdma_v4_0_init_pg(adev);
-
-	return 0;
-}
-
 /**
  * sdma_v4_0_load_microcode - load the sDMA ME ucode
  *
@@ -1426,9 +1398,7 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
 		sdma_v4_0_ctx_switch_enable(adev, true);
 		sdma_v4_0_enable(adev, true);
 	} else {
-		r = sdma_v4_0_rlc_resume(adev);
-		if (r)
-			return r;
+		sdma_v4_0_init_pg(adev);
 	}
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 72ea9db939b4..06b4bd8fca00 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -520,20 +520,6 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 	}
 }
 
-/**
- * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- * @inst_mask: mask of dma engine instances to be disabled
- *
- * Stop the compute async dma queues.
- */
-static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
-				      uint32_t inst_mask)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
  *
@@ -632,7 +618,6 @@ static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 
 	if (!enable) {
 		sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
-		sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 		if (adev->sdma.has_page_queue)
 			sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 
@@ -888,23 +873,6 @@ static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 
 }
 
-/**
- * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- * @inst_mask: mask of dma engine instances to be enabled
- *
- * Set up the compute DMA queues and enable them.
- * Returns 0 for success, error for failure.
- */
-static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
-				       uint32_t inst_mask)
-{
-	sdma_v4_4_2_init_pg(adev);
-
-	return 0;
-}
-
 /**
  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
  *
@@ -1019,9 +987,7 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 		sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 		sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 	} else {
-		r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
-		if (r)
-			return r;
+		sdma_v4_4_2_init_pg(adev);
 	}
 
 	tmp_mask = inst_mask;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 0da54c335822..b7bda6361ef9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -574,18 +574,6 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask)
 	}
 }
 
-/**
- * sdma_v5_0_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues (NAVI10).
- */
-static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
  *
@@ -661,7 +649,6 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
 	if (!enable) {
 		sdma_v5_0_gfx_stop(adev, 1 << inst_mask);
-		sdma_v5_0_rlc_stop(adev);
 	}
 
 	if (amdgpu_sriov_vf(adev))
@@ -858,19 +845,6 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * sdma_v5_0_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them (NAVI10).
- * Returns 0 for success, error for failure.
- */
-static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
-{
-	return 0;
-}
-
 /**
  * sdma_v5_0_load_microcode - load the sDMA ME ucode
  *
@@ -951,7 +925,6 @@ static int sdma_v5_0_start(struct amdgpu_device *adev)
 	r = sdma_v5_0_gfx_resume(adev);
 	if (r)
 		return r;
-	r = sdma_v5_0_rlc_resume(adev);
 
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 5543e381dcca..d063babab833 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -424,18 +424,6 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev,  uint32_t inst_mask)
 	}
 }
 
-/**
- * sdma_v5_2_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues.
- */
-static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
  *
@@ -510,7 +498,6 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
 	if (!enable) {
 		sdma_v5_2_gfx_stop(adev, inst_mask);
-		sdma_v5_2_rlc_stop(adev);
 	}
 
 	if (!amdgpu_sriov_vf(adev)) {
@@ -705,19 +692,6 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * sdma_v5_2_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them.
- * Returns 0 for success, error for failure.
- */
-static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
-{
-	return 0;
-}
-
 /**
  * sdma_v5_2_load_microcode - load the sDMA ME ucode
  *
@@ -851,7 +825,6 @@ static int sdma_v5_2_start(struct amdgpu_device *adev)
 	r = sdma_v5_2_gfx_resume(adev);
 	if (r)
 		return r;
-	r = sdma_v5_2_rlc_resume(adev);
 
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 3fd3e530c76b..22043a29fbb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -407,18 +407,6 @@ static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * sdma_v6_0_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues.
- */
-static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
  *
@@ -457,7 +445,6 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		sdma_v6_0_gfx_stop(adev);
-		sdma_v6_0_rlc_stop(adev);
 	}
 
 	if (amdgpu_sriov_vf(adev))
@@ -642,19 +629,6 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
 	return 0;
 }
 
-/**
- * sdma_v6_0_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them.
- * Returns 0 for success, error for failure.
- */
-static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
-{
-	return 0;
-}
-
 /**
  * sdma_v6_0_load_microcode - load the sDMA ME ucode
  *
@@ -832,7 +806,6 @@ static int sdma_v6_0_start(struct amdgpu_device *adev)
 	r = sdma_v6_0_gfx_resume(adev);
 	if (r)
 		return r;
-	r = sdma_v6_0_rlc_resume(adev);
 
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 745ec8b67b59..e8824d37a14a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -409,18 +409,6 @@ static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev)
 	}
 }
 
-/**
- * sdma_v7_0_rlc_stop - stop the compute async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Stop the compute async dma queues.
- */
-static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev)
-{
-	/* XXX todo */
-}
-
 /**
  * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch
  *
@@ -448,7 +436,6 @@ static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable)
 
 	if (!enable) {
 		sdma_v7_0_gfx_stop(adev);
-		sdma_v7_0_rlc_stop(adev);
 	}
 
 	if (amdgpu_sriov_vf(adev))
@@ -643,19 +630,6 @@ static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev)
 
 }
 
-/**
- * sdma_v7_0_rlc_resume - setup and start the async dma engines
- *
- * @adev: amdgpu_device pointer
- *
- * Set up the compute DMA queues and enable them.
- * Returns 0 for success, error for failure.
- */
-static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev)
-{
-	return 0;
-}
-
 static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev)
 {
 	int i;
@@ -850,7 +824,6 @@ static int sdma_v7_0_start(struct amdgpu_device *adev)
 	r = sdma_v7_0_gfx_resume(adev);
 	if (r)
 		return r;
-	r = sdma_v7_0_rlc_resume(adev);
 
 	return r;
 }
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 3/8] drm/amdgpu/sdma: Fix executing duplicate commands after recovery on SDMA v4.4.2
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
  2026-09-04  7:28 ` [PATCH 1/8] drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA Timur Kristóf
  2026-09-04  7:28 ` [PATCH 2/8] drm/amdgpu/sdma: Remove superfluous rlc_resume and rlc_stop functions Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-04  7:28 ` [PATCH 4/8] drm/amdgpu/sdma: Remove unnecessary guilty tracking of SDMA queues Timur Kristóf
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

SDMA v4.4.2 had a custom recovery implementation that
tried to keep ring contents and restore the rptr after
an SDMA soft reset. Later it was changed to use the
more common amdgpu_sdma_reset_engine() implementation.

Currently, SDMA v4.4.2 may execute some commands twice
after a recovery:

1. From the old ring buffer contents at the restored rptr
2. From the contents restored by amdgpu_sdma_reset_engine()
   that calls the ring reset helper functions.

Fix that by removing the code that restores rptr.
This is not needed anymore because amdgpu_sdma_reset_engine()
already saves and restores the contents of both the SDMA gfx
and paging rings, so there is no need to do anything extra.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c |  2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  2 -
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 76 +++++-------------------
 3 files changed, 14 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 686c92e96025..132ca5ce3a6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -347,8 +347,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 	ring->buf_mask = (ring->ring_size / 4) - 1;
 	ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
 		0xffffffffffffffff : ring->buf_mask;
-	/*  Initialize cached_rptr to 0 */
-	ring->cached_rptr = 0;
 
 	if (!ring->ring_backup) {
 		ring->ring_backup = kvzalloc(ring->ring_size, GFP_KERNEL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 015623b8fd05..5af539a89ba7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -423,8 +423,6 @@ struct amdgpu_ring {
 
 	bool            is_sw_ring;
 	unsigned int    entry_index;
-	/* store the cached rptr to restore after reset */
-	uint64_t cached_rptr;
 };
 
 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 06b4bd8fca00..890513d7c18f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -660,12 +660,11 @@ static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
  *
  * @adev: amdgpu_device pointer
  * @i: instance to resume
- * @restore: used to restore wptr when restart
  *
  * Set up the gfx DMA ring buffers and enable them.
  * Returns 0 for success, error for failure.
  */
-static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
+static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 {
 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
@@ -673,7 +672,6 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, b
 	u32 doorbell;
 	u32 doorbell_offset;
 	u64 wptr_gpu_addr;
-	u64 rwptr;
 
 	wb_offset = (ring->rptr_offs * 4);
 
@@ -693,32 +691,16 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, b
 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 
-	if (!restore)
-		ring->wptr = 0;
+	ring->wptr = 0;
 
 	/* before programing wptr to a less value, need set minor_ptr_update first */
 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 
-	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,
-	 * It is not a guilty queue, restore cache_rptr and continue execution.
-	 */
-	if (adev->sdma.instance[i].gfx_guilty)
-		rwptr = ring->wptr;
-	else
-		rwptr = ring->cached_rptr;
-
 	/* Initialize the ring buffer's read and write pointers */
-	if (restore) {
-		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2));
-	} else {
-		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
-		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
-		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
-		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
-	}
+	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
+	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
+	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
+	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 
 	doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 	doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
@@ -771,7 +753,7 @@ static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, b
  * Set up the page DMA ring buffers and enable them.
  * Returns 0 for success, error for failure.
  */
-static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
+static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 {
 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
@@ -779,7 +761,6 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i,
 	u32 doorbell;
 	u32 doorbell_offset;
 	u64 wptr_gpu_addr;
-	u64 rwptr;
 
 	wb_offset = (ring->rptr_offs * 4);
 
@@ -787,26 +768,11 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i,
 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 
-	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,
-	 * It is not a guilty queue, restore cache_rptr and continue execution.
-	 */
-	if (adev->sdma.instance[i].page_guilty)
-		rwptr = ring->wptr;
-	else
-		rwptr = ring->cached_rptr;
-
 	/* Initialize the ring buffer's read and write pointers */
-	if (restore) {
-		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2));
-		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2));
-	} else {
-		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
-		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
-		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
-		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
-	}
+	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
+	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
+	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
+	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 
 	/* set the wb address whether it's enabled or not */
 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
@@ -820,8 +786,7 @@ static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i,
 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 
-	if (!restore)
-		ring->wptr = 0;
+	ring->wptr = 0;
 
 	/* before programing wptr to a less value, need set minor_ptr_update first */
 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
@@ -959,9 +924,9 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 		uint32_t temp;
 
 		WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
-		sdma_v4_4_2_gfx_resume(adev, i, restore);
+		sdma_v4_4_2_gfx_resume(adev, i);
 		if (adev->sdma.has_page_queue)
-			sdma_v4_4_2_page_resume(adev, i, restore);
+			sdma_v4_4_2_page_resume(adev, i);
 
 		/* set utc l1 enable flag always to 1 */
 		temp = RREG32_SDMA(i, regSDMA_CNTL);
@@ -1640,7 +1605,6 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
 	struct amdgpu_device *adev = ring->adev;
 	u32 instance_id = ring->me;
 	u32 inst_mask;
-	uint64_t rptr;
 
 	if (amdgpu_sriov_vf(adev))
 		return -EINVAL;
@@ -1652,18 +1616,6 @@ static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
 		adev->sdma.instance[instance_id].page_guilty =
 			sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
 
-	/* Cache the rptr before reset, after the reset,
-	* all of the registers will be reset to 0
-	*/
-	rptr = amdgpu_ring_get_rptr(ring);
-	ring->cached_rptr = rptr;
-	/* Cache the rptr for the page queue if it exists */
-	if (adev->sdma.has_page_queue) {
-		struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page;
-		rptr = amdgpu_ring_get_rptr(page_ring);
-		page_ring->cached_rptr = rptr;
-	}
-
 	/* stop queue */
 	inst_mask = 1 << ring->me;
 	sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 4/8] drm/amdgpu/sdma: Remove unnecessary guilty tracking of SDMA queues
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
                   ` (2 preceding siblings ...)
  2026-09-04  7:28 ` [PATCH 3/8] drm/amdgpu/sdma: Fix executing duplicate commands after recovery on SDMA v4.4.2 Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-04  7:28 ` [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Timur Kristóf
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

amdgpu_sdma_reset_engine() saves and restores contents of
both the SDMA gfx queue and the paging queue, so it's
not necessary to track which queue was guilty anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  3 ---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 20 --------------------
 2 files changed, 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 8a78d6967716..055dd2522ecd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -79,9 +79,6 @@ struct amdgpu_sdma_instance {
 	uint64_t		sdma_fw_gpu_addr;
 	uint32_t		*sdma_fw_ptr;
 	struct mutex		engine_reset_mutex;
-	/* track guilty state of GFX and PAGE queues */
-	bool			gfx_guilty;
-	bool			page_guilty;
 	const struct amdgpu_sdma_funcs   *funcs;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 890513d7c18f..77f385b9ef53 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1404,9 +1404,6 @@ static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
 		mutex_init(&adev->sdma.instance[i].engine_reset_mutex);
-		/* Initialize guilty flags for GFX and PAGE queues */
-		adev->sdma.instance[i].gfx_guilty = false;
-		adev->sdma.instance[i].page_guilty = false;
 		adev->sdma.instance[i].funcs = &sdma_v4_4_2_sdma_funcs;
 
 		ring = &adev->sdma.instance[i].ring;
@@ -1577,15 +1574,6 @@ static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)
-{
-	uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;
-	uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));
-
-	/* Check if the SELECTED bit is set */
-	return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0;
-}
-
 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
 				   unsigned int vmid,
 				   struct amdgpu_fence *timedout_fence)
@@ -1603,19 +1591,11 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
-	u32 instance_id = ring->me;
 	u32 inst_mask;
 
 	if (amdgpu_sriov_vf(adev))
 		return -EINVAL;
 
-	/* Check if this queue is the guilty one */
-	adev->sdma.instance[instance_id].gfx_guilty =
-		sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
-	if (adev->sdma.has_page_queue)
-		adev->sdma.instance[instance_id].page_guilty =
-			sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
-
 	/* stop queue */
 	inst_mask = 1 << ring->me;
 	sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
                   ` (3 preceding siblings ...)
  2026-09-04  7:28 ` [PATCH 4/8] drm/amdgpu/sdma: Remove unnecessary guilty tracking of SDMA queues Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-07  7:04   ` Lazar, Lijo
  2026-09-04  7:28 ` [PATCH 6/8] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code Timur Kristóf
                   ` (2 subsequent siblings)
  7 siblings, 1 reply; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

The ring contains commands that were emitted before the reset.
These need to be cleared to make sure the HW doesn't execute
them, because they are garbage at this point.

Note that the ring reset helpers will re-emit the commands
that are necessary after the reset.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index fbac732f3e01..66f278f77f71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 		goto exit;
 	}
 
+	amdgpu_ring_clear_ring(gfx_ring);
+	gfx_ring->wptr = 0;
+	atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0);
+	atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0);
+
+	if (adev->sdma.has_page_queue) {
+		amdgpu_ring_clear_ring(page_ring);
+		page_ring->wptr = 0;
+		atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr, 0);
+		atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr, 0);
+	}
+
 	if (sdma_instance->funcs->start_kernel_queue) {
 		sdma_instance->funcs->start_kernel_queue(gfx_ring);
 		if (adev->sdma.has_page_queue)
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 6/8] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
                   ` (4 preceding siblings ...)
  2026-09-04  7:28 ` [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-04  7:28 ` [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine() Timur Kristóf
  2026-09-04  7:28 ` [PATCH 8/8] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2 Timur Kristóf
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

The code was exactly the same between SDMA v5.0 and v5.2
furthermore the exact same implementation can be shared
between all SDMA versions that don't use MES.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 37 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h |  4 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c   | 25 +---------------
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c   | 25 +---------------
 4 files changed, 43 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 66f278f77f71..9eebd8380834 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -635,3 +635,40 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 
 	return ret;
 }
+
+/**
+ * amdgpu_sdma_reset_queue_legacy() - Reset legacy SDMA queue after timeout (without MES)
+ *
+ * @ring: Pointer to the ring of the SDMA queue
+ * @vmid: VMID of the timed out job
+ * @timedout_fence: Fence of the timed out job
+ *
+ * Common implementation for resetting SDMA queues without MES (legacy).
+ * This relies on the proper amdgpu_sdma_funcs to be set up
+ * for the given ring.
+ *
+ * Applicable to SDMA versions that don't rely on the MES yet,
+ * that is all versions up to SDMA v5.x and older.
+ */
+int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
+				   unsigned int vmid,
+				   struct amdgpu_fence *timedout_fence)
+{
+	struct amdgpu_device *adev = ring->adev;
+	int r;
+
+	if (ring->me >= adev->sdma.num_instances) {
+		dev_err(adev->dev, "sdma instance not found\n");
+		return -EINVAL;
+	}
+
+	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
+
+	amdgpu_amdkfd_suspend(adev, true);
+	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
+	amdgpu_amdkfd_resume(adev, true);
+	if (r)
+		return r;
+
+	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 055dd2522ecd..cb41453c1a19 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -156,6 +156,10 @@ struct amdgpu_buffer_funcs {
 int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 			     bool caller_handles_kernel_queues);
 
+int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
+				   unsigned int vmid,
+				   struct amdgpu_fence *timedout_fence);
+
 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b7bda6361ef9..86eef0a361a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1491,29 +1491,6 @@ static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring,
-				 unsigned int vmid,
-				 struct amdgpu_fence *timedout_fence)
-{
-	struct amdgpu_device *adev = ring->adev;
-	int r;
-
-	if (ring->me >= adev->sdma.num_instances) {
-		dev_err(adev->dev, "sdma instance not found\n");
-		return -EINVAL;
-	}
-
-	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
-
-	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
-	amdgpu_amdkfd_resume(adev, true);
-	if (r)
-		return r;
-
-	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
-}
-
 static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring)
 {
 	u32 f32_cntl, freeze, cntl, stat1_reg;
@@ -1909,7 +1886,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
 	.emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
 	.init_cond_exec = sdma_v5_0_ring_init_cond_exec,
 	.preempt_ib = sdma_v5_0_ring_preempt_ib,
-	.reset = sdma_v5_0_reset_queue,
+	.reset = amdgpu_sdma_reset_queue_legacy,
 };
 
 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index d063babab833..09f00c99dd70 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1409,29 +1409,6 @@ static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring,
-				 unsigned int vmid,
-				 struct amdgpu_fence *timedout_fence)
-{
-	struct amdgpu_device *adev = ring->adev;
-	int r;
-
-	if (ring->me >= adev->sdma.num_instances) {
-		dev_err(adev->dev, "sdma instance not found\n");
-		return -EINVAL;
-	}
-
-	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
-
-	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
-	amdgpu_amdkfd_resume(adev, true);
-	if (r)
-		return r;
-
-	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
-}
-
 static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring)
 {
 	u32 f32_cntl, freeze, cntl, stat1_reg;
@@ -1924,7 +1901,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
 	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
 	.preempt_ib = sdma_v5_2_ring_preempt_ib,
-	.reset = sdma_v5_2_reset_queue,
+	.reset = amdgpu_sdma_reset_queue_legacy,
 };
 
 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine()
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
                   ` (5 preceding siblings ...)
  2026-09-04  7:28 ` [PATCH 6/8] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  2026-09-07  7:17   ` Lazar, Lijo
  2026-09-04  7:28 ` [PATCH 8/8] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2 Timur Kristóf
  7 siblings, 1 reply; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

Remove the caller_handles_kernel_queues argument from
the amdgpu_sdma_reset_engine() function and make it
always handle kernel queues.

Now the SDMA recovery sequence is more consistent
between callers for the KFD as follows.
Before recovery: first the KFD is suspended,
then the SDMA queue contents are backed up.
After recovery: first the SDMA queue contents
are restored, then the KFD is resumed.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 68 ++++++++++---------
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  3 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      |  2 +-
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |  2 +-
 4 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 9eebd8380834..07aac5b3ea92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -542,16 +542,14 @@ static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)
 }
 
 /**
- * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
+ * amdgpu_sdma_reset_engine() - Reset a specific SDMA engine instance.
+ *
  * @adev: Pointer to the AMDGPU device
  * @instance_id: Logical ID of the SDMA engine instance to reset
- * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
- * will handle it.
  *
  * Returns: 0 on success, or a negative error code on failure.
  */
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
-			     bool caller_handles_kernel_queues)
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
 {
 	struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id];
 	struct amdgpu_ring *gfx_ring = &sdma_instance->ring;
@@ -564,20 +562,23 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 
 	mutex_lock(&sdma_instance->engine_reset_mutex);
 
-	if (!caller_handles_kernel_queues) {
-		/* Stop the scheduler's work queue for the GFX and page rings if they are running.
-		 * This ensures that no new tasks are submitted to the queues while
-		 * the reset is in progress.
-		 */
+	/*
+	 * Stop the scheduler's work queue for the GFX and page rings if they are running.
+	 * This ensures that no new tasks are submitted to the queues while
+	 * the reset is in progress.
+	 */
+	if (amdgpu_ring_sched_ready(gfx_ring) && !drm_sched_is_stopped(&gfx_ring->sched))
 		drm_sched_wqueue_stop(&gfx_ring->sched);
-		gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
-		amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
 
-		if (adev->sdma.has_page_queue) {
+	gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
+	amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
+
+	if (adev->sdma.has_page_queue) {
+		if (amdgpu_ring_sched_ready(page_ring) && !drm_sched_is_stopped(&page_ring->sched))
 			drm_sched_wqueue_stop(&page_ring->sched);
-			page_fence = amdgpu_ring_find_guilty_fence(page_ring);
-			amdgpu_ring_reset_helper_begin(page_ring, page_fence);
-		}
+
+		page_fence = amdgpu_ring_find_guilty_fence(page_ring);
+		amdgpu_ring_reset_helper_begin(page_ring, page_fence);
 	}
 
 	if (sdma_instance->funcs->stop_kernel_queue) {
@@ -612,22 +613,25 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
 	}
 
 exit:
-	if (!caller_handles_kernel_queues) {
-		/* Restart the scheduler's work queue for the GFX and page rings
-		 * if they were stopped by this function. This allows new tasks
-		 * to be submitted to the queues after the reset is complete.
-		 */
-		if (!ret) {
-			ret = amdgpu_ring_reset_helper_end(gfx_ring, gfx_fence);
+	/* Restart the scheduler's work queue for the GFX and page rings
+	 * if they were stopped by this function. This allows new tasks
+	 * to be submitted to the queues after the reset is complete.
+	 */
+	if (!ret) {
+		ret = amdgpu_ring_reset_helper_end(gfx_ring, gfx_fence);
+		if (ret)
+			goto unlock;
+
+		if (amdgpu_ring_sched_ready(gfx_ring))
+			drm_sched_wqueue_start(&gfx_ring->sched);
+
+		if (adev->sdma.has_page_queue) {
+			ret = amdgpu_ring_reset_helper_end(page_ring, page_fence);
 			if (ret)
 				goto unlock;
-			drm_sched_wqueue_start(&gfx_ring->sched);
-			if (adev->sdma.has_page_queue) {
-				ret = amdgpu_ring_reset_helper_end(page_ring, page_fence);
-				if (ret)
-					goto unlock;
+
+			if (amdgpu_ring_sched_ready(page_ring))
 				drm_sched_wqueue_start(&page_ring->sched);
-			}
 		}
 	}
 unlock:
@@ -662,13 +666,11 @@ int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
 		return -EINVAL;
 	}
 
-	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
-
 	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
+	r = amdgpu_sdma_reset_engine(adev, ring->me);
 	amdgpu_amdkfd_resume(adev, true);
 	if (r)
 		return r;
 
-	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
+	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index cb41453c1a19..5709d438e824 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -153,8 +153,7 @@ struct amdgpu_buffer_funcs {
 				 uint32_t byte_count);
 };
 
-int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
-			     bool caller_handles_kernel_queues);
+int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id);
 
 int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
 				   unsigned int vmid,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 77f385b9ef53..796ea9f74763 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1583,7 +1583,7 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
 	int r;
 
 	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, id, false);
+	r = amdgpu_sdma_reset_engine(adev, id);
 	amdgpu_amdkfd_resume(adev, true);
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index a23384571193..f9fbc5628fb4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -2576,7 +2576,7 @@ static int reset_hung_queues_sdma(struct device_queue_manager *dqm)
 				continue;
 
 			/* Reset engine and check. */
-			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) ||
+			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i) ||
 			    dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
 			    !set_sdma_queue_as_reset(dqm, doorbell_off)) {
 				r = -ENOTRECOVERABLE;
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 8/8] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2
  2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
                   ` (6 preceding siblings ...)
  2026-09-04  7:28 ` [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine() Timur Kristóf
@ 2026-09-04  7:28 ` Timur Kristóf
  7 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-04  7:28 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lijo Lazar
  Cc: Timur Kristóf

Now, sdma_v4_4_2_reset_queue() does basically the same
as amdgpu_sdma_reset_queue_legacy() so let's use that.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 18 ++----------------
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 796ea9f74763..60bb22d0a43b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1574,20 +1574,6 @@ static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
 	return -ETIMEDOUT;
 }
 
-static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
-				   unsigned int vmid,
-				   struct amdgpu_fence *timedout_fence)
-{
-	struct amdgpu_device *adev = ring->adev;
-	u32 id = ring->me;
-	int r;
-
-	amdgpu_amdkfd_suspend(adev, true);
-	r = amdgpu_sdma_reset_engine(adev, id);
-	amdgpu_amdkfd_resume(adev, true);
-	return r;
-}
-
 static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring)
 {
 	struct amdgpu_device *adev = ring->adev;
@@ -2031,7 +2017,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
-	.reset = sdma_v4_4_2_reset_queue,
+	.reset = amdgpu_sdma_reset_queue_legacy,
 };
 
 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
@@ -2063,7 +2049,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
-	.reset = sdma_v4_4_2_reset_queue,
+	.reset = amdgpu_sdma_reset_queue_legacy,
 };
 
 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them
  2026-09-04  7:28 ` [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Timur Kristóf
@ 2026-09-07  7:04   ` Lazar, Lijo
  2026-09-07 18:31     ` Timur Kristóf
  0 siblings, 1 reply; 15+ messages in thread
From: Lazar, Lijo @ 2026-09-07  7:04 UTC (permalink / raw)
  To: Timur Kristóf, amd-gfx, Alexander.Deucher,
	Christian König, Natalie Vock, Tvrtko Ursulin,
	Felix Kuehling



On 04-Sep-26 12:58 PM, Timur Kristóf wrote:
> The ring contains commands that were emitted before the reset.
> These need to be cleared to make sure the HW doesn't execute
> them, because they are garbage at this point.
> 
> Note that the ring reset helpers will re-emit the commands
> that are necessary after the reset.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index fbac732f3e01..66f278f77f71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
>   		goto exit;
>   	}
>   
> +	amdgpu_ring_clear_ring(gfx_ring);
> +	gfx_ring->wptr = 0;
> +	atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0);
> +	atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0);
> +
> +	if (adev->sdma.has_page_queue) {
> +		amdgpu_ring_clear_ring(page_ring);
> +		page_ring->wptr = 0;
> +		atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr, 0);
> +		atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr, 0);
> +	}

This could be made as a small inline function like 
amdgpu_ring_reset_ptr(ring);

Thanks,
Lijo

> +
>   	if (sdma_instance->funcs->start_kernel_queue) {
>   		sdma_instance->funcs->start_kernel_queue(gfx_ring);
>   		if (adev->sdma.has_page_queue)


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine()
  2026-09-04  7:28 ` [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine() Timur Kristóf
@ 2026-09-07  7:17   ` Lazar, Lijo
  2026-09-07 18:34     ` Timur Kristóf
  0 siblings, 1 reply; 15+ messages in thread
From: Lazar, Lijo @ 2026-09-07  7:17 UTC (permalink / raw)
  To: Timur Kristóf, amd-gfx, Alexander.Deucher,
	Christian König, Natalie Vock, Tvrtko Ursulin,
	Felix Kuehling



On 04-Sep-26 12:58 PM, Timur Kristóf wrote:
> Remove the caller_handles_kernel_queues argument from
> the amdgpu_sdma_reset_engine() function and make it
> always handle kernel queues.
> 
> Now the SDMA recovery sequence is more consistent
> between callers for the KFD as follows.
> Before recovery: first the KFD is suspended,
> then the SDMA queue contents are backed up.
> After recovery: first the SDMA queue contents
> are restored, then the KFD is resumed.
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 68 ++++++++++---------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  3 +-
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      |  2 +-
>   .../drm/amd/amdkfd/kfd_device_queue_manager.c |  2 +-
>   4 files changed, 38 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index 9eebd8380834..07aac5b3ea92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -542,16 +542,14 @@ static int amdgpu_sdma_soft_reset(struct amdgpu_device *adev, u32 instance_id)
>   }
>   
>   /**
> - * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
> + * amdgpu_sdma_reset_engine() - Reset a specific SDMA engine instance.
> + *
>    * @adev: Pointer to the AMDGPU device
>    * @instance_id: Logical ID of the SDMA engine instance to reset
> - * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
> - * will handle it.
>    *
>    * Returns: 0 on success, or a negative error code on failure.
>    */
> -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
> -			     bool caller_handles_kernel_queues)
> +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id)
>   {
>   	struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id];
>   	struct amdgpu_ring *gfx_ring = &sdma_instance->ring;
> @@ -564,20 +562,23 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
>   
>   	mutex_lock(&sdma_instance->engine_reset_mutex);
>   
> -	if (!caller_handles_kernel_queues) {
> -		/* Stop the scheduler's work queue for the GFX and page rings if they are running.
> -		 * This ensures that no new tasks are submitted to the queues while
> -		 * the reset is in progress.
> -		 */
> +	/*
> +	 * Stop the scheduler's work queue for the GFX and page rings if they are running.
> +	 * This ensures that no new tasks are submitted to the queues while
> +	 * the reset is in progress.
> +	 */
> +	if (amdgpu_ring_sched_ready(gfx_ring) && !drm_sched_is_stopped(&gfx_ring->sched))
>   		drm_sched_wqueue_stop(&gfx_ring->sched);
> -		gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
> -		amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
>   
> -		if (adev->sdma.has_page_queue) {
> +	gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
> +	amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
> +
> +	if (adev->sdma.has_page_queue) {
> +		if (amdgpu_ring_sched_ready(page_ring) && !drm_sched_is_stopped(&page_ring->sched))
>   			drm_sched_wqueue_stop(&page_ring->sched);
> -			page_fence = amdgpu_ring_find_guilty_fence(page_ring);
> -			amdgpu_ring_reset_helper_begin(page_ring, page_fence);
> -		}
> +
> +		page_fence = amdgpu_ring_find_guilty_fence(page_ring);
> +		amdgpu_ring_reset_helper_begin(page_ring, page_fence);
>   	}


Since this resets the engine, a different way may be to have something 
like below (similar to amdgpu_multi_ring_reset_helper_begin) which takes 
care of all rings in the engine instance.

amdgpu_ring_engine_reset_helper_begin(guilty_ring, guilty_fence);

amdgpu_ring_engine_reset_helper_end(guilty_ring, guilty_fence);

ring_type = guilty_ring->funcs->type;
eng_instance = guilty_ring->me

Thanks,
Lijo

>   
>   	if (sdma_instance->funcs->stop_kernel_queue) {
> @@ -612,22 +613,25 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
>   	}
>   
>   exit:
> -	if (!caller_handles_kernel_queues) {
> -		/* Restart the scheduler's work queue for the GFX and page rings
> -		 * if they were stopped by this function. This allows new tasks
> -		 * to be submitted to the queues after the reset is complete.
> -		 */
> -		if (!ret) {
> -			ret = amdgpu_ring_reset_helper_end(gfx_ring, gfx_fence);
> +	/* Restart the scheduler's work queue for the GFX and page rings
> +	 * if they were stopped by this function. This allows new tasks
> +	 * to be submitted to the queues after the reset is complete.
> +	 */
> +	if (!ret) {
> +		ret = amdgpu_ring_reset_helper_end(gfx_ring, gfx_fence);
> +		if (ret)
> +			goto unlock;
> +
> +		if (amdgpu_ring_sched_ready(gfx_ring))
> +			drm_sched_wqueue_start(&gfx_ring->sched);
> +
> +		if (adev->sdma.has_page_queue) {
> +			ret = amdgpu_ring_reset_helper_end(page_ring, page_fence);
>   			if (ret)
>   				goto unlock;
> -			drm_sched_wqueue_start(&gfx_ring->sched);
> -			if (adev->sdma.has_page_queue) {
> -				ret = amdgpu_ring_reset_helper_end(page_ring, page_fence);
> -				if (ret)
> -					goto unlock;
> +
> +			if (amdgpu_ring_sched_ready(page_ring))
>   				drm_sched_wqueue_start(&page_ring->sched);
> -			}
>   		}
>   	}
>   unlock:
> @@ -662,13 +666,11 @@ int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
>   		return -EINVAL;
>   	}
>   
> -	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
> -
>   	amdgpu_amdkfd_suspend(adev, true);
> -	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
> +	r = amdgpu_sdma_reset_engine(adev, ring->me);
>   	amdgpu_amdkfd_resume(adev, true);
>   	if (r)
>   		return r;
>   
> -	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
> +	return 0;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> index cb41453c1a19..5709d438e824 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> @@ -153,8 +153,7 @@ struct amdgpu_buffer_funcs {
>   				 uint32_t byte_count);
>   };
>   
> -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id,
> -			     bool caller_handles_kernel_queues);
> +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id);
>   
>   int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
>   				   unsigned int vmid,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index 77f385b9ef53..796ea9f74763 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -1583,7 +1583,7 @@ static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring,
>   	int r;
>   
>   	amdgpu_amdkfd_suspend(adev, true);
> -	r = amdgpu_sdma_reset_engine(adev, id, false);
> +	r = amdgpu_sdma_reset_engine(adev, id);
>   	amdgpu_amdkfd_resume(adev, true);
>   	return r;
>   }
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index a23384571193..f9fbc5628fb4 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -2576,7 +2576,7 @@ static int reset_hung_queues_sdma(struct device_queue_manager *dqm)
>   				continue;
>   
>   			/* Reset engine and check. */
> -			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i, false) ||
> +			if (amdgpu_sdma_reset_engine(dqm->dev->adev, i) ||
>   			    dqm->dev->kfd2kgd->hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
>   			    !set_sdma_queue_as_reset(dqm, doorbell_off)) {
>   				r = -ENOTRECOVERABLE;


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them
  2026-09-07  7:04   ` Lazar, Lijo
@ 2026-09-07 18:31     ` Timur Kristóf
  0 siblings, 0 replies; 15+ messages in thread
From: Timur Kristóf @ 2026-09-07 18:31 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lazar, Lijo

On 2026. szeptember 7., hétfő 9:04:55 közép-európai nyári idő Lazar, Lijo 
wrote:
> On 04-Sep-26 12:58 PM, Timur Kristóf wrote:
> > The ring contains commands that were emitted before the reset.
> > These need to be cleared to make sure the HW doesn't execute
> > them, because they are garbage at this point.
> > 
> > Note that the ring reset helpers will re-emit the commands
> > that are necessary after the reset.
> > 
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > ---
> > 
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index
> > fbac732f3e01..66f278f77f71 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > @@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device
> > *adev, uint32_t instance_id,> 
> >   		goto exit;
> >   	
> >   	}
> > 
> > +	amdgpu_ring_clear_ring(gfx_ring);
> > +	gfx_ring->wptr = 0;
> > +	atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0);
> > +	atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0);
> > +
> > +	if (adev->sdma.has_page_queue) {
> > +		amdgpu_ring_clear_ring(page_ring);
> > +		page_ring->wptr = 0;
> > +		atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr, 
0);
> > +		atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr, 
0);
> > +	}
> 
> This could be made as a small inline function like
> amdgpu_ring_reset_ptr(ring);
> 
> Thanks,
> Lijo

Thank you for the suggestion, I'll add that to the next version of the series.

> 
> > +
> > 
> >   	if (sdma_instance->funcs->start_kernel_queue) {
> >   	
> >   		sdma_instance->funcs->start_kernel_queue(gfx_ring);
> >   		if (adev->sdma.has_page_queue)





^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine()
  2026-09-07  7:17   ` Lazar, Lijo
@ 2026-09-07 18:34     ` Timur Kristóf
  2026-09-08  3:25       ` Lazar, Lijo
  0 siblings, 1 reply; 15+ messages in thread
From: Timur Kristóf @ 2026-09-07 18:34 UTC (permalink / raw)
  To: amd-gfx, Alexander.Deucher, Christian König, Natalie Vock,
	Tvrtko Ursulin, Felix Kuehling, Lazar, Lijo

On 2026. szeptember 7., hétfő 9:17:12 közép-európai nyári idő Lazar, Lijo 
wrote:
> On 04-Sep-26 12:58 PM, Timur Kristóf wrote:
> > Remove the caller_handles_kernel_queues argument from
> > the amdgpu_sdma_reset_engine() function and make it
> > always handle kernel queues.
> > 
> > Now the SDMA recovery sequence is more consistent
> > between callers for the KFD as follows.
> > Before recovery: first the KFD is suspended,
> > then the SDMA queue contents are backed up.
> > After recovery: first the SDMA queue contents
> > are restored, then the KFD is resumed.
> > 
> > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > ---
> > 
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 68 ++++++++++---------
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  3 +-
> >   drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      |  2 +-
> >   .../drm/amd/amdkfd/kfd_device_queue_manager.c |  2 +-
> >   4 files changed, 38 insertions(+), 37 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index
> > 9eebd8380834..07aac5b3ea92 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> > @@ -542,16 +542,14 @@ static int amdgpu_sdma_soft_reset(struct
> > amdgpu_device *adev, u32 instance_id)> 
> >   }
> >   
> >   /**
> > 
> > - * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
> > + * amdgpu_sdma_reset_engine() - Reset a specific SDMA engine instance.
> > + *
> > 
> >    * @adev: Pointer to the AMDGPU device
> >    * @instance_id: Logical ID of the SDMA engine instance to reset
> > 
> > - * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
> > - * will handle it.
> > 
> >    *
> >    * Returns: 0 on success, or a negative error code on failure.
> >    */
> > 
> > -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
> > instance_id, -			     bool 
caller_handles_kernel_queues)
> > +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
> > instance_id)> 
> >   {
> >   
> >   	struct amdgpu_sdma_instance *sdma_instance =
> >   	&adev->sdma.instance[instance_id]; struct amdgpu_ring *gfx_ring =
> >   	&sdma_instance->ring;
> > 
> > @@ -564,20 +562,23 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device
> > *adev, uint32_t instance_id,> 
> >   	mutex_lock(&sdma_instance->engine_reset_mutex);
> > 
> > -	if (!caller_handles_kernel_queues) {
> > -		/* Stop the scheduler's work queue for the GFX and page 
rings if they
> > are running. -		 * This ensures that no new tasks are 
submitted to the
> > queues while -		 * the reset is in progress.
> > -		 */
> > +	/*
> > +	 * Stop the scheduler's work queue for the GFX and page rings if 
they
> > are running. +	 * This ensures that no new tasks are submitted to 
the
> > queues while +	 * the reset is in progress.
> > +	 */
> > +	if (amdgpu_ring_sched_ready(gfx_ring) &&
> > !drm_sched_is_stopped(&gfx_ring->sched))> 
> >   		drm_sched_wqueue_stop(&gfx_ring->sched);
> > 
> > -		gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
> > -		amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
> > 
> > -		if (adev->sdma.has_page_queue) {
> > +	gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
> > +	amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
> > +
> > +	if (adev->sdma.has_page_queue) {
> > +		if (amdgpu_ring_sched_ready(page_ring) &&
> > !drm_sched_is_stopped(&page_ring->sched))> 
> >   			drm_sched_wqueue_stop(&page_ring->sched);
> > 
> > -			page_fence = 
amdgpu_ring_find_guilty_fence(page_ring);
> > -			amdgpu_ring_reset_helper_begin(page_ring, 
page_fence);
> > -		}
> > +
> > +		page_fence = amdgpu_ring_find_guilty_fence(page_ring);
> > +		amdgpu_ring_reset_helper_begin(page_ring, page_fence);
> > 
> >   	}
> 
> Since this resets the engine, a different way may be to have something
> like below (similar to amdgpu_multi_ring_reset_helper_begin) which takes
> care of all rings in the engine instance.
> 
> amdgpu_ring_engine_reset_helper_begin(guilty_ring, guilty_fence);
> 
> amdgpu_ring_engine_reset_helper_end(guilty_ring, guilty_fence);
> 
> ring_type = guilty_ring->funcs->type;
> eng_instance = guilty_ring->me
> 
> Thanks,
> Lijo

I am planning to do exactly that, but I want to keep this series short and 
focused on unifying the code paths for SDMA v4.4.2 and v5.x.

Is it OK if I do that in a follow-up series?

Thanks,
Timur

> 
> >   	if (sdma_instance->funcs->stop_kernel_queue) {
> > 
> > @@ -612,22 +613,25 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device
> > *adev, uint32_t instance_id,> 
> >   	}
> >   
> >   exit:
> > -	if (!caller_handles_kernel_queues) {
> > -		/* Restart the scheduler's work queue for the GFX and 
page rings
> > -		 * if they were stopped by this function. This allows 
new tasks
> > -		 * to be submitted to the queues after the reset is 
complete.
> > -		 */
> > -		if (!ret) {
> > -			ret = amdgpu_ring_reset_helper_end(gfx_ring, 
gfx_fence);
> > +	/* Restart the scheduler's work queue for the GFX and page rings
> > +	 * if they were stopped by this function. This allows new tasks
> > +	 * to be submitted to the queues after the reset is complete.
> > +	 */
> > +	if (!ret) {
> > +		ret = amdgpu_ring_reset_helper_end(gfx_ring, 
gfx_fence);
> > +		if (ret)
> > +			goto unlock;
> > +
> > +		if (amdgpu_ring_sched_ready(gfx_ring))
> > +			drm_sched_wqueue_start(&gfx_ring->sched);
> > +
> > +		if (adev->sdma.has_page_queue) {
> > +			ret = 
amdgpu_ring_reset_helper_end(page_ring, page_fence);
> > 
> >   			if (ret)
> >   			
> >   				goto unlock;
> > 
> > -			drm_sched_wqueue_start(&gfx_ring->sched);
> > -			if (adev->sdma.has_page_queue) {
> > -				ret = 
amdgpu_ring_reset_helper_end(page_ring, page_fence);
> > -				if (ret)
> > -					goto unlock;
> > +
> > +			if (amdgpu_ring_sched_ready(page_ring))
> > 
> >   				
drm_sched_wqueue_start(&page_ring->sched);
> > 
> > -			}
> > 
> >   		}
> >   	
> >   	}
> >   
> >   unlock:
> > @@ -662,13 +666,11 @@ int amdgpu_sdma_reset_queue_legacy(struct
> > amdgpu_ring *ring,> 
> >   		return -EINVAL;
> >   	
> >   	}
> > 
> > -	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
> > -
> > 
> >   	amdgpu_amdkfd_suspend(adev, true);
> > 
> > -	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
> > +	r = amdgpu_sdma_reset_engine(adev, ring->me);
> > 
> >   	amdgpu_amdkfd_resume(adev, true);
> >   	if (r)
> >   	
> >   		return r;
> > 
> > -	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
> > +	return 0;
> > 
> >   }
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index
> > cb41453c1a19..5709d438e824 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
> > @@ -153,8 +153,7 @@ struct amdgpu_buffer_funcs {
> > 
> >   				 uint32_t byte_count);
> >   
> >   };
> > 
> > -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
> > instance_id, -			     bool 
caller_handles_kernel_queues);
> > +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
> > instance_id);> 
> >   int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
> >   
> >   				   unsigned int vmid,
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index
> > 77f385b9ef53..796ea9f74763 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> > @@ -1583,7 +1583,7 @@ static int sdma_v4_4_2_reset_queue(struct
> > amdgpu_ring *ring,> 
> >   	int r;
> >   	
> >   	amdgpu_amdkfd_suspend(adev, true);
> > 
> > -	r = amdgpu_sdma_reset_engine(adev, id, false);
> > +	r = amdgpu_sdma_reset_engine(adev, id);
> > 
> >   	amdgpu_amdkfd_resume(adev, true);
> >   	return r;
> >   
> >   }
> > 
> > diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index
> > a23384571193..f9fbc5628fb4 100644
> > --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> > @@ -2576,7 +2576,7 @@ static int reset_hung_queues_sdma(struct
> > device_queue_manager *dqm)> 
> >   				continue;
> >   			
> >   			/* Reset engine and check. */
> > 
> > -			if (amdgpu_sdma_reset_engine(dqm->dev->adev, 
i, false) ||
> > +			if (amdgpu_sdma_reset_engine(dqm->dev->adev, 
i) ||
> > 
> >   			    dqm->dev->kfd2kgd-
>hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
> >   			    !set_sdma_queue_as_reset(dqm, 
doorbell_off)) {
> >   				
> >   				r = -ENOTRECOVERABLE;





^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine()
  2026-09-07 18:34     ` Timur Kristóf
@ 2026-09-08  3:25       ` Lazar, Lijo
  0 siblings, 0 replies; 15+ messages in thread
From: Lazar, Lijo @ 2026-09-08  3:25 UTC (permalink / raw)
  To: Timur Kristóf, amd-gfx, Alexander.Deucher,
	Christian König, Natalie Vock, Tvrtko Ursulin,
	Felix Kuehling



On 08-Sep-26 12:04 AM, Timur Kristóf wrote:
> On 2026. szeptember 7., hétfő 9:17:12 közép-európai nyári idő Lazar, Lijo
> wrote:
>> On 04-Sep-26 12:58 PM, Timur Kristóf wrote:
>>> Remove the caller_handles_kernel_queues argument from
>>> the amdgpu_sdma_reset_engine() function and make it
>>> always handle kernel queues.
>>>
>>> Now the SDMA recovery sequence is more consistent
>>> between callers for the KFD as follows.
>>> Before recovery: first the KFD is suspended,
>>> then the SDMA queue contents are backed up.
>>> After recovery: first the SDMA queue contents
>>> are restored, then the KFD is resumed.
>>>
>>> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
>>> ---
>>>
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c      | 68 ++++++++++---------
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h      |  3 +-
>>>    drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c      |  2 +-
>>>    .../drm/amd/amdkfd/kfd_device_queue_manager.c |  2 +-
>>>    4 files changed, 38 insertions(+), 37 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index
>>> 9eebd8380834..07aac5b3ea92 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>>> @@ -542,16 +542,14 @@ static int amdgpu_sdma_soft_reset(struct
>>> amdgpu_device *adev, u32 instance_id)>
>>>    }
>>>    
>>>    /**
>>>
>>> - * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
>>> + * amdgpu_sdma_reset_engine() - Reset a specific SDMA engine instance.
>>> + *
>>>
>>>     * @adev: Pointer to the AMDGPU device
>>>     * @instance_id: Logical ID of the SDMA engine instance to reset
>>>
>>> - * @caller_handles_kernel_queues: Skip kernel queue processing. Caller
>>> - * will handle it.
>>>
>>>     *
>>>     * Returns: 0 on success, or a negative error code on failure.
>>>     */
>>>
>>> -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
>>> instance_id, -			     bool
> caller_handles_kernel_queues)
>>> +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
>>> instance_id)>
>>>    {
>>>    
>>>    	struct amdgpu_sdma_instance *sdma_instance =
>>>    	&adev->sdma.instance[instance_id]; struct amdgpu_ring *gfx_ring =
>>>    	&sdma_instance->ring;
>>>
>>> @@ -564,20 +562,23 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device
>>> *adev, uint32_t instance_id,>
>>>    	mutex_lock(&sdma_instance->engine_reset_mutex);
>>>
>>> -	if (!caller_handles_kernel_queues) {
>>> -		/* Stop the scheduler's work queue for the GFX and page
> rings if they
>>> are running. -		 * This ensures that no new tasks are
> submitted to the
>>> queues while -		 * the reset is in progress.
>>> -		 */
>>> +	/*
>>> +	 * Stop the scheduler's work queue for the GFX and page rings if
> they
>>> are running. +	 * This ensures that no new tasks are submitted to
> the
>>> queues while +	 * the reset is in progress.
>>> +	 */
>>> +	if (amdgpu_ring_sched_ready(gfx_ring) &&
>>> !drm_sched_is_stopped(&gfx_ring->sched))>
>>>    		drm_sched_wqueue_stop(&gfx_ring->sched);
>>>
>>> -		gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
>>> -		amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
>>>
>>> -		if (adev->sdma.has_page_queue) {
>>> +	gfx_fence = amdgpu_ring_find_guilty_fence(gfx_ring);
>>> +	amdgpu_ring_reset_helper_begin(gfx_ring, gfx_fence);
>>> +
>>> +	if (adev->sdma.has_page_queue) {
>>> +		if (amdgpu_ring_sched_ready(page_ring) &&
>>> !drm_sched_is_stopped(&page_ring->sched))>
>>>    			drm_sched_wqueue_stop(&page_ring->sched);
>>>
>>> -			page_fence =
> amdgpu_ring_find_guilty_fence(page_ring);
>>> -			amdgpu_ring_reset_helper_begin(page_ring,
> page_fence);
>>> -		}
>>> +
>>> +		page_fence = amdgpu_ring_find_guilty_fence(page_ring);
>>> +		amdgpu_ring_reset_helper_begin(page_ring, page_fence);
>>>
>>>    	}
>>
>> Since this resets the engine, a different way may be to have something
>> like below (similar to amdgpu_multi_ring_reset_helper_begin) which takes
>> care of all rings in the engine instance.
>>
>> amdgpu_ring_engine_reset_helper_begin(guilty_ring, guilty_fence);
>>
>> amdgpu_ring_engine_reset_helper_end(guilty_ring, guilty_fence);
>>
>> ring_type = guilty_ring->funcs->type;
>> eng_instance = guilty_ring->me
>>
>> Thanks,
>> Lijo
> 
> I am planning to do exactly that, but I want to keep this series short and
> focused on unifying the code paths for SDMA v4.4.2 and v5.x.
> 
> Is it OK if I do that in a follow-up series?
> 

Yes, that will do.

Thanks,
Lijo

> Thanks,
> Timur
> 
>>
>>>    	if (sdma_instance->funcs->stop_kernel_queue) {
>>>
>>> @@ -612,22 +613,25 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device
>>> *adev, uint32_t instance_id,>
>>>    	}
>>>    
>>>    exit:
>>> -	if (!caller_handles_kernel_queues) {
>>> -		/* Restart the scheduler's work queue for the GFX and
> page rings
>>> -		 * if they were stopped by this function. This allows
> new tasks
>>> -		 * to be submitted to the queues after the reset is
> complete.
>>> -		 */
>>> -		if (!ret) {
>>> -			ret = amdgpu_ring_reset_helper_end(gfx_ring,
> gfx_fence);
>>> +	/* Restart the scheduler's work queue for the GFX and page rings
>>> +	 * if they were stopped by this function. This allows new tasks
>>> +	 * to be submitted to the queues after the reset is complete.
>>> +	 */
>>> +	if (!ret) {
>>> +		ret = amdgpu_ring_reset_helper_end(gfx_ring,
> gfx_fence);
>>> +		if (ret)
>>> +			goto unlock;
>>> +
>>> +		if (amdgpu_ring_sched_ready(gfx_ring))
>>> +			drm_sched_wqueue_start(&gfx_ring->sched);
>>> +
>>> +		if (adev->sdma.has_page_queue) {
>>> +			ret =
> amdgpu_ring_reset_helper_end(page_ring, page_fence);
>>>
>>>    			if (ret)
>>>    			
>>>    				goto unlock;
>>>
>>> -			drm_sched_wqueue_start(&gfx_ring->sched);
>>> -			if (adev->sdma.has_page_queue) {
>>> -				ret =
> amdgpu_ring_reset_helper_end(page_ring, page_fence);
>>> -				if (ret)
>>> -					goto unlock;
>>> +
>>> +			if (amdgpu_ring_sched_ready(page_ring))
>>>
>>>    				
> drm_sched_wqueue_start(&page_ring->sched);
>>>
>>> -			}
>>>
>>>    		}
>>>    	
>>>    	}
>>>    
>>>    unlock:
>>> @@ -662,13 +666,11 @@ int amdgpu_sdma_reset_queue_legacy(struct
>>> amdgpu_ring *ring,>
>>>    		return -EINVAL;
>>>    	
>>>    	}
>>>
>>> -	amdgpu_ring_reset_helper_begin(ring, timedout_fence);
>>> -
>>>
>>>    	amdgpu_amdkfd_suspend(adev, true);
>>>
>>> -	r = amdgpu_sdma_reset_engine(adev, ring->me, true);
>>> +	r = amdgpu_sdma_reset_engine(adev, ring->me);
>>>
>>>    	amdgpu_amdkfd_resume(adev, true);
>>>    	if (r)
>>>    	
>>>    		return r;
>>>
>>> -	return amdgpu_ring_reset_helper_end(ring, timedout_fence);
>>> +	return 0;
>>>
>>>    }
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index
>>> cb41453c1a19..5709d438e824 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> @@ -153,8 +153,7 @@ struct amdgpu_buffer_funcs {
>>>
>>>    				 uint32_t byte_count);
>>>    
>>>    };
>>>
>>> -int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
>>> instance_id, -			     bool
> caller_handles_kernel_queues);
>>> +int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t
>>> instance_id);>
>>>    int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring,
>>>    
>>>    				   unsigned int vmid,
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index
>>> 77f385b9ef53..796ea9f74763 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>>> @@ -1583,7 +1583,7 @@ static int sdma_v4_4_2_reset_queue(struct
>>> amdgpu_ring *ring,>
>>>    	int r;
>>>    	
>>>    	amdgpu_amdkfd_suspend(adev, true);
>>>
>>> -	r = amdgpu_sdma_reset_engine(adev, id, false);
>>> +	r = amdgpu_sdma_reset_engine(adev, id);
>>>
>>>    	amdgpu_amdkfd_resume(adev, true);
>>>    	return r;
>>>    
>>>    }
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index
>>> a23384571193..f9fbc5628fb4 100644
>>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>>> @@ -2576,7 +2576,7 @@ static int reset_hung_queues_sdma(struct
>>> device_queue_manager *dqm)>
>>>    				continue;
>>>    			
>>>    			/* Reset engine and check. */
>>>
>>> -			if (amdgpu_sdma_reset_engine(dqm->dev->adev,
> i, false) ||
>>> +			if (amdgpu_sdma_reset_engine(dqm->dev->adev,
> i) ||
>>>
>>>    			    dqm->dev->kfd2kgd-
>> hqd_sdma_get_doorbell(dqm->dev->adev, i, j) ||
>>>    			    !set_sdma_queue_as_reset(dqm,
> doorbell_off)) {
>>>    				
>>>    				r = -ENOTRECOVERABLE;
> 
> 
> 
> 


^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2026-09-08  3:25 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-04  7:28 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v3) Timur Kristóf
2026-09-04  7:28 ` [PATCH 1/8] drm/amdgpu/sdma: Remove unimplemented soft_reset() for SDMA and SI DMA Timur Kristóf
2026-09-04  7:28 ` [PATCH 2/8] drm/amdgpu/sdma: Remove superfluous rlc_resume and rlc_stop functions Timur Kristóf
2026-09-04  7:28 ` [PATCH 3/8] drm/amdgpu/sdma: Fix executing duplicate commands after recovery on SDMA v4.4.2 Timur Kristóf
2026-09-04  7:28 ` [PATCH 4/8] drm/amdgpu/sdma: Remove unnecessary guilty tracking of SDMA queues Timur Kristóf
2026-09-04  7:28 ` [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Timur Kristóf
2026-09-07  7:04   ` Lazar, Lijo
2026-09-07 18:31     ` Timur Kristóf
2026-09-04  7:28 ` [PATCH 6/8] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code Timur Kristóf
2026-09-04  7:28 ` [PATCH 7/8] drm/amdgpu/sdma: Always handle kernel queues in amdgpu_sdma_reset_engine() Timur Kristóf
2026-09-07  7:17   ` Lazar, Lijo
2026-09-07 18:34     ` Timur Kristóf
2026-09-08  3:25       ` Lazar, Lijo
2026-09-04  7:28 ` [PATCH 8/8] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2 Timur Kristóf
  -- strict thread matches above, loose matches on Subject: below --
2026-09-01  8:41 [PATCH 0/8] drm/amdgpu/sdma: Improve existing SDMA queue resets (v2) Timur Kristóf
2026-09-01  8:41 ` [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Timur Kristóf

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