[PATCH 1/4] drm/amd/pm: add smu pcie dpm cap & width convert helper

[PATCH 1/4] drm/amd/pm: add smu pcie dpm cap & width convert helper

[Yang Wang]

define following heler to convert pmfw pcie dpm index to smu index.
- SMU_DPM_PCIE_GEN_IDX(gen)
- SMU_DPM_PCIE_WIDTH_IDX(width)

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 50 ++++++++++++++++++++++++++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h |  6 ++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index b606829a1f3f..732dadc4ebbf 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -1346,3 +1346,53 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
 
 	return 0;
 }
+
+int smu_cmn_dpm_pcie_gen_idx(int gen)
+{
+	int ret;
+
+	switch (gen) {
+	case 1 ... 5:
+		ret = gen - 1;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+int smu_cmn_dpm_pcie_width_idx(int width)
+{
+	int ret;
+
+	switch (width) {
+	case 1:
+		ret = 1;
+		break;
+	case 2:
+		ret = 2;
+		break;
+	case 4:
+		ret = 3;
+		break;
+	case 8:
+		ret = 4;
+		break;
+	case 12:
+		ret = 5;
+		break;
+	case 16:
+		ret = 6;
+		break;
+	case 32:
+		ret = 7;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index f458125e8d4e..3a8d05afa654 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -93,6 +93,9 @@
 		header->structure_size = sizeof(*tmp);                          \
 	} while (0)
 
+#define SMU_DPM_PCIE_GEN_IDX(gen)	smu_cmn_dpm_pcie_gen_idx((gen))
+#define SMU_DPM_PCIE_WIDTH_IDX(width)	smu_cmn_dpm_pcie_width_idx((width))
+
 extern const int link_speed[];
 
 /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
@@ -212,6 +215,9 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
 			       uint32_t cur_gen, uint32_t cur_lane,
 			       char *buf, int *offset);
 
+int smu_cmn_dpm_pcie_gen_idx(int gen);
+int smu_cmn_dpm_pcie_width_idx(int width);
+
 /*SMU gpu metrics */
 
 /* Attribute ID mapping */
-- 
2.34.1

[PATCH 2/4] drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v14.0.2

[Yang Wang]

put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v14.0.2:
smu_cmn_print_pcie_levels()

Fixes: 55fc561a1955 ("drm/amd/pm: Use common helper for smuv14.0.2 dpm")

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index d996ff69c60a..4a2a56758bc2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -1095,8 +1095,10 @@ static int smu_v14_0_2_emit_clk_levels(struct smu_context *smu,
 			return ret;
 
 		pcie_table = &(dpm_context->dpm_tables.pcie_table);
-		return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed,
-						 lane_width, buf, offset);
+		return smu_cmn_print_pcie_levels(smu, pcie_table,
+						 SMU_DPM_PCIE_GEN_IDX(gen_speed),
+						 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
+						 buf, offset);
 
 	case SMU_OD_SCLK:
 		if (!smu_v14_0_2_is_od_feature_supported(smu,
-- 
2.34.1

[PATCH 3/4] drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.0

[Yang Wang]

put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v13.0.0:
smu_cmn_print_pcie_levels()

Fixes: 5ab288d9e21e ("drm/amd/pm: Use common helper for smuv13.0.0 dpm")

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index aee365bcdbff..faa577aebd89 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1255,8 +1255,10 @@ static int smu_v13_0_0_emit_clk_levels(struct smu_context *smu,
 			return ret;
 
 		pcie_table = &(dpm_context->dpm_tables.pcie_table);
-		return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed,
-						 lane_width, buf, offset);
+		return smu_cmn_print_pcie_levels(smu, pcie_table,
+						 SMU_DPM_PCIE_GEN_IDX(gen_speed),
+						 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
+						 buf, offset);
 	case SMU_OD_SCLK:
 		if (!smu_v13_0_0_is_od_feature_supported(smu,
 							 PP_OD_FEATURE_GFXCLK_BIT))
-- 
2.34.1

[PATCH 4/4] drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.7

[Yang Wang]

put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v13.0.7:
smu_cmn_print_pcie_levels()

Fixes: b60647c37084 ("drm/amd/pm: Use common helper for smuv13.0.7 dpm")

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 30bac969d565..135328121630 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1223,8 +1223,10 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu,
 			return ret;
 
 		pcie_table = &(dpm_context->dpm_tables.pcie_table);
-		return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed,
-						 lane_width, buf, offset);
+		return smu_cmn_print_pcie_levels(smu, pcie_table,
+						 SMU_DPM_PCIE_GEN_IDX(gen_speed),
+						 SMU_DPM_PCIE_WIDTH_IDX(lane_width),
+						 buf, offset);
 	case SMU_OD_SCLK:
 		if (!smu_v13_0_7_is_od_feature_supported(smu,
 							 PP_OD_FEATURE_GFXCLK_BIT))
-- 
2.34.1

Re: [PATCH 1/4] drm/amd/pm: add smu pcie dpm cap & width convert helper

[Lazar, Lijo]

On 12/11/2025 10:45 AM, Yang Wang wrote:
> define following heler to convert pmfw pcie dpm index to smu index.
> - SMU_DPM_PCIE_GEN_IDX(gen)
> - SMU_DPM_PCIE_WIDTH_IDX(width)
> 
> Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 50 ++++++++++++++++++++++++++
>   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h |  6 ++++
>   2 files changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index b606829a1f3f..732dadc4ebbf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -1346,3 +1346,53 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
>   
>   	return 0;
>   }
> +
> +int smu_cmn_dpm_pcie_gen_idx(int gen)
> +{
> +	int ret;
> +
> +	switch (gen) {
> +	case 1 ... 5:
> +		ret = gen - 1;
> +		break;
> +	default:
> +		ret = -1;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +int smu_cmn_dpm_pcie_width_idx(int width)
> +{
> +	int ret;
> +
> +	switch (width) {
> +	case 1:
> +		ret = 1;
> +		break;
> +	case 2:
> +		ret = 2;
> +		break;
> +	case 4:
> +		ret = 3;
> +		break;
> +	case 8:
> +		ret = 4;
> +		break;
> +	case 12:
> +		ret = 5;
> +		break;
> +	case 16:
> +		ret = 6;
> +		break;
> +	case 32:
> +		ret = 7;
> +		break;
> +	default:
> +		ret = -1;
> +		break;
> +	}
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> index f458125e8d4e..3a8d05afa654 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> @@ -93,6 +93,9 @@
>   		header->structure_size = sizeof(*tmp);                          \
>   	} while (0)
>   
> +#define SMU_DPM_PCIE_GEN_IDX(gen)	smu_cmn_dpm_pcie_gen_idx((gen))
> +#define SMU_DPM_PCIE_WIDTH_IDX(width)	smu_cmn_dpm_pcie_width_idx((width))

Are these macros really needed, can't the functions be directly used?

Regardless, series is -

	Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>

Thanks,
Lijo

> +
>   extern const int link_speed[];
>   
>   /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */
> @@ -212,6 +215,9 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
>   			       uint32_t cur_gen, uint32_t cur_lane,
>   			       char *buf, int *offset);
>   
> +int smu_cmn_dpm_pcie_gen_idx(int gen);
> +int smu_cmn_dpm_pcie_width_idx(int width);
> +
>   /*SMU gpu metrics */
>   
>   /* Attribute ID mapping */

RE: [PATCH 1/4] drm/amd/pm: add smu pcie dpm cap & width convert helper

[Wang, Yang(Kevin)]

[AMD Official Use Only - AMD Internal Distribution Only]

>> Are these macros really needed, can't the functions be directly used?

I want to hide the implementation details, which are currently universal, but I am not sure if they will be universal in all upcoming Asics.
if yes, this macro definition can be modified to per asic.

Best Regards,
Kevin
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Thursday, December 11, 2025 15:47
To: Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 1/4] drm/amd/pm: add smu pcie dpm cap & width convert helper



On 12/11/2025 10:45 AM, Yang Wang wrote:
> define following heler to convert pmfw pcie dpm index to smu index.
> - SMU_DPM_PCIE_GEN_IDX(gen)
> - SMU_DPM_PCIE_WIDTH_IDX(width)
>
> Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 50 ++++++++++++++++++++++++++
>   drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h |  6 ++++
>   2 files changed, 56 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index b606829a1f3f..732dadc4ebbf 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -1346,3 +1346,53 @@ int smu_cmn_print_pcie_levels(struct
> smu_context *smu,
>
>       return 0;
>   }
> +
> +int smu_cmn_dpm_pcie_gen_idx(int gen) {
> +     int ret;
> +
> +     switch (gen) {
> +     case 1 ... 5:
> +             ret = gen - 1;
> +             break;
> +     default:
> +             ret = -1;
> +             break;
> +     }
> +
> +     return ret;
> +}
> +
> +int smu_cmn_dpm_pcie_width_idx(int width) {
> +     int ret;
> +
> +     switch (width) {
> +     case 1:
> +             ret = 1;
> +             break;
> +     case 2:
> +             ret = 2;
> +             break;
> +     case 4:
> +             ret = 3;
> +             break;
> +     case 8:
> +             ret = 4;
> +             break;
> +     case 12:
> +             ret = 5;
> +             break;
> +     case 16:
> +             ret = 6;
> +             break;
> +     case 32:
> +             ret = 7;
> +             break;
> +     default:
> +             ret = -1;
> +             break;
> +     }
> +
> +     return ret;
> +}
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> index f458125e8d4e..3a8d05afa654 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
> @@ -93,6 +93,9 @@
>               header->structure_size = sizeof(*tmp);                          \
>       } while (0)
>
> +#define SMU_DPM_PCIE_GEN_IDX(gen)    smu_cmn_dpm_pcie_gen_idx((gen))
> +#define SMU_DPM_PCIE_WIDTH_IDX(width)        smu_cmn_dpm_pcie_width_idx((width))

Are these macros really needed, can't the functions be directly used?

Regardless, series is -

        Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>

Thanks,
Lijo

> +
>   extern const int link_speed[];
>
>   /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed
> units */ @@ -212,6 +215,9 @@ int smu_cmn_print_pcie_levels(struct smu_context *smu,
>                              uint32_t cur_gen, uint32_t cur_lane,
>                              char *buf, int *offset);
>
> +int smu_cmn_dpm_pcie_gen_idx(int gen); int
> +smu_cmn_dpm_pcie_width_idx(int width);
> +
>   /*SMU gpu metrics */
>
>   /* Attribute ID mapping */