From: "Christian König" <christian.koenig@amd.com>
To: Satyajit Sahu <satyajit.sahu@amd.com>, amd-gfx@lists.freedesktop.org
Cc: leo.liu@amd.com, Alexander.Deucher@amd.com,
shashank.sharma@amd.com, nirmoy.das@amd.com
Subject: Re: [PATCH 5/5] drm/amdgpu/vcn/vce:schedule encode job based on priorrity
Date: Tue, 24 Aug 2021 08:14:07 +0200 [thread overview]
Message-ID: <e55e35da-d513-b8c7-95f2-49edd9026fe8@amd.com> (raw)
In-Reply-To: <20210824055510.1189185-5-satyajit.sahu@amd.com>
Am 24.08.21 um 07:55 schrieb Satyajit Sahu:
> Schedule the encode job properly in the VCE/VCN encode
> rings based on the priority set by UMD.
>
> Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++++++++++++++++++++++--
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 5 ++--
> 8 files changed, 58 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index e7a010b7ca1f..adc11bb81787 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -73,15 +73,49 @@ static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sch
> }
> }
>
> +static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_vcn_prio(enum drm_sched_priority prio)
> +{
> + switch (prio) {
> + case DRM_SCHED_PRIORITY_HIGH:
> + return AMDGPU_VCN_ENC_PRIO_HIGH;
> + case DRM_SCHED_PRIORITY_VERY_HIGH:
> + return AMDGPU_VCN_ENC_PRIO_VERY_HIGH;
> + default:
> + return AMDGPU_VCN_ENC_PRIO_NORMAL;
> + }
> +}
> +
> +static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_vce_prio(enum drm_sched_priority prio)
> +{
> + switch (prio) {
> + case DRM_SCHED_PRIORITY_HIGH:
> + return AMDGPU_VCE_ENC_PRIO_HIGH;
> + case DRM_SCHED_PRIORITY_VERY_HIGH:
> + return AMDGPU_VCE_ENC_PRIO_VERY_HIGH;
> + default:
> + return AMDGPU_VCE_ENC_PRIO_NORMAL;
> + }
> +}
> +
> static unsigned int amdgpu_ctx_prio_sched_to_hw(struct amdgpu_device *adev,
> enum drm_sched_priority prio,
> u32 hw_ip)
> {
> unsigned int hw_prio;
>
> - hw_prio = (hw_ip == AMDGPU_HW_IP_COMPUTE) ?
> - amdgpu_ctx_sched_prio_to_compute_prio(prio) :
> - AMDGPU_RING_PRIO_DEFAULT;
> + switch(hw_ip) {
> + case AMDGPU_HW_IP_COMPUTE:
> + hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(prio);
> + break;
> + case AMDGPU_HW_IP_VCN_ENC:
> + hw_prio = amdgpu_ctx_sched_prio_to_vcn_prio(prio);
> + break;
> + case AMDGPU_HW_IP_VCE:
> + hw_prio = amdgpu_ctx_sched_prio_to_vce_prio(prio);
> + break;
> + default:
> + hw_prio = AMDGPU_RING_PRIO_DEFAULT;
> + }
Ok now I see where your confusion is coming from. Those functions here
should not work with the scheduler priority to begin with.
> hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM);
> if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0)
> hw_prio = AMDGPU_RING_PRIO_DEFAULT;
The rest of the changes starting from here should not be part of this
patch, but rather of the respectively VCN/VCE changes.
Regards,
Christian.
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index c7d28c169be5..2b6b7f1a77b9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -431,10 +431,12 @@ static int vce_v2_0_sw_init(void *handle)
> return r;
>
> for (i = 0; i < adev->vce.num_rings; i++) {
> + unsigned int hw_prio = get_vce_ring_prio(i);
> +
> ring = &adev->vce.ring[i];
> sprintf(ring->name, "vce%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 3b82fb289ef6..5ce182a837f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -440,10 +440,12 @@ static int vce_v3_0_sw_init(void *handle)
> return r;
>
> for (i = 0; i < adev->vce.num_rings; i++) {
> + unsigned int hw_prio = get_vce_ring_prio(i);
> +
> ring = &adev->vce.ring[i];
> sprintf(ring->name, "vce%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 90910d19db12..c085defaabfe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -463,6 +463,8 @@ static int vce_v4_0_sw_init(void *handle)
> }
>
> for (i = 0; i < adev->vce.num_rings; i++) {
> + unsigned int hw_prio = get_vce_ring_prio(i);
> +
> ring = &adev->vce.ring[i];
> sprintf(ring->name, "vce%d", i);
> if (amdgpu_sriov_vf(adev)) {
> @@ -478,7 +480,7 @@ static int vce_v4_0_sw_init(void *handle)
> ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 * 2 + 1;
> }
> r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 284bb42d6c86..a41b2c40487e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -145,10 +145,12 @@ static int vcn_v1_0_sw_init(void *handle)
> SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
>
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> + unsigned int hw_prio = get_vcn_enc_ring_prio(i);
> +
> ring = &adev->vcn.inst->ring_enc[i];
> sprintf(ring->name, "vcn_enc%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8af567c546db..9729a383786b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -159,6 +159,8 @@ static int vcn_v2_0_sw_init(void *handle)
> adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
>
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> + unsigned int hw_prio = get_vcn_enc_ring_prio(i);
> +
> ring = &adev->vcn.inst->ring_enc[i];
> ring->use_doorbell = true;
> if (!amdgpu_sriov_vf(adev))
> @@ -167,7 +169,7 @@ static int vcn_v2_0_sw_init(void *handle)
> ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
> sprintf(ring->name, "vcn_enc%d", i);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 888b17d84691..9eca70d3ff30 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -194,6 +194,8 @@ static int vcn_v2_5_sw_init(void *handle)
> return r;
>
> for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> + unsigned int hw_prio = get_vcn_enc_ring_prio(i);
> +
> ring = &adev->vcn.inst[j].ring_enc[i];
> ring->use_doorbell = true;
>
> @@ -203,7 +205,7 @@ static int vcn_v2_5_sw_init(void *handle)
> sprintf(ring->name, "vcn_enc_%d.%d", j, i);
> r = amdgpu_ring_init(adev, ring, 512,
> &adev->vcn.inst[j].irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT, NULL);
> + hw_prio, NULL);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 47d4f04cbd69..926c9f4bfc21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -227,6 +227,8 @@ static int vcn_v3_0_sw_init(void *handle)
> return r;
>
> for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
> + unsigned int hw_prio = get_vcn_enc_ring_prio(j);
> +
> /* VCN ENC TRAP */
> r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
> j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
> @@ -242,8 +244,7 @@ static int vcn_v3_0_sw_init(void *handle)
> }
> sprintf(ring->name, "vcn_enc_%d.%d", i, j);
> r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
> - AMDGPU_RING_PRIO_DEFAULT,
> - &adev->vcn.inst[i].sched_score);
> + hw_prio, &adev->vcn.inst[i].sched_score);
> if (r)
> return r;
> }
next prev parent reply other threads:[~2021-08-24 6:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-24 5:55 [PATCH 1/5] drm/sched:add new priority level Satyajit Sahu
2021-08-24 5:55 ` [PATCH 2/5] drm/amdgpu: map user set priority to drm sched priority Satyajit Sahu
2021-08-24 5:55 ` [PATCH 3/5] drm/amdgpu/vce:set vce ring priority level Satyajit Sahu
2021-08-24 6:09 ` Christian König
2021-08-24 5:55 ` [PATCH 4/5] drm/amdgpu/vcn:set vcn encode " Satyajit Sahu
2021-08-24 5:55 ` [PATCH 5/5] drm/amdgpu/vcn/vce:schedule encode job based on priorrity Satyajit Sahu
2021-08-24 6:14 ` Christian König [this message]
2021-08-24 6:10 ` [PATCH 1/5] drm/sched:add new priority level Christian König
2021-08-24 8:32 ` Sharma, Shashank
2021-08-24 8:55 ` Christian König
2021-08-24 9:45 ` Sharma, Shashank
2021-08-24 11:56 ` Christian König
2021-08-24 11:57 ` Das, Nirmoy
2021-08-24 12:07 ` Christian König
2021-08-24 12:39 ` Das, Nirmoy
2021-08-24 13:18 ` Christian König
2021-08-24 13:23 ` Das, Nirmoy
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